Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573462
Janakiraman Viraraghavan, D. Leu, Balaji Jayaraman, A. Cestero, Robert Kilker, M. Yin, J. Golz, R. R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, F. Khan, T. Kirihata, S. Iyer
An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.
{"title":"80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity","authors":"Janakiraman Viraraghavan, D. Leu, Balaji Jayaraman, A. Cestero, Robert Kilker, M. Yin, J. Golz, R. R. Tummuru, Ramesh Raghavan, D. Moy, Thejas Kempanna, F. Khan, T. Kirihata, S. Iyer","doi":"10.1109/VLSIC.2016.7573462","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573462","url":null,"abstract":"An 80Kb logic Embedded Multi-Time Programmable Memory (MTPM) employs charge trapping and de-trapping behavior in 32nm/22nm High-K transistor, resulting in no added process complexity. Multi-step verification with overwrite protection employs block-write and signal margin degradation (~30%) to satisfy 10 year retention at 105° C.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1998 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82772883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573508
T. Meister, K. Ishida, C. Carta, R. Shabanpour, B. K. Boroujeni, N. Münzenrieder, L. Petti, G. Salvatore, G. Schmidt, Pol Ghesquière, S. Kiefl, G. Toma, T. Faetti, A. Hübler, G. Tröster, F. Ellinger
We developed a fully flexible AM (amplitude modulation) radio receiver suitable for integration in an “audio bag”, by exploiting the heterogeneous integration of several fully flexible technologies. In this paper, we present a 2.9 mW 2-bit digitally-controlled tuner with a 576 kHz tuning range, a 3.5 mW 1 MHz AM detector and their integration in such a fully-flexible system. Their optimized power consumptions are essential because thin flexible batteries and organic solar cells serve as power supply. The circuits are fabricated in a low-temperature amorphous indium gallium zinc oxide (a-IGZO) technology. For the system integration textile techniques as well as flexible inkjet-printed packages and printed circuit boards (IPCBs) were used.
{"title":"3.5mW 1MHz AM detector and digitally-controlled tuner in a-IGZO TFT for wireless communications in a fully integrated flexible system for audio bag","authors":"T. Meister, K. Ishida, C. Carta, R. Shabanpour, B. K. Boroujeni, N. Münzenrieder, L. Petti, G. Salvatore, G. Schmidt, Pol Ghesquière, S. Kiefl, G. Toma, T. Faetti, A. Hübler, G. Tröster, F. Ellinger","doi":"10.1109/VLSIC.2016.7573508","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573508","url":null,"abstract":"We developed a fully flexible AM (amplitude modulation) radio receiver suitable for integration in an “audio bag”, by exploiting the heterogeneous integration of several fully flexible technologies. In this paper, we present a 2.9 mW 2-bit digitally-controlled tuner with a 576 kHz tuning range, a 3.5 mW 1 MHz AM detector and their integration in such a fully-flexible system. Their optimized power consumptions are essential because thin flexible batteries and organic solar cells serve as power supply. The circuits are fabricated in a low-temperature amorphous indium gallium zinc oxide (a-IGZO) technology. For the system integration textile techniques as well as flexible inkjet-printed packages and printed circuit boards (IPCBs) were used.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"17 3 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83549668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The proposed single-inductor dual-output (SIDO) converter can provide wide range in duty ratio control to convert input voltage 5-20V to dual output voltages 3.3V and 1.2V when its switching frequency is raised to 10MHz for compact size solution. The proposed synthesized waveform control (SWC) technique can emulate the inductor current without being affected by switching noise. Thus, the minimum allowable duty ratio can be lowered to 6% to meet the requirement of USB-C in one-stage low duty ratio conversion. Moreover, the switching frequency is dynamically decreased by the derived DC loading information from the SWC technique. Not only the output power MOSFET but also the main power MOSFET switch in a load-dependent switching frequency for power saving. 67% more power reduction can be obtained. 95% and 83% efficiency are achieved at light and heavy loads, respectively, when the silicon is limited within 1400μm*1350μm.
{"title":"95% light-load efficiency single-inductor dual-output DC-DC buck converter with synthesized waveform control technique for USB type-C","authors":"Wen-Hau Yang, Chiun-He Lin, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai, Jui-Lung Chen","doi":"10.1109/VLSIC.2016.7573476","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573476","url":null,"abstract":"The proposed single-inductor dual-output (SIDO) converter can provide wide range in duty ratio control to convert input voltage 5-20V to dual output voltages 3.3V and 1.2V when its switching frequency is raised to 10MHz for compact size solution. The proposed synthesized waveform control (SWC) technique can emulate the inductor current without being affected by switching noise. Thus, the minimum allowable duty ratio can be lowered to 6% to meet the requirement of USB-C in one-stage low duty ratio conversion. Moreover, the switching frequency is dynamically decreased by the derived DC loading information from the SWC technique. Not only the output power MOSFET but also the main power MOSFET switch in a load-dependent switching frequency for power saving. 67% more power reduction can be obtained. 95% and 83% efficiency are achieved at light and heavy loads, respectively, when the silicon is limited within 1400μm*1350μm.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79870893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573469
Jong Seok Park, T. Chi, Amy Su, Chengjie Zhu, J. H. Sung, H. Cho, Mark P. Styczynski, Hua Wang
This paper presents a fully integrated 1024-pixel world-first joint multi-modality sensor/stimulator array in CMOS for holistic real-time cell characterization. Each pixel supports extracellular voltage recording, optical detection, and cellular impedance measurement, as well as current-mode cellular stimulation. Four independent on-chip temperature sensors monitor the ambient temperature variation. The chip is implemented in a 130nm CMOS process with a pixel size of 58μm×58μm, achieving the largest array-size and smallest pixel for a multi-modality joint sensor/stimulator array in CMOS. The electrical and biological measurements demonstrate the utility of this high-density multi-modality array in cell-based assays for drug and chemical screening.
{"title":"A high-density CMOS multi-modality joint sensor/stimulator array with 1024 pixels for holistic real-time cellular characterization","authors":"Jong Seok Park, T. Chi, Amy Su, Chengjie Zhu, J. H. Sung, H. Cho, Mark P. Styczynski, Hua Wang","doi":"10.1109/VLSIC.2016.7573469","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573469","url":null,"abstract":"This paper presents a fully integrated 1024-pixel world-first joint multi-modality sensor/stimulator array in CMOS for holistic real-time cell characterization. Each pixel supports extracellular voltage recording, optical detection, and cellular impedance measurement, as well as current-mode cellular stimulation. Four independent on-chip temperature sensors monitor the ambient temperature variation. The chip is implemented in a 130nm CMOS process with a pixel size of 58μm×58μm, achieving the largest array-size and smallest pixel for a multi-modality joint sensor/stimulator array in CMOS. The electrical and biological measurements demonstrate the utility of this high-density multi-modality array in cell-based assays for drug and chemical screening.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"289 2 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72913040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573534
Yan Hong, Yong Wang, W. Goh, Yuan Gao, Lei Yao
A new time-domain impedance sensor readout circuit based on 0.18-μm CMOS technology is presented. A current DAC is used to charge the device under test (DUT) to increase the node voltage of the DUT. Using a time-domain comparator and a counter, a time period between the start of charge till the moment that the node voltage reaches a reference level is recorded and digitally converted. The resistance and capacitance components of the impedance can be quantized by using the time period data. The fabricated prototype consumes only 9.84 to 73.2 nJ of energy and requires merely 3 ms per measurement, where both are >103 times' reductions as compared to the state-of-the-arts. Moreover, to the best of the authors' knowledge, this proposed readout chip is the first of its kind that is able to deduce each resistance and capacitance component of the impedance. The chip takes up 0.048-mm2 of area.
{"title":"A 9.84–73.2 nJ, 0.048 mm2 time-domain impedance sensor that provides values of resistance and capacitance","authors":"Yan Hong, Yong Wang, W. Goh, Yuan Gao, Lei Yao","doi":"10.1109/VLSIC.2016.7573534","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573534","url":null,"abstract":"A new time-domain impedance sensor readout circuit based on 0.18-μm CMOS technology is presented. A current DAC is used to charge the device under test (DUT) to increase the node voltage of the DUT. Using a time-domain comparator and a counter, a time period between the start of charge till the moment that the node voltage reaches a reference level is recorded and digitally converted. The resistance and capacitance components of the impedance can be quantized by using the time period data. The fabricated prototype consumes only 9.84 to 73.2 nJ of energy and requires merely 3 ms per measurement, where both are >103 times' reductions as compared to the state-of-the-arts. Moreover, to the best of the authors' knowledge, this proposed readout chip is the first of its kind that is able to deduce each resistance and capacitance component of the impedance. The chip takes up 0.048-mm2 of area.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"157 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75104047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573526
Phil C. Knag, Chester Liu, Zhengya Zhang
Sparsity is a brain-inspired property that enables a significant reduction in workload and power dissipation of deep learning. This work presents a 1.40mm2 40nm CMOS sparse neuromorphic processor that implements a two-layer convolutional restricted Boltzmann machine (CRBM) for inference and a support vector machine (SVM) classifier. The processor incorporates sparse convolvers to realize sparsity-proportional workload reduction. The architecture is parallelized along a non-sparse dimension to minimize stalling. At 0.9V and 240MHz, the processor achieves an effective 898.2GOPS performance, dissipating 140.9mW. Using sparsity, we reduce the workload, datapath power consumption and area by 3.4×, 3.3× and 1.74×, respectively. The design uses latch-based memory to reduce area and dynamic clock gating to save power.
{"title":"A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS","authors":"Phil C. Knag, Chester Liu, Zhengya Zhang","doi":"10.1109/VLSIC.2016.7573526","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573526","url":null,"abstract":"Sparsity is a brain-inspired property that enables a significant reduction in workload and power dissipation of deep learning. This work presents a 1.40mm2 40nm CMOS sparse neuromorphic processor that implements a two-layer convolutional restricted Boltzmann machine (CRBM) for inference and a support vector machine (SVM) classifier. The processor incorporates sparse convolvers to realize sparsity-proportional workload reduction. The architecture is parallelized along a non-sparse dimension to minimize stalling. At 0.9V and 240MHz, the processor achieves an effective 898.2GOPS performance, dissipating 140.9mW. Using sparsity, we reduce the workload, datapath power consumption and area by 3.4×, 3.3× and 1.74×, respectively. The design uses latch-based memory to reduce area and dynamic clock gating to save power.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"16 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75581574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573496
S. Ujita, Y. Kinoshita, H. Umeda, T. Morita, K. Kaibara, S. Tamura, M. Ishida, T. Ueda
In this paper, we present a state-of-the-art integrated GaN power IC capable of operating in a high frequency (MHz) regime. This realizes system size reduction, 60% maximum, of a power IC. The IC consists of two output power transistors (PT) and two gate drivers (GD). The key devices in the IC are normally-off gate injection transistors (GITs) for PT and GD and a normally-on hetero-junction field effect transistor (HFET) for GD. Novel local control of carrier concentration of an identical 2 dimensional electron gas (2DEG) at an AlGaN/GaN interface which made integration of the transistors with such a large threshold voltage difference possible is described. A specially developed post-passivation interconnection process giving low parasitic components is also described. The IC applied to a 12V-1.8V DC-DC converter shows high frequency switching operation well beyond the limit of Si pointing to future improvement in consumer electronics power supply systems.
{"title":"A fully integrated GaN-based power IC including gate drivers for high-efficiency DC-DC Converters","authors":"S. Ujita, Y. Kinoshita, H. Umeda, T. Morita, K. Kaibara, S. Tamura, M. Ishida, T. Ueda","doi":"10.1109/VLSIC.2016.7573496","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573496","url":null,"abstract":"In this paper, we present a state-of-the-art integrated GaN power IC capable of operating in a high frequency (MHz) regime. This realizes system size reduction, 60% maximum, of a power IC. The IC consists of two output power transistors (PT) and two gate drivers (GD). The key devices in the IC are normally-off gate injection transistors (GITs) for PT and GD and a normally-on hetero-junction field effect transistor (HFET) for GD. Novel local control of carrier concentration of an identical 2 dimensional electron gas (2DEG) at an AlGaN/GaN interface which made integration of the transistors with such a large threshold voltage difference possible is described. A specially developed post-passivation interconnection process giving low parasitic components is also described. The IC applied to a 12V-1.8V DC-DC converter shows high frequency switching operation well beyond the limit of Si pointing to future improvement in consumer electronics power supply systems.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"20 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73367158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573475
Xun Liu, Cheng Huang, P. Mok
In this paper, a 50-MHz 5-V input 3-W output 3-level buck converter is presented. A real-time flying capacitor (CF) calibration is proposed to ensure a constant Vg/2 voltage across the CF, which is essential to ensure the reliability and maintain the advantages of 3-level converters. A 0.6-4.2V wide output range, a 90% peak efficiency and a 23-29ns/V reference tracking response are observed in measurements with 65nm process. A significantly reduced VO ripple is achieved after enabling the proposed calibration.
{"title":"A 50MHz 5V 3W 90% efficiency 3-level buck converter with real-time calibration and wide output range for fast-DVS in 65nm CMOS","authors":"Xun Liu, Cheng Huang, P. Mok","doi":"10.1109/VLSIC.2016.7573475","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573475","url":null,"abstract":"In this paper, a 50-MHz 5-V input 3-W output 3-level buck converter is presented. A real-time flying capacitor (CF) calibration is proposed to ensure a constant Vg/2 voltage across the CF, which is essential to ensure the reliability and maintain the advantages of 3-level converters. A 0.6-4.2V wide output range, a 90% peak efficiency and a 23-29ns/V reference tracking response are observed in measurements with 65nm process. A significantly reduced VO ripple is achieved after enabling the proposed calibration.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"34 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73337381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573465
A. Sanyal, Nan Sun
A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply.
{"title":"A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration","authors":"A. Sanyal, Nan Sun","doi":"10.1109/VLSIC.2016.7573465","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573465","url":null,"abstract":"A scaling-friendly and energy-efficient 0-1 MASH ΔΣ ADC is proposed in this work. An 8b SAR is used as the 1st stage for coarse quantization. A ring VCO is used as the 2nd stage for fine quantization. The proposed ADC uses digital background calibration to track VCO gain variation across PVT. A 40nm CMOS prototype achieves a Walden FoM of 18.5 fJ/conv-step while operating from 1.1V supply.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"119 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75802082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573558
X. Yuan, S. Kim, J. Juyon, M. D'Urbino, Torsten Bullmann, Yihui Chen, A. Stettler, A. Hierlemann, U. Frey
CMOS microelectrode arrays allow for recording from neurons at thousands of sites. Here, we introduce the concept of a `dual-mode operation' microelectrode array, leveraging the advantages of full-frame scanning and switch-matrix array architectures into a single device. The chip was fabricated in 0.18 μm CMOS technology. Measured noise levels were 11.1 μVrms for full-frame scanning and 1.6 μVrms for switch-matrix mode at 3.3 μW and 38.1 μW per channel power consumption. Recordings of electrical activity from cultured neurons have been successfully conducted.
{"title":"A microelectrode array with 8,640 electrodes enabling simultaneous full-frame readout at 6.5 kfps and 112-channel switch-matrix readout at 20 kS/s","authors":"X. Yuan, S. Kim, J. Juyon, M. D'Urbino, Torsten Bullmann, Yihui Chen, A. Stettler, A. Hierlemann, U. Frey","doi":"10.1109/VLSIC.2016.7573558","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573558","url":null,"abstract":"CMOS microelectrode arrays allow for recording from neurons at thousands of sites. Here, we introduce the concept of a `dual-mode operation' microelectrode array, leveraging the advantages of full-frame scanning and switch-matrix array architectures into a single device. The chip was fabricated in 0.18 μm CMOS technology. Measured noise levels were 11.1 μVrms for full-frame scanning and 1.6 μVrms for switch-matrix mode at 3.3 μW and 38.1 μW per channel power consumption. Recordings of electrical activity from cultured neurons have been successfully conducted.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"30 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72931426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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