Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573504
T. Onuki, W. Uesugi, H. Tamura, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, Chen Bin Lin, J. Y. Wu, C. Shuai, Shao Hui Wu, James Myers, K. Doppler, M. Fujita, S. Yamazaki
Low-power embedded memory and an ARM Cortex-M0 core that operate at 30 MHz were fabricated in combination with a 60-nm c-axis aligned crystalline indium-gallium-zinc oxide FET and a 65-nm Si CMOS. The embedded memory adopted a structure in which oxide semiconductor-based 1T1C cells are stacked on Si sense amplifiers. This memory achieved a standby power of 3 nW while retaining data and an active power of 11.7 μW/MHz by making each bitline as short as each sense amplifier. The M0 core adopted the flip-flop in which an oxide semiconductor-based 3T1C cell is stacked on the Si scan flip-flop cell without area overhead and achieved a standby power of 6 nW while retaining data. The combination of the embedded memory and the M0 core provided high-performance, low-power Internet of Things devices operating with a broad range of active standby power ratios.
低功耗嵌入式存储器和工作频率为30 MHz的ARM Cortex-M0内核由60 nm c轴排列晶体铟镓氧化锌场效应管和65 nm Si CMOS组合而成。嵌入式存储器采用的结构是基于氧化物半导体的1T1C单元堆叠在硅感测放大器上。通过使每个位线与每个感测放大器一样短，该存储器在保留数据的同时实现了3nw的待机功率和11.7 μW/MHz的有功功率。M0核心采用了触发器，其中基于氧化物半导体的3T1C电池堆叠在Si扫描触发器电池上，没有面积开销，在保留数据的情况下实现了6 nW的待机功率。嵌入式存储器和M0核心的结合提供了高性能，低功耗的物联网设备，具有广泛的工作待机功率比。
{"title":"Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS","authors":"T. Onuki, W. Uesugi, H. Tamura, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, Chen Bin Lin, J. Y. Wu, C. Shuai, Shao Hui Wu, James Myers, K. Doppler, M. Fujita, S. Yamazaki","doi":"10.1109/VLSIC.2016.7573504","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573504","url":null,"abstract":"Low-power embedded memory and an ARM Cortex-M0 core that operate at 30 MHz were fabricated in combination with a 60-nm c-axis aligned crystalline indium-gallium-zinc oxide FET and a 65-nm Si CMOS. The embedded memory adopted a structure in which oxide semiconductor-based 1T1C cells are stacked on Si sense amplifiers. This memory achieved a standby power of 3 nW while retaining data and an active power of 11.7 μW/MHz by making each bitline as short as each sense amplifier. The M0 core adopted the flip-flop in which an oxide semiconductor-based 3T1C cell is stacked on the Si scan flip-flop cell without area overhead and achieved a standby power of 6 nW while retaining data. The combination of the embedded memory and the M0 core provided high-performance, low-power Internet of Things devices operating with a broad range of active standby power ratios.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"44 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78570595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573529
M. Cho, Carlos Tokunaga, Stephen T. Kim, J. Tschanz, M. Khellah, V. De
Combining adaptive clocking with dynamic power gating in an optimal manner mitigates energy efficiency and performance impacts of fast supply voltage droop in a 22nm graphics execution core more effectively than adaptive clocking alone. Measurements show that there is an optimal VMIN where the combination provides the best improvement - 14% lower energy at 890MHz vs. 4% with adaptive clocking.
{"title":"Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core","authors":"M. Cho, Carlos Tokunaga, Stephen T. Kim, J. Tschanz, M. Khellah, V. De","doi":"10.1109/VLSIC.2016.7573529","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573529","url":null,"abstract":"Combining adaptive clocking with dynamic power gating in an optimal manner mitigates energy efficiency and performance impacts of fast supply voltage droop in a 22nm graphics execution core more effectively than adaptive clocking alone. Measurements show that there is an optimal VMIN where the combination provides the best improvement - 14% lower energy at 890MHz vs. 4% with adaptive clocking.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"56 5","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72577612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573546
Sechang Oh, Ngoc Le Ba, S. Bang, Junwon Jeong, D. Blaauw, T. T. Kim, D. Sylvester
This paper presents a low-power infrared motion detection system suitable for smart devices such as wearables. The SoC incorporates instrumentation chopper amplifiers (ICA), LPFs, ADCs, and a DSP. The low-noise ICAs amplify very low frequency μV-level thermopile outputs with 2.0 NEF and provide programmable gain modes. To reduce standby power the ICA uses lower current when the system is in idle mode. Wakeup can be triggered by detection of a simple gesture. For the LPF, source degeneration by pseudo-resistors and gm division techniques are used for both improved linearity and 30Hz bandwidth. The DSP employs a motion history image technique to achieve low-power detection. The system consumes 260μW in active mode and 46μW in idle mode while processing 16×4 infrared data at 30fps. A complete system demonstration is shown.
{"title":"A 260µW infrared gesture recognition system-on-chip for smart devices","authors":"Sechang Oh, Ngoc Le Ba, S. Bang, Junwon Jeong, D. Blaauw, T. T. Kim, D. Sylvester","doi":"10.1109/VLSIC.2016.7573546","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573546","url":null,"abstract":"This paper presents a low-power infrared motion detection system suitable for smart devices such as wearables. The SoC incorporates instrumentation chopper amplifiers (ICA), LPFs, ADCs, and a DSP. The low-noise ICAs amplify very low frequency μV-level thermopile outputs with 2.0 NEF and provide programmable gain modes. To reduce standby power the ICA uses lower current when the system is in idle mode. Wakeup can be triggered by detection of a simple gesture. For the LPF, source degeneration by pseudo-resistors and gm division techniques are used for both improved linearity and 30Hz bandwidth. The DSP employs a motion history image technique to achieve low-power detection. The system consumes 260μW in active mode and 46μW in idle mode while processing 16×4 infrared data at 30fps. A complete system demonstration is shown.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"10 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73313694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573536
Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu
This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital control unit to achieve 400MS/s operation. The prototype in 16-nm CMOS occupies an active area of 0.023 mm2. From a 0.95-V supply, the power consumption is 8.2 mW at 1.6 GS/s. The peak SNDR is 55 dB and HF FOM is 19 fJ/conversion-step.
{"title":"A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS","authors":"Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu","doi":"10.1109/VLSIC.2016.7573536","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573536","url":null,"abstract":"This paper presents a 4-way 1.6-GS/s time-interleaved (TI) SAR ADC with fast reference charge neutralization (CN) and background timing-skew calibration. The SAR sub-ADC uses a flip-flop-less digital control unit to achieve 400MS/s operation. The prototype in 16-nm CMOS occupies an active area of 0.023 mm2. From a 0.95-V supply, the power consumption is 8.2 mW at 1.6 GS/s. The peak SNDR is 55 dB and HF FOM is 19 fJ/conversion-step.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"14 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84329340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573464
Yi Zhang, Chia-Hung Chen, Tao He, G. Temes
A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.
{"title":"A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator","authors":"Yi Zhang, Chia-Hung Chen, Tao He, G. Temes","doi":"10.1109/VLSIC.2016.7573464","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573464","url":null,"abstract":"A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82784593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573459
Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, W. Chan, J. Liaw, H. Liao, Jonathan Chang
A total solution for 8T dual-port (DP) SRAM to improve its operating voltage range (VMIN/VMAX) is proposed. Partial suppressed word-line (PSWL) technique improves the static noise margin (SNM) when both ports (A, B ports) access at the same time. Dummy read recovery (DRR) and negative bit-line (NBL) techniques are introduced to eliminate the dummy read induced write recovery failure and write contention failure, respectively. The silicon results show that the VDD operation window can be improved from 220mV to 570mV in 16nm FinFET technology.
{"title":"A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications","authors":"Yen-Huei Chen, Kao-Cheng Lin, Ching-Wei Wu, W. Chan, J. Liaw, H. Liao, Jonathan Chang","doi":"10.1109/VLSIC.2016.7573459","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573459","url":null,"abstract":"A total solution for 8T dual-port (DP) SRAM to improve its operating voltage range (VMIN/VMAX) is proposed. Partial suppressed word-line (PSWL) technique improves the static noise margin (SNM) when both ports (A, B ports) access at the same time. Dummy read recovery (DRR) and negative bit-line (NBL) techniques are introduced to eliminate the dummy read induced write recovery failure and write contention failure, respectively. The silicon results show that the VDD operation window can be improved from 220mV to 570mV in 16nm FinFET technology.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"72 1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90724063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573510
Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, Jaeha Kim
A field-programmable mixed-signal IC for fast-prototyping and low-cost production of mixed-signal system is presented. The IC contains time-domain configurable analog blocks (TCABs) that can be programmed into a time-to-digital converter (TDC), digitally controlled oscillator (DCO), digitally controlled delay element, digital pulse-width modulator (DPWM), or phase interpolator (PI). The prototype IC fabricated in 65-nm CMOS demonstrates its versatile programmability with the successful operations as a 1-GHz PLL with 12.3-psrms integrated jitter, 50-MS/s ADC with 32.5-dB SNDR, and 1.2-to-0.7V DC-DC converter with 95.5% efficiency.
提出了一种用于混合信号系统快速成型和低成本生产的现场可编程混合信号集成电路。该IC包含时域可配置模拟块(tcab)，可将其编程为时间-数字转换器(TDC)、数字控制振荡器(DCO)、数字控制延迟元件、数字脉宽调制器(DPWM)或相位插补器(PI)。该原型IC采用65纳米CMOS制造，具有广泛的可编程性，成功实现了1 ghz锁相环、12.3 psrms集成抖动、50 ms /s ADC、32.5 db SNDR和效率为95.5%的1.2- 0.7 v DC-DC转换器。
{"title":"A field-programmable mixed-signal IC with time-domain configurable analog blocks","authors":"Yunju Choi, Yoontaek Lee, Seung-Heon Baek, Sung-Joon Lee, Jaeha Kim","doi":"10.1109/VLSIC.2016.7573510","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573510","url":null,"abstract":"A field-programmable mixed-signal IC for fast-prototyping and low-cost production of mixed-signal system is presented. The IC contains time-domain configurable analog blocks (TCABs) that can be programmed into a time-to-digital converter (TDC), digitally controlled oscillator (DCO), digitally controlled delay element, digital pulse-width modulator (DPWM), or phase interpolator (PI). The prototype IC fabricated in 65-nm CMOS demonstrates its versatile programmability with the successful operations as a 1-GHz PLL with 12.3-psrms integrated jitter, 50-MS/s ADC with 32.5-dB SNDR, and 1.2-to-0.7V DC-DC converter with 95.5% efficiency.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"4 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88091518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573543
Y. Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, A. Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Y. Sakano, Y. Kitano, Takuya Nakamura, T. Toyama, H. Iwamoto, T. Ezaki
A 4K2K 480 fps global-shutter CMOS image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 μVrms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of output image within 0.18 %. The 16-channel output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.
{"title":"An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure","authors":"Y. Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, A. Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Y. Sakano, Y. Kitano, Takuya Nakamura, T. Toyama, H. Iwamoto, T. Ezaki","doi":"10.1109/VLSIC.2016.7573543","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573543","url":null,"abstract":"A 4K2K 480 fps global-shutter CMOS image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 μVrms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of output image within 0.18 %. The 16-channel output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"148 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88654735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573486
P. Gill, T. Vogelsang
Lensless Smart Sensors (LSS) add optical and thermal sensing capabilities to the Internet of Things (IoT) in a form factor that cannot be achieved with traditional lensed systems. Different from lensed systems, LSS is based on diffraction instead of refraction, and different from other diffractive optical elements in that it can operate with a wide field of view (FOV) and over a wide wavelength band. LSS's use of computation to extract information from a captured scene makes LSS a good fit for applications where the goal is not to create an image for human consumption, but for machine viewing (e.g. to trigger actions in a connected device). Since the raw sensed image is encoded by the grating structure, LSS opens applications where the use of a camera would create privacy concerns. This paper describes the operational principle of LSS and discusses three examples in more detail.
{"title":"Lensless Smart Sensors: Optical and thermal sensing for the Internet of Things","authors":"P. Gill, T. Vogelsang","doi":"10.1109/VLSIC.2016.7573486","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573486","url":null,"abstract":"Lensless Smart Sensors (LSS) add optical and thermal sensing capabilities to the Internet of Things (IoT) in a form factor that cannot be achieved with traditional lensed systems. Different from lensed systems, LSS is based on diffraction instead of refraction, and different from other diffractive optical elements in that it can operate with a wide field of view (FOV) and over a wide wavelength band. LSS's use of computation to extract information from a captured scene makes LSS a good fit for applications where the goal is not to create an image for human consumption, but for machine viewing (e.g. to trigger actions in a connected device). Since the raw sensed image is encoded by the grating structure, LSS opens applications where the use of a camera would create privacy concerns. This paper describes the operational principle of LSS and discusses three examples in more detail.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"192 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76521350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-15DOI: 10.1109/VLSIC.2016.7573551
Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, K. Hsieh, Mark Chen, A. Ximenes, R. Staszewski
A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.
{"title":"A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8–19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS","authors":"Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, K. Hsieh, Mark Chen, A. Ximenes, R. Staszewski","doi":"10.1109/VLSIC.2016.7573551","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573551","url":null,"abstract":"A tiny LC-tank-based ADPLL in 10nm FinFET CMOS achieves an area comparable to that of inverter-based ring-oscillator PLLs. A DCO occupying 0.016mm2 uses a controllable multi-turn magnetic coupling transformer to extend its tuning range to 10.8-19.3GHz (56.5%). A diversity of fine-tune capacitor banks limits the max/min step-size ratio to 2.3×. A new metastability-resolution scheme allows to use the frequency reference (FREF) clock directly instead of a retimed FREF (CKR) of conventional ADPLLs. A low-complexity estimator calculates inverse of the TDC. The fractional phase jitter (725fs) reaches sub-ps for the first time among PLLs of <;0.1mm2. Frequency pushing is 1.8%/V, which is at least 50× better than in traditional ring-type PLLs.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"44 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87114362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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