A. Podpod, J. Slabbekoorn, A. Phommahaxay, F. Duval, A. Salahouelhadj, Mario Gonzalez, K. Rebibis, Andy Miller, G. Beyer, E. Beyne
The rapid growth of data bandwidth required between logic and memory chips for next generation device nodes is progressively pushing low I/O count serial busses to their limits. To further satisfy this increasing need for high data rates, wider I/O count busses are now being developed and established. Over the past years, various Fan-Out Wafer-Level-Packaging (FOWLP) approaches have been developed to answer the needs mentioned above and the increasingly demanding function integration on package. Imec has been working on a novel 300mm Fan-Out Wafer-Level-Packaging concept that enables 20µm pitch interconnect density. Results from experiments demonstrates wafer bow below 500µm after molding on silicon substrate with ultra-low die shift with maximum die to carrier mismatch below 10µm on full 300mm wafers. Further warpage and die shift evolution are expected depending on the process steps the wafers must go through and will be further discussed.
{"title":"A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-µm Pitch","authors":"A. Podpod, J. Slabbekoorn, A. Phommahaxay, F. Duval, A. Salahouelhadj, Mario Gonzalez, K. Rebibis, Andy Miller, G. Beyer, E. Beyne","doi":"10.1109/ECTC.2018.00063","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00063","url":null,"abstract":"The rapid growth of data bandwidth required between logic and memory chips for next generation device nodes is progressively pushing low I/O count serial busses to their limits. To further satisfy this increasing need for high data rates, wider I/O count busses are now being developed and established. Over the past years, various Fan-Out Wafer-Level-Packaging (FOWLP) approaches have been developed to answer the needs mentioned above and the increasingly demanding function integration on package. Imec has been working on a novel 300mm Fan-Out Wafer-Level-Packaging concept that enables 20µm pitch interconnect density. Results from experiments demonstrates wafer bow below 500µm after molding on silicon substrate with ultra-low die shift with maximum die to carrier mismatch below 10µm on full 300mm wafers. Further warpage and die shift evolution are expected depending on the process steps the wafers must go through and will be further discussed.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"370-378"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75482554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the recent years, 3D packaging has become a major enabler for heterogeneous integration of multiple functional devices and different nodes into a single package. The integration of multiple devices into 3D packages poses significant challenges when it comes to electrical fault isolation and failure analysis. With 3D packages, non-destructive fault isolation is important so as to accurately isolate the defect to the specific part of the failing package. This is critical since the different components in a 3D package are often owned by different suppliers and accurate non-destructive fault isolation will facilitate further root cause analysis and failure disposition by the concerned suppliers. Much higher sensitivity and better resolution in defect depth are two critical capabilities required for 3D packages. Lock-in Thermography (LIT) is a powerful non-destructive fault isolation technique for thermally active defects in semiconductor packages. With the integration of multiple components into 3D packages, the challenge lies in the added complexity in terms of the number of active devices and routing inside the package. More often than not, we have multiple defects inside the package at the same time. This study presents a fundamental analysis on the interaction between multiple defects in a package and its effect on defect depth estimate accuracy in lock-in thermography applications. In addition, data from real test cases have also been presented, which help better understand the interaction between multiple defects and provide confidence in the proposed correlations. The learnings from this study will facilitate tool and technique development and benefit failure analysis and 3D package development community.
{"title":"Effect of Interaction Between Multiple Defects on Z-Depth Estimate in Lock-in Thermography Applications","authors":"B. Ravi, Mayue Xie, D. Goyal","doi":"10.1109/ECTC.2018.00343","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00343","url":null,"abstract":"In the recent years, 3D packaging has become a major enabler for heterogeneous integration of multiple functional devices and different nodes into a single package. The integration of multiple devices into 3D packages poses significant challenges when it comes to electrical fault isolation and failure analysis. With 3D packages, non-destructive fault isolation is important so as to accurately isolate the defect to the specific part of the failing package. This is critical since the different components in a 3D package are often owned by different suppliers and accurate non-destructive fault isolation will facilitate further root cause analysis and failure disposition by the concerned suppliers. Much higher sensitivity and better resolution in defect depth are two critical capabilities required for 3D packages. Lock-in Thermography (LIT) is a powerful non-destructive fault isolation technique for thermally active defects in semiconductor packages. With the integration of multiple components into 3D packages, the challenge lies in the added complexity in terms of the number of active devices and routing inside the package. More often than not, we have multiple defects inside the package at the same time. This study presents a fundamental analysis on the interaction between multiple defects in a package and its effect on defect depth estimate accuracy in lock-in thermography applications. In addition, data from real test cases have also been presented, which help better understand the interaction between multiple defects and provide confidence in the proposed correlations. The learnings from this study will facilitate tool and technique development and benefit failure analysis and 3D package development community.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2280-2287"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75681654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new, highly productive and accurate thermal compression bonder is presented. Overcoming the disparity between productivity and accuracy, we propose a multi-table and multi-bond head system utilizing gantries, including: a pipeline system to decrease total cooling time during TCB, a cancellation system for vibration during table motion, and a structure for high force bonding with accuracy appropriate for TCB. On a system containing 2 bond heads on 2 gantries, the total TCB process time applying the proposed pipeline system is decreased to 5.5sec, which is 33% higher productivity compared to series processing. By using a structure of separating the bonder base and moving axis, which functions as a cancellation system for vibration generated from the moving axis, no vibration propagates to the other moving axis, resulting that the system enables high speed operation to improve productivity. Typical systems which mount bonding heads on a gantry are constructed with a cantilever structure having advantages for the structure and light weight while having disadvantages for shifting placement position during high force bonding over 100N. To satisfy both placement accuracy and high force for TCB, a new system is designed which transfers high Z axis force to a separate upper structure, solving the inherent accuracy problems with cantilever systems. At 200N, the placement shifts are 1µm with the system and 12µm without it. By implementing the described functions, a productive and accurate TCB bonder is realized. In this paper, we report detailed experimental results for the functions. The potential of a new TCB bonder including these new functions will be demonstrated through bonding results.
{"title":"Design and Application of Innovative Multi-table and Bond Head Drive System on Thermal Compression Bonder with UPH Over 2000","authors":"Kohei Seyama, Shoji Wada, Yuji Eguchi, Tomonori Nakamura, Doug Day, S. Sugawa","doi":"10.1109/ECTC.2018.00066","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00066","url":null,"abstract":"A new, highly productive and accurate thermal compression bonder is presented. Overcoming the disparity between productivity and accuracy, we propose a multi-table and multi-bond head system utilizing gantries, including: a pipeline system to decrease total cooling time during TCB, a cancellation system for vibration during table motion, and a structure for high force bonding with accuracy appropriate for TCB. On a system containing 2 bond heads on 2 gantries, the total TCB process time applying the proposed pipeline system is decreased to 5.5sec, which is 33% higher productivity compared to series processing. By using a structure of separating the bonder base and moving axis, which functions as a cancellation system for vibration generated from the moving axis, no vibration propagates to the other moving axis, resulting that the system enables high speed operation to improve productivity. Typical systems which mount bonding heads on a gantry are constructed with a cantilever structure having advantages for the structure and light weight while having disadvantages for shifting placement position during high force bonding over 100N. To satisfy both placement accuracy and high force for TCB, a new system is designed which transfers high Z axis force to a separate upper structure, solving the inherent accuracy problems with cantilever systems. At 200N, the placement shifts are 1µm with the system and 12µm without it. By implementing the described functions, a productive and accurate TCB bonder is realized. In this paper, we report detailed experimental results for the functions. The potential of a new TCB bonder including these new functions will be demonstrated through bonding results.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"3 1","pages":"392-400"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78400160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jarrid A. Wittkopf, Ning Ge, R. Ionescu, Wagston Staehler, Doug Pederson, H. Holder
Chipless RFIDs are a disruptive technology that acts as a moderate solution between conventional barcodes and chipped RFIDs. These devices allow for cost savings compared to chipped RFIDs and can be identified even with an obstructed view of the tag. One category of chipless RFID is known as the radar cross section (RCS) backscattered chipless RFID. RCS Chipless RFID tags operate by physically encoding data with carefully designed resonating elements. These resonating elements are short electrically coupled resonators that backscatter an interrogating signal based on their frequency dependent RCS signature. In this study, we investigate through simulation and experimental results the properties of four inkjet printable RCS backscattered chipless RFID designs. Each of the designs have different resonating elements that effect the tags reading range, readability, tag size, bandwidth utilization, and polarization dependence. The goal of this study is to give insight into how each of these designs will function in future smart packaging applications.
{"title":"Chipless RFID with Fully Inkjet Printed Tags: A Practical Case Study for Low Cost Smart Packaging Applications","authors":"Jarrid A. Wittkopf, Ning Ge, R. Ionescu, Wagston Staehler, Doug Pederson, H. Holder","doi":"10.1109/ECTC.2018.00144","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00144","url":null,"abstract":"Chipless RFIDs are a disruptive technology that acts as a moderate solution between conventional barcodes and chipped RFIDs. These devices allow for cost savings compared to chipped RFIDs and can be identified even with an obstructed view of the tag. One category of chipless RFID is known as the radar cross section (RCS) backscattered chipless RFID. RCS Chipless RFID tags operate by physically encoding data with carefully designed resonating elements. These resonating elements are short electrically coupled resonators that backscatter an interrogating signal based on their frequency dependent RCS signature. In this study, we investigate through simulation and experimental results the properties of four inkjet printable RCS backscattered chipless RFID designs. Each of the designs have different resonating elements that effect the tags reading range, readability, tag size, bandwidth utilization, and polarization dependence. The goal of this study is to give insight into how each of these designs will function in future smart packaging applications.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"940-947"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76107299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Piekarz, J. Sorocki, K. Wincza, S. Gruszczynski, J. Papapolymerou
In this paper, the realization of microwave circuits in suspended microstrip structure with a 3D printed conductive enclosure is presented for the first time. An example of a low-pass filter with a cut-off frequency of 2.5 GHz was designed, manufactured and measured. A Fused Deposition Modeling (FDM) type 3D printing and a conductive copper-based filament recently developed by Multi 3D were employed to realize an enclosure serving both mechanical and electrical purposes. The influence of the ground plane conductivity on the total loss within the circuit was studied, and requirements for the conductive material properties were established. Moreover, the impact of the print parameters as well as the connection between microstrip line and SMA connectors was investigated. The obtained measurements proved that the proposed approach is of potential use for circuits and systems operating within low GHz frequency range.
{"title":"Suspended Microstrip Low-Pass Filter Realized Using FDM Type 3D Printing with Conductive Copper-Based Filament","authors":"I. Piekarz, J. Sorocki, K. Wincza, S. Gruszczynski, J. Papapolymerou","doi":"10.1109/ECTC.2018.00372","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00372","url":null,"abstract":"In this paper, the realization of microwave circuits in suspended microstrip structure with a 3D printed conductive enclosure is presented for the first time. An example of a low-pass filter with a cut-off frequency of 2.5 GHz was designed, manufactured and measured. A Fused Deposition Modeling (FDM) type 3D printing and a conductive copper-based filament recently developed by Multi 3D were employed to realize an enclosure serving both mechanical and electrical purposes. The influence of the ground plane conductivity on the total loss within the circuit was studied, and requirements for the conductive material properties were established. Moreover, the impact of the print parameters as well as the connection between microstrip line and SMA connectors was investigated. The obtained measurements proved that the proposed approach is of potential use for circuits and systems operating within low GHz frequency range.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2470-2476"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79945473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Goodhue, D. Danovitch, Jeff Moussodji Moussodji, Benoit Papineau, É. Duchesne
This paper presents work undertaken to investigate a temporary carrier technique to control the warpage of an organic coreless substrate during a flip chip assembly process that exploits the higher throughput technique of mass reflow chip joining. To optimally select an appropriate carrier and adhesive, a study of the forces necessary to maintain substrate flatness throughout a simulated temperature excursion of the chip joining process was conducted by developing a novel adaptation of the Shadow-Moiré fringe measurement technique. Different temporary adhesives and carriers were then investigated by modeling and mechanical testing as well as by thermal Shadow-Moiré comparison of free-standing versus bonded substrates during the chip joining temperature profile. These tests recommended the use of an aluminum carrier. Both polyimide and thermoplastic adhesive demonstrated improved results (20 µm warpage) with this carrier as compared to the freestanding substrate (40-100 µm), although the tendency of the thermoplastic to deform at elevated temperatures and stresses was identified as a concern. Subsequent assembly experiments on production scale equipment validated both the improved warpage control obtained by a temporary carrier solution and the superior performance of the polyimide adhesive. Results of the polyimide solution are presented through detailed comparison to a standard process. Significant improvements were observed in such aspects as die warpage (20-30 µm vs 130-140 µm), interconnect height consistency (56-59 µm vs 55-68 µm) and post underfill assembly warpage (150 µm vs 250 µm). The results warrant further work to develop a manufacturing level debonding process and ultimately integrate the entire solution into a high volume production flip chip assembly process.
本文介绍了一种临时载流子技术，以控制倒装芯片组装过程中有机无芯衬底的弯曲，该技术利用了高通量的大规模回流芯片连接技术。为了最佳地选择合适的载体和粘合剂，通过开发一种新的阴影-莫尔条纹测量技术，研究了在芯片连接过程的模拟温度偏移过程中保持衬底平坦度所需的力。然后，通过建模和力学测试以及在芯片连接温度曲线期间对独立基材和粘合基材的热影-摩尔对比，研究了不同的临时粘合剂和载体。这些测试建议使用铝载体。与独立基板(40-100 μ m)相比，聚酰亚胺和热塑性胶粘剂的效果都有所改善(20 μ m翘曲)，尽管热塑性塑料在高温和应力下变形的趋势被认为是一个问题。随后在生产规模的设备上进行的装配实验验证了临时载体溶液改善的翘曲控制效果和聚酰亚胺胶粘剂的优越性能。通过与标准工艺的详细比较，给出了聚酰亚胺溶液的结果。在模具翘曲度(20-30 μ m vs 130-140 μ m)、互连高度一致性(56-59 μ m vs 55-68 μ m)和后下填料装配翘曲度(150 μ m vs 250 μ m)等方面观察到显著改善。研究结果表明，需要进一步开发制造级脱粘工艺，并最终将整个解决方案集成到大批量生产的倒装芯片组装工艺中。
{"title":"Warpage Control During Mass Reflow Flip Chip Assembly Using Temporary Adhesive Bonding","authors":"N. Goodhue, D. Danovitch, Jeff Moussodji Moussodji, Benoit Papineau, É. Duchesne","doi":"10.1109/ECTC.2018.00110","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00110","url":null,"abstract":"This paper presents work undertaken to investigate a temporary carrier technique to control the warpage of an organic coreless substrate during a flip chip assembly process that exploits the higher throughput technique of mass reflow chip joining. To optimally select an appropriate carrier and adhesive, a study of the forces necessary to maintain substrate flatness throughout a simulated temperature excursion of the chip joining process was conducted by developing a novel adaptation of the Shadow-Moiré fringe measurement technique. Different temporary adhesives and carriers were then investigated by modeling and mechanical testing as well as by thermal Shadow-Moiré comparison of free-standing versus bonded substrates during the chip joining temperature profile. These tests recommended the use of an aluminum carrier. Both polyimide and thermoplastic adhesive demonstrated improved results (20 µm warpage) with this carrier as compared to the freestanding substrate (40-100 µm), although the tendency of the thermoplastic to deform at elevated temperatures and stresses was identified as a concern. Subsequent assembly experiments on production scale equipment validated both the improved warpage control obtained by a temporary carrier solution and the superior performance of the polyimide adhesive. Results of the polyimide solution are presented through detailed comparison to a standard process. Significant improvements were observed in such aspects as die warpage (20-30 µm vs 130-140 µm), interconnect height consistency (56-59 µm vs 55-68 µm) and post underfill assembly warpage (150 µm vs 250 µm). The results warrant further work to develop a manufacturing level debonding process and ultimately integrate the entire solution into a high volume production flip chip assembly process.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"136-137 1","pages":"703-711"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79236623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Guilian Gao, L. Mirkarimi, G. Fountain, Liang Wang, C. Uzoh, Thomas Workman, Gabe Guevara, Chandrasekhar Mandalapu, Bongsub Lee, R. Katkar
The low-temperature direct bond interconnect commonly referred to as hybrid bonding technology is a promising solution for achieving an interconnect pitch smaller than 40µm. Wafer-to-wafer (W2W) direct bond interconnect technology has been in high volume manufacturing for several years. This paper presents the latest development for extending this technology from W2W to die-to-wafer (D2W) and die-to-die (D2D) applications. Daisy chain die with direct bond interconnect layers on either one or both surfaces are designed with a similar size to a high bandwidth dynamic random access memory (HBM DRAM) die, 7.96 mm x 11.96 mm. The longest daisy chain structure has 31,356 links and covers an active area of 5.36mm x 9.36mm. The bonding pitch ranges from 10 to 40 µm with a pad diameter of either 5 or 10 µm. The paper addresses the critical issues in bringing direct bond interconnect into a manufacturing environment with a D2W or D2D assembly flow while sharing the latest results. The assembly topics addressed here include extension of CMP to 10 µm pads, dicing, surface preparation for the direct bonding in a pick and place tool. The dies bond to a full-thickness host wafer integrated with a mating daisy chain to demonstrate electrical connectivity. Bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. Electrical test yield as high as 92% on the full daisy chain is achieved. Bonded parts have showed superior reliability in the JEDEC standard thermal cycling and high temperature storage testing.
低温直接键合互连通常被称为混合键合技术，是实现互连间距小于40µm的有前途的解决方案。晶圆对晶圆(W2W)直接键合互连技术已经大批量生产了好几年。本文介绍了将该技术从W2W扩展到晶圆(D2W)和晶圆(D2D)应用的最新进展。在一个或两个表面上具有直接键合互连层的菊花链芯片的设计尺寸与高带宽动态随机存取存储器(HBM DRAM)芯片相似，为7.96 mm x 11.96 mm。最长的菊花链结构有31,356个链接，覆盖5.36mm x 9.36mm的活动面积。键合间距范围为10 ~ 40 μ m，焊盘直径为5或10 μ m。本文讨论了将直接键合互连引入具有D2W或D2D装配流程的制造环境中的关键问题，同时分享了最新成果。这里讨论的组装主题包括将CMP扩展到10 μ m焊盘，切割，在拾取和放置工具中直接粘合的表面准备。模具结合到一个全厚度的主晶圆集成配合菊花链，以证明电气连接。用c型扫描声学显微镜(CSAM)、电阻测量和截面显微镜分析来表征键合质量。在全雏菊链上实现了高达92%的电气测试良率。结合件在JEDEC标准热循环和高温储存试验中表现出优异的可靠性。
{"title":"Scaling Package Interconnects Below 20µm Pitch with Hybrid Bonding","authors":"Guilian Gao, L. Mirkarimi, G. Fountain, Liang Wang, C. Uzoh, Thomas Workman, Gabe Guevara, Chandrasekhar Mandalapu, Bongsub Lee, R. Katkar","doi":"10.1109/ECTC.2018.00055","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00055","url":null,"abstract":"The low-temperature direct bond interconnect commonly referred to as hybrid bonding technology is a promising solution for achieving an interconnect pitch smaller than 40µm. Wafer-to-wafer (W2W) direct bond interconnect technology has been in high volume manufacturing for several years. This paper presents the latest development for extending this technology from W2W to die-to-wafer (D2W) and die-to-die (D2D) applications. Daisy chain die with direct bond interconnect layers on either one or both surfaces are designed with a similar size to a high bandwidth dynamic random access memory (HBM DRAM) die, 7.96 mm x 11.96 mm. The longest daisy chain structure has 31,356 links and covers an active area of 5.36mm x 9.36mm. The bonding pitch ranges from 10 to 40 µm with a pad diameter of either 5 or 10 µm. The paper addresses the critical issues in bringing direct bond interconnect into a manufacturing environment with a D2W or D2D assembly flow while sharing the latest results. The assembly topics addressed here include extension of CMP to 10 µm pads, dicing, surface preparation for the direct bonding in a pick and place tool. The dies bond to a full-thickness host wafer integrated with a mating daisy chain to demonstrate electrical connectivity. Bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. Electrical test yield as high as 92% on the full daisy chain is achieved. Bonded parts have showed superior reliability in the JEDEC standard thermal cycling and high temperature storage testing.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"125 1","pages":"314-322"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81699468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The size of the 3D micro glass shell resonator is one of the main factors affecting the performance of the micro shell resonator gyroscopes (µSRG) such as resonant frequency and quality factor. Different sizes result in different resonant frequencies, which will directly affect the performance of the µSRG. Therefore, for wafer-level fabrication process of micro shell resonators, ensuring size uniformity is an important issue that must be considered. The original wafer-level method for the preparation of micro shell resonators - chemical foaming process (CFP), cannot guarantee that all the resonators on the wafer have the same size. In this paper, an improved process is investigated to improve size uniformity of wafer level shell resonators. Through the measurement, the standard deviation of the height of micro shell resonators on the wafer is reduced from 0.12 to 0.08, and the range is reduced from 480µm to 350µm. The improved process shows potential for improving size uniformity.
{"title":"Study on an Improved Wafer Level Fabrication Process to Achieve Size Uniformity for Micro Glass Shell Resonators","authors":"Zhaoxi Su, J. Shang, Bin Luo, C. Wong","doi":"10.1109/ECTC.2018.00147","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00147","url":null,"abstract":"The size of the 3D micro glass shell resonator is one of the main factors affecting the performance of the micro shell resonator gyroscopes (µSRG) such as resonant frequency and quality factor. Different sizes result in different resonant frequencies, which will directly affect the performance of the µSRG. Therefore, for wafer-level fabrication process of micro shell resonators, ensuring size uniformity is an important issue that must be considered. The original wafer-level method for the preparation of micro shell resonators - chemical foaming process (CFP), cannot guarantee that all the resonators on the wafer have the same size. In this paper, an improved process is investigated to improve size uniformity of wafer level shell resonators. Through the measurement, the standard deviation of the height of micro shell resonators on the wafer is reduced from 0.12 to 0.08, and the range is reduced from 480µm to 350µm. The improved process shows potential for improving size uniformity.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"58 1","pages":"962-966"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85487625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, silver (Ag) alloys have been emerging as bonding wire materials for commercialized electronic products because of moderate hardness, high ductility, best thermal and electrical conductivities among metals and low growth rate of intermetallic compounds (IMCs). Many compositional designs such as Ag-Palladium (Pd), Ag-Gold (Au)-Pd have been demonstrated and relevant reliability issues on aluminum (Al) pad have been studied. Ag2Al and Ag3Al have been identified as the interfacial IMCs. However, the softness, facture toughness and corrosion resistance of Ag2Al are much better than those of Ag3Al. Therefore, Ag3Al and its interfaces between adjacent phases become weak part in terms of long term reliability. In this paper, an approach to eliminate Ag3Al phase is proposed by alloying indium (In) into Ag. Comprehensive studies are preformed after the inter-diffusion between Ag and Al. Focus ion beam (FIB) is utilized to create clean cross sections and sample preparation. Scanning electron microscopy (SEM) by using in-beam secondary electron (ISE) detector is carried out for cross-sectional examination and morphological evolution description. Furthermore, nanostructure, high spatial resolution compositional study and phase identification are conducted by transmission electron microscopy (TEM), energy dispersive spectroscopy (EDX) and selected area electron diffraction (SAED). The results show that the IMCs growth rate is high suppressed and Ag3Al layer has been replaced by an Ag-In-Al ternary phase. The crystal structure of the ternary phase is identified as hexagonal close packing (hcp), which is same as the structure of Ag2Al. As a result, the weak phase and interfaces due to the growth of Ag3Al are eliminated, which will definitely increase the reliability of joints. Also, alloying with indium will improve the mechanical property and tarnishing resistance of Ag, therefore, it should be promising in the future Ag wire bonding market.
{"title":"Eliminating Harmful Intermetallic Compound Phase in Silver Wire Bonding by Alloying Silver with Indium","authors":"Jiaqi Wu, Chin C. Lee","doi":"10.1109/ECTC.2018.00335","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00335","url":null,"abstract":"Recently, silver (Ag) alloys have been emerging as bonding wire materials for commercialized electronic products because of moderate hardness, high ductility, best thermal and electrical conductivities among metals and low growth rate of intermetallic compounds (IMCs). Many compositional designs such as Ag-Palladium (Pd), Ag-Gold (Au)-Pd have been demonstrated and relevant reliability issues on aluminum (Al) pad have been studied. Ag2Al and Ag3Al have been identified as the interfacial IMCs. However, the softness, facture toughness and corrosion resistance of Ag2Al are much better than those of Ag3Al. Therefore, Ag3Al and its interfaces between adjacent phases become weak part in terms of long term reliability. In this paper, an approach to eliminate Ag3Al phase is proposed by alloying indium (In) into Ag. Comprehensive studies are preformed after the inter-diffusion between Ag and Al. Focus ion beam (FIB) is utilized to create clean cross sections and sample preparation. Scanning electron microscopy (SEM) by using in-beam secondary electron (ISE) detector is carried out for cross-sectional examination and morphological evolution description. Furthermore, nanostructure, high spatial resolution compositional study and phase identification are conducted by transmission electron microscopy (TEM), energy dispersive spectroscopy (EDX) and selected area electron diffraction (SAED). The results show that the IMCs growth rate is high suppressed and Ag3Al layer has been replaced by an Ag-In-Al ternary phase. The crystal structure of the ternary phase is identified as hexagonal close packing (hcp), which is same as the structure of Ag2Al. As a result, the weak phase and interfaces due to the growth of Ag3Al are eliminated, which will definitely increase the reliability of joints. Also, alloying with indium will improve the mechanical property and tarnishing resistance of Ag, therefore, it should be promising in the future Ag wire bonding market.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"45 1","pages":"2230-2236"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81069717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The high thermal conductivity, light weight, and low cost of aluminum (Al) make it a promising substrate material for high power electronic packaging. Recently, direct bond aluminum (DBA) substrate has received significant attention as a possible alternative to direct bond copper (DBC) substrate which seems to have thermal cycling reliability issues. A main challenge of using aluminum substrates in electronic packaging is the poor bondability. The native aluminum oxide layer prevents aluminum from forming bonding with die-attach materials or metallization layers. Thus, zincating process is required to dissolve the aluminum oxide and deposit a protective layer of zinc, which provides a basis for subsequent metallization. In this research, Ag-Al eutectic bonding has been developed as a novel bonding technique to direct bond Ag to Al substrate. The shear strength of the Ag-Al joints passes military criterion (MIL-STD-883H method 2019.8) with a large margin. SEM and TEM analyses were utilized to study the microstructures in details. The results reveal that eutectic structure of Ag2Al and (Al) phase forms at the Ag/Al bonding interface. A uniform Ag2Al compound layer was observed between the eutectic structure and Ag region, with no Ag3Al compound detected. In the Ag-Al eutectic reaction process, the aluminum oxide layer was broken into pieces and dispersed into the eutectic structure region. To investigate the fracture modes of Ag-Al eutectic joints, the fracture surfaces of Ag-Al joints were evaluated after the shear test. The fracture surfaces correspond to a typical ductile fracture with plastic deformation and drawing matrix. An application of this new technique is to bond Ag foils to Al substrates and make them bondable to die-attach materials such as solders and nano-silver paste. At a more advanced level, device chips can be bonded to the Ag foil on Al substrates at 300 °C using solid state bonding technique. This foil bonding application provides an alternative to the zincating and metallization processes on aluminum substrates. Other potential applications include making Al surfaces easier to blaze to other metals such as brass and copper.
{"title":"Direct Bonding Silver to Aluminum Using Eutectic Reaction in Air","authors":"Shao-Wei Fu, Chin C. Lee","doi":"10.1109/ECTC.2018.00086","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00086","url":null,"abstract":"The high thermal conductivity, light weight, and low cost of aluminum (Al) make it a promising substrate material for high power electronic packaging. Recently, direct bond aluminum (DBA) substrate has received significant attention as a possible alternative to direct bond copper (DBC) substrate which seems to have thermal cycling reliability issues. A main challenge of using aluminum substrates in electronic packaging is the poor bondability. The native aluminum oxide layer prevents aluminum from forming bonding with die-attach materials or metallization layers. Thus, zincating process is required to dissolve the aluminum oxide and deposit a protective layer of zinc, which provides a basis for subsequent metallization. In this research, Ag-Al eutectic bonding has been developed as a novel bonding technique to direct bond Ag to Al substrate. The shear strength of the Ag-Al joints passes military criterion (MIL-STD-883H method 2019.8) with a large margin. SEM and TEM analyses were utilized to study the microstructures in details. The results reveal that eutectic structure of Ag2Al and (Al) phase forms at the Ag/Al bonding interface. A uniform Ag2Al compound layer was observed between the eutectic structure and Ag region, with no Ag3Al compound detected. In the Ag-Al eutectic reaction process, the aluminum oxide layer was broken into pieces and dispersed into the eutectic structure region. To investigate the fracture modes of Ag-Al eutectic joints, the fracture surfaces of Ag-Al joints were evaluated after the shear test. The fracture surfaces correspond to a typical ductile fracture with plastic deformation and drawing matrix. An application of this new technique is to bond Ag foils to Al substrates and make them bondable to die-attach materials such as solders and nano-silver paste. At a more advanced level, device chips can be bonded to the Ag foil on Al substrates at 300 °C using solid state bonding technique. This foil bonding application provides an alternative to the zincating and metallization processes on aluminum substrates. Other potential applications include making Al surfaces easier to blaze to other metals such as brass and copper.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"91 1","pages":"545-550"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79520869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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