K. Dhandapani, Jiantao Zheng, B. Roggeman, Marcus Hsu
Package on Package (PoP) has been an ideal choice for high end products in mobile ecosystem due to its high-density bandwidth support and flexibility for the original equipment manufacturers (OEMs) to accommodate required memory integration. Form-factor and performance requirements of high end handsets pushes the envelope of PoP package solutions in recent times and requires chip manufacturers to constantly shift package attributes. These changes often add various thermo-mechanical challenges for the chip manufacturers and end OEMs when integrating into their final system while maintaining high reliability requirement in field. In this paper, the focus will be primarily on addressing various attributes that concern the 2nd level solder interconnect reliability. We will discuss factors that affect both PoP memory BGAs and bottom logic package BGAs especially during temperature cycle (TC) condition. We will demonstrate a few case studies using both testing data and simulation data on how factors such as Memory BGA array, underfill choices and BGA depopulation can impact the board level reliability. We will further provide recommendations and guidelines to improve board level reliability of PoP packages in current ecosystem where OEMs are facing challenges juggling form-factor constraints, performance, functionality and field reliability.
{"title":"Improving Solder Joint Reliability for PoP Packages in Current Mobile Ecosystem","authors":"K. Dhandapani, Jiantao Zheng, B. Roggeman, Marcus Hsu","doi":"10.1109/ECTC.2018.00248","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00248","url":null,"abstract":"Package on Package (PoP) has been an ideal choice for high end products in mobile ecosystem due to its high-density bandwidth support and flexibility for the original equipment manufacturers (OEMs) to accommodate required memory integration. Form-factor and performance requirements of high end handsets pushes the envelope of PoP package solutions in recent times and requires chip manufacturers to constantly shift package attributes. These changes often add various thermo-mechanical challenges for the chip manufacturers and end OEMs when integrating into their final system while maintaining high reliability requirement in field. In this paper, the focus will be primarily on addressing various attributes that concern the 2nd level solder interconnect reliability. We will discuss factors that affect both PoP memory BGAs and bottom logic package BGAs especially during temperature cycle (TC) condition. We will demonstrate a few case studies using both testing data and simulation data on how factors such as Memory BGA array, underfill choices and BGA depopulation can impact the board level reliability. We will further provide recommendations and guidelines to improve board level reliability of PoP packages in current ecosystem where OEMs are facing challenges juggling form-factor constraints, performance, functionality and field reliability.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"56 1","pages":"1645-1650"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78790036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Jourdain, N. Tutunjyan, J. Devos, S. Sardo, D. Piumi, Andy Miller, E. Beyne, E. Walsby, H. Ashraf, D. Thomas, N. Rassoul
In the general context of scaling, the 3D stacked system architecture is considered today, more than ever, as one of the future alternatives. Multiple options are still under investigation, but common process modules can already be identified. An important element of 3D integration is the backside Through-Silicon Via (TSV) reveal process after wafer bonding and thinning, also called Via Reveal. This has gained more and more interest in recent years as process robustness and stability will impact the device electrical performances and reliability. Moreover, subsequent processing such as bumping or RDL (Redistribution Layers) processing directly rely on successfully exposed TSVs. Different approaches have been developed for via reveal and have already been adopted by industry. So far, different studies have been carried out investigating issues affecting process integration, mainly to assess non-uniformity issues. Indeed, multiple factors can lead to variability within the process that will affect the TSV reveal performances. The consequences are large within-wafer variations, wafer-to-wafer non-uniformities and lot-to-lot variations. The robustness and stability of the via reveal process can be drastically improved by using an in-situ optical endpoint detection (EPD) system. The focus of this paper is to introduce an innovative approach where the via reveal process is controlled by an integrated optical EPD system during the reactive Si dry etch to expose the backside TSVs. The first part of the study introduces the impact of mask open area (or TSV density) on the EPD traces. As the system is based on optical reflection, the reflected signal intensity can vary according to the revealed TSVs. The second part focuses on the study of the optical EPD window modulation where the wafer area of interest can be extended within the wafer (center and along the wafer). This approach can be beneficial where the incoming Si thickness after grind and the TSV depth profile have variability wafer to wafer. A comparison of low TSV density and high TSV density is also shown. Finally, directions for process improvement are discussed.
{"title":"Characterization of Optical End-Point Detection for Via Reveal Processing","authors":"A. Jourdain, N. Tutunjyan, J. Devos, S. Sardo, D. Piumi, Andy Miller, E. Beyne, E. Walsby, H. Ashraf, D. Thomas, N. Rassoul","doi":"10.1109/ECTC.2018.00182","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00182","url":null,"abstract":"In the general context of scaling, the 3D stacked system architecture is considered today, more than ever, as one of the future alternatives. Multiple options are still under investigation, but common process modules can already be identified. An important element of 3D integration is the backside Through-Silicon Via (TSV) reveal process after wafer bonding and thinning, also called Via Reveal. This has gained more and more interest in recent years as process robustness and stability will impact the device electrical performances and reliability. Moreover, subsequent processing such as bumping or RDL (Redistribution Layers) processing directly rely on successfully exposed TSVs. Different approaches have been developed for via reveal and have already been adopted by industry. So far, different studies have been carried out investigating issues affecting process integration, mainly to assess non-uniformity issues. Indeed, multiple factors can lead to variability within the process that will affect the TSV reveal performances. The consequences are large within-wafer variations, wafer-to-wafer non-uniformities and lot-to-lot variations. The robustness and stability of the via reveal process can be drastically improved by using an in-situ optical endpoint detection (EPD) system. The focus of this paper is to introduce an innovative approach where the via reveal process is controlled by an integrated optical EPD system during the reactive Si dry etch to expose the backside TSVs. The first part of the study introduces the impact of mask open area (or TSV density) on the EPD traces. As the system is based on optical reflection, the reflected signal intensity can vary according to the revealed TSVs. The second part focuses on the study of the optical EPD window modulation where the wafer area of interest can be extended within the wafer (center and along the wafer). This approach can be beneficial where the incoming Si thickness after grind and the TSV depth profile have variability wafer to wafer. A comparison of low TSV density and high TSV density is also shown. Finally, directions for process improvement are discussed.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"17 1","pages":"1181-1187"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91256239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Natsuki Suzuki, T. Ohba, Yuta Kondo, T. Sakamoto, N. Uchiyama, K. Atsumi
This paper describes the throughput and edge straightness achieved by singulating memory wafers using a dicing method called Stealth Dicing (SD). Conventional SD faces the problem that, when the laser beam is focused in a region deep inside the silicon wafer, the beam is blurred, and its power density decreases owing to spherical aberration caused by a refractive index mismatch between air and the wafer material, and as a result, the throughput decreases. In this study, we used a phase-only Spatial Light Modulator (SLM) to improve the spherical aberration, and we evaluated how the total amount of aberration correction affected the processing performance. In addition, we evaluated the processing capability using three laser wavelengths (1064 nm, 1080 nm and 1099 nm) which have different transmittances in silicon. The edge straightness at these wavelengths changed with the aberration correction and was 1 μm or less in the case of under correction. The crack length decreased in the case of under correction. Thus, there was a trade-off between the aberration correction and crack growth. By applying the SD method with optimized aberration correction using 1099 nmwavelength laser light to dice memory wafers, the throughput was improved by two-times compared with Blade Dicing, and high manufacturability for volume production can thus be anticipated.
{"title":"High Throughput and Improved Edge Straightness for Memory Applications Using Stealth Dicing","authors":"Natsuki Suzuki, T. Ohba, Yuta Kondo, T. Sakamoto, N. Uchiyama, K. Atsumi","doi":"10.1109/ECTC.2018.00327","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00327","url":null,"abstract":"This paper describes the throughput and edge straightness achieved by singulating memory wafers using a dicing method called Stealth Dicing (SD). Conventional SD faces the problem that, when the laser beam is focused in a region deep inside the silicon wafer, the beam is blurred, and its power density decreases owing to spherical aberration caused by a refractive index mismatch between air and the wafer material, and as a result, the throughput decreases. In this study, we used a phase-only Spatial Light Modulator (SLM) to improve the spherical aberration, and we evaluated how the total amount of aberration correction affected the processing performance. In addition, we evaluated the processing capability using three laser wavelengths (1064 nm, 1080 nm and 1099 nm) which have different transmittances in silicon. The edge straightness at these wavelengths changed with the aberration correction and was 1 μm or less in the case of under correction. The crack length decreased in the case of under correction. Thus, there was a trade-off between the aberration correction and crack growth. By applying the SD method with optimized aberration correction using 1099 nmwavelength laser light to dice memory wafers, the throughput was improved by two-times compared with Blade Dicing, and high manufacturability for volume production can thus be anticipated.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"2180-2185"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90110024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chen-Yu Huang, Yuan-Hung Hsu, Y. Lu, K. Yu, W. Tsai, Chang-Fu Lin, C. Chung
The multi-chip module assembled with a composite layer of thin film on top of organic substrate is presented in this paper. This is a new-arising assembly technology with equivalent electrical performance of 2.5D package but much simplified supply-chain processes. We name this package as 2.1D package which converts the silicon interposer on the substrate. In this paper, the implementation of 2.1D technology on the monolithic, daisy-chain test vehicle is described. We employed thermal compression bonding (TCB) to mount two large dies with minimum 40 ?m-pitch micro bumps onto 45 x 45 mm organic substrate using 2/2 µm line width/space (L/S). Thermally induced misalignment, substrate warpage and the ELK (Extreme Low-K) stress during micro bumps joining with micro pads on substrate were evaluated. The mechanism of micro bump misalignment during solder formation has been experimentally and numerical validated by TCB and conventional mass reflow (MR) process. Finite element analyses were conducted to understand the 2.1D package warpage and stress behaviors, and hence defined better materials and process parameters. Simulation results showed that micro bump joining by TCB has 45% misalignment improvement as compared to MR process. In stress simulation results, the ELK layer stress of micro bump using TCB has a 59% reduction with reference to MR. In addition, the warpage behavior of fine-line organic substrate and 2.1D full package were measured using conventional shadow moiré system. Results showed that the warpage variation of thin-film coated substrates was very stable within micro pads area that has less than 10 µm differences under high temperature period (120~260 °C). However, the package moiré results showed that the thermally attaching of stiffener ring could significantly affect the global package warpage based on moiré contours and warpage distributions. The reliability of this developed 2.1D, multi-chip test vehicle using TCB assembling processes was validated as well. This package passed MSL4 preconditioning and 1000 thermal cycles using G-conditions (-40~125 °C).
本文提出了在有机衬底上装配复合薄膜层的多芯片模块。这是一种新兴的装配技术，其电气性能与2.5D封装相当，但大大简化了供应链流程。我们将这种封装命名为2.1D封装，它转换了衬底上的硅中间层。本文介绍了2.1D技术在单片菊花链试验车上的实现。我们采用热压缩键合(TCB)将两个具有最小40 μ m间距微凸起的大型模具安装在45 x 45 mm有机基板上，线宽/空间(L/S)为2/2 μ m。研究了热致错位、衬底翘曲以及衬底微凸起与微垫连接时的ELK(极低k)应力。通过TCB和传统的质量回流(MR)工艺，对焊料形成过程中微凹凸错位的机理进行了实验和数值验证。通过有限元分析来了解2.1D封装翘曲和应力行为，从而确定更好的材料和工艺参数。仿真结果表明，与MR工艺相比，TCB工艺的微凸点连接的不对中率提高了45%。在应力模拟结果中，使用TCB的微凸点的ELK层应力与mr相比降低了59%。此外，使用传统的阴影变形系统测量了细线有机衬底和2.1D全封装的翘曲行为。结果表明，在高温期(120~260℃)，薄膜涂层基板的翘曲变化在微衬垫区域内非常稳定，差异小于10µm。然而，从变形轮廓和变形分布来看，强化环的热附著对整体变形有显著影响。采用TCB装配工艺的2.1D多芯片测试车的可靠性也得到了验证。该封装通过了MSL4预处理和在g条件下(-40~125°C)进行1000次热循环。
{"title":"Analysis of Warpage and Stress Behavior in a Fine Pitch Multi-Chip Interconnection with Ultrafine-Line Organic Substrate (2.1D)","authors":"Chen-Yu Huang, Yuan-Hung Hsu, Y. Lu, K. Yu, W. Tsai, Chang-Fu Lin, C. Chung","doi":"10.1109/ECTC.2018.00100","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00100","url":null,"abstract":"The multi-chip module assembled with a composite layer of thin film on top of organic substrate is presented in this paper. This is a new-arising assembly technology with equivalent electrical performance of 2.5D package but much simplified supply-chain processes. We name this package as 2.1D package which converts the silicon interposer on the substrate. In this paper, the implementation of 2.1D technology on the monolithic, daisy-chain test vehicle is described. We employed thermal compression bonding (TCB) to mount two large dies with minimum 40 ?m-pitch micro bumps onto 45 x 45 mm organic substrate using 2/2 µm line width/space (L/S). Thermally induced misalignment, substrate warpage and the ELK (Extreme Low-K) stress during micro bumps joining with micro pads on substrate were evaluated. The mechanism of micro bump misalignment during solder formation has been experimentally and numerical validated by TCB and conventional mass reflow (MR) process. Finite element analyses were conducted to understand the 2.1D package warpage and stress behaviors, and hence defined better materials and process parameters. Simulation results showed that micro bump joining by TCB has 45% misalignment improvement as compared to MR process. In stress simulation results, the ELK layer stress of micro bump using TCB has a 59% reduction with reference to MR. In addition, the warpage behavior of fine-line organic substrate and 2.1D full package were measured using conventional shadow moiré system. Results showed that the warpage variation of thin-film coated substrates was very stable within micro pads area that has less than 10 µm differences under high temperature period (120~260 °C). However, the package moiré results showed that the thermally attaching of stiffener ring could significantly affect the global package warpage based on moiré contours and warpage distributions. The reliability of this developed 2.1D, multi-chip test vehicle using TCB assembling processes was validated as well. This package passed MSL4 preconditioning and 1000 thermal cycles using G-conditions (-40~125 °C).","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"631-637"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89366310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lowering the dielectric constant of interconnect, substrates and boards for electronic devices is needed to achieve faster switching speed and smaller electronic device packages. A feasible way to reduce the dielectric constant of existing material is by introducing porosity within the dielectric film. The density of pores and pore size play an important role in determining the mechanical property and electrical property of the film. An increase in the pore fraction leads to lower dielectric constant. However, higher pore fraction can deteriorate the mechanical properties. Therefore, it is important to achieve a balance between dielectric constant and mechanical properties. In this study, a low molecular weight sacrificial polymer poly(propylene carbonate) was functionalized with epoxide groups to increase its miscibility in an FR4 epoxy resin formulation by cross-linking it with the epoxy matrix. During or after curing, the epoxy resin can be heated to a temperature to generate the porous structure by evolution of the sacrificial polymer products. The mechanical and dielectric properties were measured to show the feasibility of using this modified sacrificial polymer in existing FR4 epoxy formulations to achieve lower dielectric constant interconnect.
{"title":"Porous Epoxy Film for Low Dielectric Constant Chip Substrates and Boards","authors":"Jisu Jiang, O. Phillips, Landon Keller, P. Kohl","doi":"10.1109/ECTC.2018.00013","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00013","url":null,"abstract":"Lowering the dielectric constant of interconnect, substrates and boards for electronic devices is needed to achieve faster switching speed and smaller electronic device packages. A feasible way to reduce the dielectric constant of existing material is by introducing porosity within the dielectric film. The density of pores and pore size play an important role in determining the mechanical property and electrical property of the film. An increase in the pore fraction leads to lower dielectric constant. However, higher pore fraction can deteriorate the mechanical properties. Therefore, it is important to achieve a balance between dielectric constant and mechanical properties. In this study, a low molecular weight sacrificial polymer poly(propylene carbonate) was functionalized with epoxide groups to increase its miscibility in an FR4 epoxy resin formulation by cross-linking it with the epoxy matrix. During or after curing, the epoxy resin can be heated to a temperature to generate the porous structure by evolution of the sacrificial polymer products. The mechanical and dielectric properties were measured to show the feasibility of using this modified sacrificial polymer in existing FR4 epoxy formulations to achieve lower dielectric constant interconnect.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"72 1","pages":"33-39"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89436165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Murugesan, T. F. J. Bea, H. Hashimoto, M. Koyanagi
Attempt has been made to form nanoc (NCy)ylinder structures inside Si trench and via in LSI chips by advanced directed-self-assembly. For the PS:PMMA ratio of 2:1 in PS(57k)-b-PMMA(25k) diblock-copolymer (DBC), the directed self-assembly reaction inside Si trench lead to the formation of 20 nm-width NCys and are running parallel > 6 m. It is inferred that upon increasing the molecular weight of PS to 140k from 57k, the width of NCy can be increased from 20 nm to ~70-80 nm. A ~100 nm-width metal interconnects were formed inside the ~500 nm-width vias of the bonded 3D-ICs, respectively for In metal. 2D simulation results reveal that the metal particles can be attached to PMMA of DBC and and forms cylinder. A resistance value of few tens of ohm was extracted from the I-V measurement data for In nanowires formed inside the 0.5 m vias between the flip-chip bonded LSI chips by DSA.
{"title":"Low-Cost and Self-Formed Vertical Nanowires with Aspect Ratio >100x in Deep Si-Trenches for Future 3D-LSI/IC Applications","authors":"M. Murugesan, T. F. J. Bea, H. Hashimoto, M. Koyanagi","doi":"10.1109/ECTC.2018.00176","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00176","url":null,"abstract":"Attempt has been made to form nanoc (NCy)ylinder structures inside Si trench and via in LSI chips by advanced directed-self-assembly. For the PS:PMMA ratio of 2:1 in PS(57k)-b-PMMA(25k) diblock-copolymer (DBC), the directed self-assembly reaction inside Si trench lead to the formation of 20 nm-width NCys and are running parallel > 6 m. It is inferred that upon increasing the molecular weight of PS to 140k from 57k, the width of NCy can be increased from 20 nm to ~70-80 nm. A ~100 nm-width metal interconnects were formed inside the ~500 nm-width vias of the bonded 3D-ICs, respectively for In metal. 2D simulation results reveal that the metal particles can be attached to PMMA of DBC and and forms cylinder. A resistance value of few tens of ohm was extracted from the I-V measurement data for In nanowires formed inside the 0.5 m vias between the flip-chip bonded LSI chips by DSA.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"1146-1151"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78699827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Po-Hao Chang, C. Hsieh, Chun-Wei Chang, Chih-Lun Chuang, Chen-Feng Chiang
MediaTek INFO Link (M-Link) is worldwide first successful homogeneous DIE-to-DIE data link for high-speed networking application. Considering benefits from large on-die capacitance of core-power domain, merged power domain for INFO and core-power is adopted. However, in order to sustain over 250W external core-power interference and internal INFO SSO noises, optimization of whole band target impedances to against these noises becomes one of major challenges. In this paper, a systematic approach to design M-Link in the extreme condition is proposed. In first part of paper, modulated chip power model (MCPM) technology is applied to ensure System-PDN. MCPM is modulated CPM which serves as new current load to represent mid-frequency bands interference for system level time domain noise simulations. In the second part, input pattern modulation (IPM) was applied to predict worst power ripple on INFO I/Os and jitter from sensitive circuit critical path. The IPM methodology serves as a total assessment considering all SI/PI impact to ensure a robust design. Finally, given fully consideration on System-PDN and INFO SI/PI, INFO I/Os with 4.8Gbps speed achieved 70% ETT eye windows in both simulation and verification. The design trade-off on core-power merged and separated is also discussed for future higher system bandwidth requirement.
联发科INFO Link (M-Link)是世界上第一个成功的高速网络应用的同质DIE-to-DIE数据链路。考虑到芯功率域的片上电容大的优点，采用了INFO和芯功率的合并功率域。然而，为了承受超过250W的外部核心功率干扰和内部INFO SSO噪声，优化全带目标阻抗以抵抗这些噪声成为主要挑战之一。本文提出了一种在极端条件下设计M-Link的系统方法。在论文的第一部分，采用调制芯片功率模型(MCPM)技术来保证系统- pdn。MCPM是一种调制的CPM，它作为新的电流负载来表示系统级时域噪声仿真中的中频干扰。在第二部分，应用输入模式调制(IPM)预测INFO I/ o的最坏功率纹波和敏感电路关键路径的抖动。IPM方法作为考虑所有SI/PI影响的总体评估，以确保稳健的设计。最后，在充分考虑System-PDN和INFO SI/PI的情况下，在仿真和验证中，速度为4.8Gbps的INFO I/ o均达到了70%的ETT眼窗。针对未来更高的系统带宽需求，讨论了核功率合并与分离的设计权衡。
{"title":"Signal and Power Integrity Analysis of InFO Interconnect for Networking Application","authors":"Po-Hao Chang, C. Hsieh, Chun-Wei Chang, Chih-Lun Chuang, Chen-Feng Chiang","doi":"10.1109/ECTC.2018.00258","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00258","url":null,"abstract":"MediaTek INFO Link (M-Link) is worldwide first successful homogeneous DIE-to-DIE data link for high-speed networking application. Considering benefits from large on-die capacitance of core-power domain, merged power domain for INFO and core-power is adopted. However, in order to sustain over 250W external core-power interference and internal INFO SSO noises, optimization of whole band target impedances to against these noises becomes one of major challenges. In this paper, a systematic approach to design M-Link in the extreme condition is proposed. In first part of paper, modulated chip power model (MCPM) technology is applied to ensure System-PDN. MCPM is modulated CPM which serves as new current load to represent mid-frequency bands interference for system level time domain noise simulations. In the second part, input pattern modulation (IPM) was applied to predict worst power ripple on INFO I/Os and jitter from sensitive circuit critical path. The IPM methodology serves as a total assessment considering all SI/PI impact to ensure a robust design. Finally, given fully consideration on System-PDN and INFO SI/PI, INFO I/Os with 4.8Gbps speed achieved 70% ETT eye windows in both simulation and verification. The design trade-off on core-power merged and separated is also discussed for future higher system bandwidth requirement.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"1720-1725"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76505565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tiwei Wei, H. Oprins, V. Cherman, I. De Wolf, E. Beyne, Shoufeng Yang, M. Baelmans
Liquid jet impingement cooling is a very efficient cooling technology for high performance devices. Previous studies demonstrated that polymers can be used as a cost effective alternative for Si for the fabrication of impingement coolers. The recent developments in additive manufacturing or 3D printing technology enable the potential to fabricate low cost polymer coolers with complex internal channels. In this paper, the use of 3D printing is discussed for the fabrication of a chip level polymer impingement cooler. The paper presents the cooler design, the manufacturability aspects and the characterization of several 3D printed coolers with different nozzles arrays. The challenges and opportunities for the use of 3D printing for this applications are discussed. A methodology to provide design guidelines for 3D printed liquid impingement jet coolers is elaborated.
{"title":"3D Printed Liquid Jet Impingement Cooler: Demonstration, Opportunities and Challenges","authors":"Tiwei Wei, H. Oprins, V. Cherman, I. De Wolf, E. Beyne, Shoufeng Yang, M. Baelmans","doi":"10.1109/ECTC.2018.00360","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00360","url":null,"abstract":"Liquid jet impingement cooling is a very efficient cooling technology for high performance devices. Previous studies demonstrated that polymers can be used as a cost effective alternative for Si for the fabrication of impingement coolers. The recent developments in additive manufacturing or 3D printing technology enable the potential to fabricate low cost polymer coolers with complex internal channels. In this paper, the use of 3D printing is discussed for the fabrication of a chip level polymer impingement cooler. The paper presents the cooler design, the manufacturability aspects and the characterization of several 3D printed coolers with different nozzles arrays. The challenges and opportunities for the use of 3D printing for this applications are discussed. A methodology to provide design guidelines for 3D printed liquid impingement jet coolers is elaborated.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"2389-2396"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86233380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Fukushima, Y. Susumago, H. Kino, Tetsu Tanaka, A. Alam, A. Hanna, S. Iyer
We have developed new flexible hybrid electronics (FHE) systems called FlexTrateTM that is high-performance and scalable flexible substrates embedding heterogeneous inorganic monocrystalline semiconductor dielets. In this work, a modified die-first FOWLP technology with surface tension-driven multichip self-assembly is used for the fabrication of FlexTrateTM. The detailed self-assembly for the FlexTrateTM application is described to precisely and highly integrate heterogeneous dielets embedded in PDMS as a flexible substrate in wafer-level processing.
{"title":"Self-Assembly Technologies for FlexTrate™","authors":"T. Fukushima, Y. Susumago, H. Kino, Tetsu Tanaka, A. Alam, A. Hanna, S. Iyer","doi":"10.1109/ECTC.2018.00275","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00275","url":null,"abstract":"We have developed new flexible hybrid electronics (FHE) systems called FlexTrateTM that is high-performance and scalable flexible substrates embedding heterogeneous inorganic monocrystalline semiconductor dielets. In this work, a modified die-first FOWLP technology with surface tension-driven multichip self-assembly is used for the fabrication of FlexTrateTM. The detailed self-assembly for the FlexTrateTM application is described to precisely and highly integrate heterogeneous dielets embedded in PDMS as a flexible substrate in wafer-level processing.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"13 1","pages":"1836-1841"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86237157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Shih, Ryan Chen, PeterBS Chen, Ying-Chih Lee, Karenyu Chen, Ian Hu, Tang-Yuan Chen, Lung Tsai, Eatice Chen, E. Tsai, D. Tarng, C. Hung
In recent years, Fan-Out (FO) packages have become widely used in handheld, mobile consumer and internet of things (IoT) devices. FO packaging enables a greater I/O density as well as multiple components in the same package. Several types of FO packaging are offered in the market today, for example; embedded wafer level BGA (eWLB), M-Series™ as well as a flip chip based structure referred to as Fan-out Chip-Last Package (FOCLP) The work compares the mechanical and thermal performance of the three types of FO packages. Finite element analyses were carried out to examine mechanical performance metrics, including warpage, stress in the extreme low-k (ELK) interconnect and board level solder joint reliability. Thermal simulations were completed to compare the thermal dissipation differences among the FO package types. The paper concludes with a summary of the advantages and disadvantages of the different FO structures studied.
{"title":"Comparative Study on Mechanical and Thermal Performance of eWLB, M-Series™ and Fan-Out Chip Last Packages","authors":"M. Shih, Ryan Chen, PeterBS Chen, Ying-Chih Lee, Karenyu Chen, Ian Hu, Tang-Yuan Chen, Lung Tsai, Eatice Chen, E. Tsai, D. Tarng, C. Hung","doi":"10.1109/ECTC.2018.00252","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00252","url":null,"abstract":"In recent years, Fan-Out (FO) packages have become widely used in handheld, mobile consumer and internet of things (IoT) devices. FO packaging enables a greater I/O density as well as multiple components in the same package. Several types of FO packaging are offered in the market today, for example; embedded wafer level BGA (eWLB), M-Series™ as well as a flip chip based structure referred to as Fan-out Chip-Last Package (FOCLP) The work compares the mechanical and thermal performance of the three types of FO packages. Finite element analyses were carried out to examine mechanical performance metrics, including warpage, stress in the extreme low-k (ELK) interconnect and board level solder joint reliability. Thermal simulations were completed to compare the thermal dissipation differences among the FO package types. The paper concludes with a summary of the advantages and disadvantages of the different FO structures studied.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"111 1","pages":"1676-1682"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73968814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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