In an effort to replace Pb-based solders commonly used in high-temperature electronics (operating at 200°C or higher) with a new high-temperature capable material, we have developed a transient liquid phase (TLP) bonding between bismuth (Bi) and nickel (Ni) in our previous study. To address the reliability concerns and also to warrant the manufacturing efficiency of the TLP bonds, the current study was focused on the optimization of the interlayer structure and alloying via: i) thin bond-line-thickness (BLT) (< 10 um), ii) intermediate BLT (20-40 um), and iii) thick BLT (> 60 um). These TLP bonded coupons were then tested for bonding reaction, microstructure development, and mechanical reliability. A thin BLT was made via sputter deposition of Bi on Ni-metallized die, which enabled a Ni layer (? 1 um) remaining during reflow without being completely consumed. The intermediate BLT sample was made using a Bi preform as in our previous study. For the thick BLT case, a powder/paste of Bi-xNi (from x=0 to 21.9 wt.%) was used. In particular, as pure Bi will not react with the Cu metallized surface (or Cu substrate), an interlayer consisting of Bi-Ni mixed powder/paste will enable Cu surface to be bondable with this TLP system. In this paper, the reflow conditions and the interlayer microstructures for the Bi-Ni TLP bonding with the three different approaches are discussed.
{"title":"Effects of the Interlayer Thickness and Alloying on the Reliability of Transient Liquid Phase (TLP) Bonding","authors":"Junghyun Cho, F. Dong, L. Yin, D. Shaddock","doi":"10.1109/ECTC.2018.00087","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00087","url":null,"abstract":"In an effort to replace Pb-based solders commonly used in high-temperature electronics (operating at 200°C or higher) with a new high-temperature capable material, we have developed a transient liquid phase (TLP) bonding between bismuth (Bi) and nickel (Ni) in our previous study. To address the reliability concerns and also to warrant the manufacturing efficiency of the TLP bonds, the current study was focused on the optimization of the interlayer structure and alloying via: i) thin bond-line-thickness (BLT) (< 10 um), ii) intermediate BLT (20-40 um), and iii) thick BLT (> 60 um). These TLP bonded coupons were then tested for bonding reaction, microstructure development, and mechanical reliability. A thin BLT was made via sputter deposition of Bi on Ni-metallized die, which enabled a Ni layer (? 1 um) remaining during reflow without being completely consumed. The intermediate BLT sample was made using a Bi preform as in our previous study. For the thick BLT case, a powder/paste of Bi-xNi (from x=0 to 21.9 wt.%) was used. In particular, as pure Bi will not react with the Cu metallized surface (or Cu substrate), an interlayer consisting of Bi-Ni mixed powder/paste will enable Cu surface to be bondable with this TLP system. In this paper, the reflow conditions and the interlayer microstructures for the Bi-Ni TLP bonding with the three different approaches are discussed.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"46 1","pages":"551-556"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82661626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Crackstops are vital parts of the back-end-of-line (BEOL) chip stack in electronic packages and are often responsible for preventing catastrophic mechanical and electrical breakdown within a semiconductor device. The present work is focused on evaluating the fracture toughness of crack-stops using a mixed-mode bending test structure. The test fixture designed as part of this study enables crack propagation in the BEOL under a wide range of mode-mixities which mimics the stress drivers within an organic flip-chip package. Techniques for optimized sample preparation beginning with a processed wafer to the final, test-ready coupon for mixed-mode testing will be discussed. The designed sample preparation tools and methods allow for the precise driving of a crack to specific features within the BEOL. Rigorous analytical verifications were conducted to validate the results obtained from the tests and it will be demonstrated that the test is highly effective for understanding the factors that can influence the strength of a crackstop and the mechanics of its strength degradation under prolonged moisture exposure.
{"title":"Back-end-of-Line (BEOL) Mechanical Integrity Evaluation: A Mixed-Mode Double Cantilever Beam Test for Crackstop Strength Assessment","authors":"Max Cioban, Tuhin Sinha, T. Shaw","doi":"10.1109/ECTC.2018.00075","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00075","url":null,"abstract":"Crackstops are vital parts of the back-end-of-line (BEOL) chip stack in electronic packages and are often responsible for preventing catastrophic mechanical and electrical breakdown within a semiconductor device. The present work is focused on evaluating the fracture toughness of crack-stops using a mixed-mode bending test structure. The test fixture designed as part of this study enables crack propagation in the BEOL under a wide range of mode-mixities which mimics the stress drivers within an organic flip-chip package. Techniques for optimized sample preparation beginning with a processed wafer to the final, test-ready coupon for mixed-mode testing will be discussed. The designed sample preparation tools and methods allow for the precise driving of a crack to specific features within the BEOL. Rigorous analytical verifications were conducted to validate the results obtained from the tests and it will be demonstrated that the test is highly effective for understanding the factors that can influence the strength of a crackstop and the mechanics of its strength degradation under prolonged moisture exposure.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"467-475"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82752029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study explores the analysis and the design of a passive input matching circuit used in low power wake-up receivers. The results show that by using a combination of on-chip components, package parasitics, and an off-chip inductor, a passive gain of 23.23 dB can be achieved at 915 MHz while achieving a return loss of -15 dB.
{"title":"Design Considerations of a Matching Circuit for Low Power Wake-Up Receivers","authors":"J. Ou","doi":"10.1109/ECTC.2018.00351","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00351","url":null,"abstract":"This study explores the analysis and the design of a passive input matching circuit used in low power wake-up receivers. The results show that by using a combination of on-chip components, package parasitics, and an off-chip inductor, a passive gain of 23.23 dB can be achieved at 915 MHz while achieving a return loss of -15 dB.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"48 1","pages":"2332-2335"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89088385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ko, Henry Yang, J. Lau, Ming Li, Margie Li, Curry Lin, JW Lin, Tony Chen, Iris Xu, Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Q. Yong, N. Fan, E. Kuah, Zhang Li, K. Tan, Y. Cheung, Eric Ng, Wu Kai, J. Hao, R. Beica, M. Lin, Y. Chen, Zhong Cheng, Koh Sau Wee, Jiang Ran, Cao Xi, S. Lim, Nc Lee, Mian Tao, J. Lo, Ricky S. W. Lee
The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOPLP (fan-out panel-level packaging) method are investigated in this study. Emphasis is placed on the application of a special assembly process called Uni-SIP (Uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the thermal cycling test is also performed.
{"title":"Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration","authors":"C. Ko, Henry Yang, J. Lau, Ming Li, Margie Li, Curry Lin, JW Lin, Tony Chen, Iris Xu, Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Q. Yong, N. Fan, E. Kuah, Zhang Li, K. Tan, Y. Cheung, Eric Ng, Wu Kai, J. Hao, R. Beica, M. Lin, Y. Chen, Zhong Cheng, Koh Sau Wee, Jiang Ran, Cao Xi, S. Lim, Nc Lee, Mian Tao, J. Lo, Ricky S. W. Lee","doi":"10.1109/ECTC.2018.00061","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00061","url":null,"abstract":"The design, materials, process, fabrication, and reliability of a heterogeneous integration of 4 chips and 4 capacitors by a FOPLP (fan-out panel-level packaging) method are investigated in this study. Emphasis is placed on the application of a special assembly process called Uni-SIP (Uni-substrate-integrated-package) for fabricating the RDLs (redistribution layers) of the FOPLP. The ABF (Ajinomoto build-up film) is used as the dielectric of the RDLs and is built up by the SAP (semi-additive process). The electroless Cu is used to make the seed layer, the LDI (laser direct imaging) is used for opening the photoresist, and the PCB (printed circuit board) Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the thermal cycling test is also performed.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"143 11","pages":"355-363"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91402455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a land grid array-type ultra-small shielded module that has a 2.4 GHz slot antenna is presented. Slots are patterned on both an interposer and a shield layer. The slots are connected at the side of the interposer and compose the slot antenna. A large part of the slot antenna is formed on the shield deposited on the surface of the module. The slot on the interposer is short and occupy a small area, therefore the slot antenna allows the area of the interposer to be reduced. In addition to that the slot antenna reduces the keep-out zone in which no wires can be laid out on the board. It is because the area of the slot on the interposer is small. A prototype of the module with a Bluetooth Low Energy chip was fabricated. The volume of the prototype is 5.25 x 9.0 x 1.0 mm3. The keep-out zone of the module is 9.0 mm2. The module has received Japanese modular approval certification because it contains all the elements for wireless communication except for a power supply.
本文提出了一种具有2.4 GHz缝隙天线的地网阵列式超小型屏蔽模块。槽在中间层和屏蔽层上都有图案。所述槽连接在所述插线器侧面，并组成所述槽天线。槽天线的很大一部分是在沉积在模块表面的屏蔽上形成的。所述插口上的槽短且占用的面积小，因此所述槽天线允许减小所述插口的面积。此外，槽天线减少了保持区，其中没有电线可以在板上铺设。这是因为中间层上的槽面积很小。制作了带有低功耗蓝牙芯片的模块原型。样机的体积为5.25 x 9.0 x 1.0 mm3。模块的防静电区为9.0 mm2。该模块包含了除电源之外的所有无线通信元件，因此获得了日本模块化认证。
{"title":"Small Shielded Bluetooth Module Equipped with Slot Antenna on the Surface","authors":"K. Yamada, M. Sano, M. Higaki, A. Happoya","doi":"10.1109/ECTC.2018.00036","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00036","url":null,"abstract":"In this paper, a land grid array-type ultra-small shielded module that has a 2.4 GHz slot antenna is presented. Slots are patterned on both an interposer and a shield layer. The slots are connected at the side of the interposer and compose the slot antenna. A large part of the slot antenna is formed on the shield deposited on the surface of the module. The slot on the interposer is short and occupy a small area, therefore the slot antenna allows the area of the interposer to be reduced. In addition to that the slot antenna reduces the keep-out zone in which no wires can be laid out on the board. It is because the area of the slot on the interposer is small. A prototype of the module with a Bluetooth Low Energy chip was fabricated. The volume of the prototype is 5.25 x 9.0 x 1.0 mm3. The keep-out zone of the module is 9.0 mm2. The module has received Japanese modular approval certification because it contains all the elements for wireless communication except for a power supply.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"119 1","pages":"185-190"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91534298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Schumann, Xiaochen Zhu, J. Neff, A. Hebard, H. Zmuda, Y. Yoon
Thin films of barium titanate (BTO) are controllably grown to produce two different memory applications: ferroelectric Schottky diodes and resistive switching cells. The entire structure and fabrication of the two cells are identical, except for a slight adjustment to the calcination temperature for the BTO films. Films calcined at 800°C were ferroelectric and were used to create the ferroelectric Schottky diode. Conversely, films calcined at 700°C displayed resistive switching behavior and were used to create memristor cells. The ferroelectric Schottky diodes showed an ON/OFF ratio of over three orders of magnitude and the resistive switching cells showed an ON/OFF ratio of nearly two orders of magnitude, though both can likely be improved through electrode optimization. The identification of the critical process parameter shows that both memory cells can be fabricated on the same die with nearly identical processes, which would reduce process complexity for creating multiple advanced memories on a single die.
{"title":"Solely Calcine Controlled Ferroelectricity and Resistivity of Barium Titanate Thin Films and Their Advanced Memory Applications","authors":"T. Schumann, Xiaochen Zhu, J. Neff, A. Hebard, H. Zmuda, Y. Yoon","doi":"10.1109/ECTC.2018.00214","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00214","url":null,"abstract":"Thin films of barium titanate (BTO) are controllably grown to produce two different memory applications: ferroelectric Schottky diodes and resistive switching cells. The entire structure and fabrication of the two cells are identical, except for a slight adjustment to the calcination temperature for the BTO films. Films calcined at 800°C were ferroelectric and were used to create the ferroelectric Schottky diode. Conversely, films calcined at 700°C displayed resistive switching behavior and were used to create memristor cells. The ferroelectric Schottky diodes showed an ON/OFF ratio of over three orders of magnitude and the resistive switching cells showed an ON/OFF ratio of nearly two orders of magnitude, though both can likely be improved through electrode optimization. The identification of the critical process parameter shows that both memory cells can be fabricated on the same die with nearly identical processes, which would reduce process complexity for creating multiple advanced memories on a single die.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"1402-1406"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90349586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Do-won Kim, Hong Yu Li, K. Chang, W. Loh, S. Chong, H. Cai, B. Surya
In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated circuit (Si-PIC) in SOI which has TSV for electrical interconnection is flip-chip bonded on a Si interposer using electrochemical plating (ECP) bumps of 90 µm-diameter in this 3D EPIC packaging. A 750 ?-cm of high-resistivity SOI and silicon wafers are used for PIC chip with TSV and interposer respectively. Measured insertion loss (S21) for the 3D EPIC packaged test vehicle using TSV is less than 3.5dB and return loss (S11) is less than -13dB up to 50 GHz. This high-bandwidth 3D EPIC packaging platform can be applied for the system-on-packaging (SOP) modules and subsystems such as optical transceiver (TRx) and radio-over-fiber (ROF) solutions.
{"title":"3D System-on-Packaging Using Through Silicon Via on SOI for High-Speed Optcal Interconnections with Silicon Photonics Devices for Application of 400 Gbps and Beyond","authors":"Do-won Kim, Hong Yu Li, K. Chang, W. Loh, S. Chong, H. Cai, B. Surya","doi":"10.1109/ECTC.2018.00129","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00129","url":null,"abstract":"In this study, 3D electronic-photonic integrated circuits (EPIC) packaging using through silicon vias (TSV) has been demonstrated. Silicon photonic integrated circuit (Si-PIC) in SOI which has TSV for electrical interconnection is flip-chip bonded on a Si interposer using electrochemical plating (ECP) bumps of 90 µm-diameter in this 3D EPIC packaging. A 750 ?-cm of high-resistivity SOI and silicon wafers are used for PIC chip with TSV and interposer respectively. Measured insertion loss (S21) for the 3D EPIC packaged test vehicle using TSV is less than 3.5dB and return loss (S11) is less than -13dB up to 50 GHz. This high-bandwidth 3D EPIC packaging platform can be applied for the system-on-packaging (SOP) modules and subsystems such as optical transceiver (TRx) and radio-over-fiber (ROF) solutions.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"65 1","pages":"834-840"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88849706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The unknown statistical distributions of two effective elastic properties of Sn-3.0Ag-0.5Cu solder joint of leadless chip resistors (LCR) are determined while considering the statistical variations of six other input variables including die thickness, solder joint height, termination length, and thickness and elastic moduli of a printed circuit board. The cyclic bending test results of the LCR assemblies are used to obtain the probability density functions of the effective elastic properties of the SAC305 solder by statistical model calibration in conjunction with an advanced uncertainty propagation analysis. The statistical distribution of cycles to failure of the same LCRs subjected to a different loading level is predicted accurately by the calibrated model, which corroborates the validity of the proposed approach.
{"title":"Prediction of Statistical Distribution of Vibration-Induced Solder Fatigue Failure Considering Intrinsic Variations of Mechanical Properties of Anisotropic Sn-Rich Solder Alloys","authors":"Hsiu-Ping Wei, Yu-Hsiang Yang, Bulong Wu, B. Han","doi":"10.1109/ECTC.2018.00115","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00115","url":null,"abstract":"The unknown statistical distributions of two effective elastic properties of Sn-3.0Ag-0.5Cu solder joint of leadless chip resistors (LCR) are determined while considering the statistical variations of six other input variables including die thickness, solder joint height, termination length, and thickness and elastic moduli of a printed circuit board. The cyclic bending test results of the LCR assemblies are used to obtain the probability density functions of the effective elastic properties of the SAC305 solder by statistical model calibration in conjunction with an advanced uncertainty propagation analysis. The statistical distribution of cycles to failure of the same LCRs subjected to a different loading level is predicted accurately by the calibrated model, which corroborates the validity of the proposed approach.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"217 1","pages":"741-747"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89103285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. de Vos, S. Van Huylenbroeck, A. Jourdain, N. Heylen, Lan Peng, G. Jamieson, N. Tutunjyan, S. Sardo, Andy Miller, E. Beyne
This paper presents face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination a novel 1µm diameter via last connection between top and bottom wafers, called "hole-in-one TSV". This scheme reduces besides the interconnection pitch and also the number of processing steps. The hole-in-one TSV is introducing an innovating integration modification. With the introduction of a cavity etched in the top wafer prior to W2W bonding, the via last etch process is simplified. The etch time of the dielectric part of the TSV etch is heavily reduced, minimizing the over etch time on the top landing metal to open the landing wafer's metal pad. Critical integration steps like CMP processes, wafer bonding and thinning to 5µm Si thickness are highlighted, together with alignment tolerances and connectivity yield between the bonded 300mm Si wafers.
本文提出了一种采用sicn - sicn介电键合的面对面晶圆键合(W2W)技术，并结合了一种新颖的直径为1 μ m的顶部和底部晶圆之间的最后连接，称为“一孔入洞TSV”。该方案不仅减少了互连间距，而且减少了处理步骤。一杆进洞TSV引入了创新的集成修改。在W2W键合之前，在顶部晶圆上引入了一个蚀刻腔，从而简化了通过最后的蚀刻过程。大大减少了TSV蚀刻的介电部分的蚀刻时间，最大限度地减少了顶部着陆金属打开着陆晶圆金属垫的过度蚀刻时间。重点介绍了关键集成步骤，如CMP工艺、晶圆键合和减薄至5 μ m Si厚度，以及键合的300mm Si晶圆之间的对准公差和连接性良率。
{"title":"\"Hole-in-One TSV\", a New Via Last Concept for High Density 3D-SOC Interconnects","authors":"J. de Vos, S. Van Huylenbroeck, A. Jourdain, N. Heylen, Lan Peng, G. Jamieson, N. Tutunjyan, S. Sardo, Andy Miller, E. Beyne","doi":"10.1109/ECTC.2018.00228","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00228","url":null,"abstract":"This paper presents face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination a novel 1µm diameter via last connection between top and bottom wafers, called \"hole-in-one TSV\". This scheme reduces besides the interconnection pitch and also the number of processing steps. The hole-in-one TSV is introducing an innovating integration modification. With the introduction of a cavity etched in the top wafer prior to W2W bonding, the via last etch process is simplified. The etch time of the dielectric part of the TSV etch is heavily reduced, minimizing the over etch time on the top landing metal to open the landing wafer's metal pad. Critical integration steps like CMP processes, wafer bonding and thinning to 5µm Si thickness are highlighted, together with alignment tolerances and connectivity yield between the bonded 300mm Si wafers.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"1499-1504"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80706883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kwang-Seong Choi, Wagno Alves Braganca Junior, leeseul Jeong, Keon‐Soo Jang, Seok-Hwan Moon, Hyun-Cheol Bae, Y. Eom, Min-Kyo Cho, S. I. Chang
Flexible displays and electronics are emerging technology. A PET substrate is one the strong candidate substrate materials for the applications, however, its low thermal stability limited its penetration depth in the market. We propose the interconnection process using laser and hybrid underfill as a technical solution to prevent the thermal deformation of a PET film during the interconnection process. The LED module array is successfully fabricated on a PET substrate using laser and hybrid underfill. The process features a very short cycle time and tiling process for the high throughput.
{"title":"Interconnection Process Using Laser and Hybrid Underfill for LED Array Module on PET Substrate","authors":"Kwang-Seong Choi, Wagno Alves Braganca Junior, leeseul Jeong, Keon‐Soo Jang, Seok-Hwan Moon, Hyun-Cheol Bae, Y. Eom, Min-Kyo Cho, S. I. Chang","doi":"10.1109/ECTC.2018.00238","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00238","url":null,"abstract":"Flexible displays and electronics are emerging technology. A PET substrate is one the strong candidate substrate materials for the applications, however, its low thermal stability limited its penetration depth in the market. We propose the interconnection process using laser and hybrid underfill as a technical solution to prevent the thermal deformation of a PET film during the interconnection process. The LED module array is successfully fabricated on a PET substrate using laser and hybrid underfill. The process features a very short cycle time and tiling process for the high throughput.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"1567-1573"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80771012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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