Vincent Lafage, Y. Beilliard, A. Sridhar, T. Brunschwiler, D. Drouin
On-chip integration of voltage regulators could significantly improve performance of 3D ICs. However, integration of voltage regulators is difficult due to the size of inductors. To reduce inductor size, thin-film magnetic materials on glass substrates, which amplifies inductance values, should help on-chip inductor integration. Using Ni45Fe55 and Co80P20 magnetic materials, we successfully fabricated 2D core and coreless copper inductors, on both glass and silicon substrates for comparison purposes. Inductors on glass exhibit better performance than the ones fabricated on silicon. An inductance density of up to ~30 nH/mm² was reached.
{"title":"2D Magnetic Inductors for DC-DC Converters on Glass Interposer","authors":"Vincent Lafage, Y. Beilliard, A. Sridhar, T. Brunschwiler, D. Drouin","doi":"10.1109/ECTC.2018.00308","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00308","url":null,"abstract":"On-chip integration of voltage regulators could significantly improve performance of 3D ICs. However, integration of voltage regulators is difficult due to the size of inductors. To reduce inductor size, thin-film magnetic materials on glass substrates, which amplifies inductance values, should help on-chip inductor integration. Using Ni45Fe55 and Co80P20 magnetic materials, we successfully fabricated 2D core and coreless copper inductors, on both glass and silicon substrates for comparison purposes. Inductors on glass exhibit better performance than the ones fabricated on silicon. An inductance density of up to ~30 nH/mm² was reached.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"14 1","pages":"2055-2060"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84035374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Shan, Daniel Freidman, Craig Kennedy, Warren Persak, K. Lau
A backward compatible PCIe connector targeting 25-32Gb/s per-channel data rates was jointly developed under a collaboration between IBM Research and Amphenol Corporation. To demonstrate the improvement on loss/reflection/crosstalk, an evaluation board with both original and new PCIe connector footprints was designed, fabricated, and tested. 3D full-wave simulations were performed and correlated with measurement results. Optimal pad and ground configurations were used to update PCIe channel budget/specifications and provide design recommendations for potential PCIe Gen5 channels.
{"title":"Backward Compatible Connectors for Next Generation PCIe Electrical I/O","authors":"L. Shan, Daniel Freidman, Craig Kennedy, Warren Persak, K. Lau","doi":"10.1109/ECTC.2018.00270","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00270","url":null,"abstract":"A backward compatible PCIe connector targeting 25-32Gb/s per-channel data rates was jointly developed under a collaboration between IBM Research and Amphenol Corporation. To demonstrate the improvement on loss/reflection/crosstalk, an evaluation board with both original and new PCIe connector footprints was designed, fabricated, and tested. 3D full-wave simulations were performed and correlated with measurement results. Optimal pad and ground configurations were used to update PCIe channel budget/specifications and provide design recommendations for potential PCIe Gen5 channels.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"128 1","pages":"1798-1804"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78090921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Cherman, M. Lofrano, Mario Gonzalez, F. Cadacio, K. Rebibis, E. Beyne, A. Takano, M. Higashi
In this work the focus is on thermo-mechanical aspects of Chip Package Interaction (CPI) in flip-chip Chip Scale packages (fcCSP) packages. To minimize mechanical stress induced during flip-chip process, the laminate substrate with very low coefficient of thermal expansion (CTE) of the core material (?5 ppm/°C) is used. Mechanical stress induced in Si chip after every main assembly step is measured using the proprietary chip with integrated stress sensors and is simulated using calibrated finite element models. In particular, two flip-chip processes, i.e. Mass Reflow (MR) and Thermo-Compression Bonding (TCB) are benchmarked. The effect of application of capillary underfill (CUF) on mechanical stress is separately studied and shown to be not significant. The CPI effect of low-CTE substrate on mechanical stress is benchmarked with that induced by the substrate with conventional thermo-mechanical properties. The benefits of lowering core' CTE in terms of stress are clearly demonstrated. This is also confirmed by finite element modeling which reveals that stress induced in Si after flip-chip die attach process is very sensitive to the effective CTE of the substrate.
{"title":"Evaluation of Mechanical Stress Induced During IC Packaging","authors":"V. Cherman, M. Lofrano, Mario Gonzalez, F. Cadacio, K. Rebibis, E. Beyne, A. Takano, M. Higashi","doi":"10.1109/ECTC.2018.00325","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00325","url":null,"abstract":"In this work the focus is on thermo-mechanical aspects of Chip Package Interaction (CPI) in flip-chip Chip Scale packages (fcCSP) packages. To minimize mechanical stress induced during flip-chip process, the laminate substrate with very low coefficient of thermal expansion (CTE) of the core material (?5 ppm/°C) is used. Mechanical stress induced in Si chip after every main assembly step is measured using the proprietary chip with integrated stress sensors and is simulated using calibrated finite element models. In particular, two flip-chip processes, i.e. Mass Reflow (MR) and Thermo-Compression Bonding (TCB) are benchmarked. The effect of application of capillary underfill (CUF) on mechanical stress is separately studied and shown to be not significant. The CPI effect of low-CTE substrate on mechanical stress is benchmarked with that induced by the substrate with conventional thermo-mechanical properties. The benefits of lowering core' CTE in terms of stress are clearly demonstrated. This is also confirmed by finite element modeling which reveals that stress induced in Si after flip-chip die attach process is very sensitive to the effective CTE of the substrate.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"76 1","pages":"2168-2173"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76674702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Alghoul, M. Yadav, S. Thekkut, R. Sivasubramony, C. M. Greene, M. Poliks, P. Borgesen, L. Wentlent, M. Meilunas, N. Stoffel, D. Shaddock, L. Yin
The use of commercial electronics components with Tin-Silver-Copper solder bumps normally calls for relatively high cost substrates, posing a challenge for disposable (inexpensive) products. The present effort addresses the feasibility of reducing reflow temperatures through the use of a eutectic Tin-Bismuth solder paste for products that do not have to survive significant thermal cycling. A set of experiments was conducted to assess the effects of paste volume and reflow profiles on solder joint strength and low cycle fatigue resistance. Both strength and fatigue resistance tended to decrease with decreasing peak temperature and paste volume, but indications are that performances comparable to those of conventionally reflowed Tin-Silver-Copper solder joints can be achieved even with laser reflow and a peak temperature as low as 160C. This offers promise for the use of low cost substrates such as PET.
{"title":"Low Temperature Solder Attach of SnAgCu Bumped Components for a Flexible Hybrid Electronics Based Medical Monitor","authors":"T. Alghoul, M. Yadav, S. Thekkut, R. Sivasubramony, C. M. Greene, M. Poliks, P. Borgesen, L. Wentlent, M. Meilunas, N. Stoffel, D. Shaddock, L. Yin","doi":"10.1109/ECTC.2018.00145","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00145","url":null,"abstract":"The use of commercial electronics components with Tin-Silver-Copper solder bumps normally calls for relatively high cost substrates, posing a challenge for disposable (inexpensive) products. The present effort addresses the feasibility of reducing reflow temperatures through the use of a eutectic Tin-Bismuth solder paste for products that do not have to survive significant thermal cycling. A set of experiments was conducted to assess the effects of paste volume and reflow profiles on solder joint strength and low cycle fatigue resistance. Both strength and fatigue resistance tended to decrease with decreasing peak temperature and paste volume, but indications are that performances comparable to those of conventionally reflowed Tin-Silver-Copper solder joints can be achieved even with laser reflow and a peak temperature as low as 160C. This offers promise for the use of low cost substrates such as PET.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"50 1","pages":"948-953"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81387684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Muhammad Ali, Fuhan Liu, A. Watanabe, P. Raj, V. Sundaram, M. Tentzeris, R. Tummala
This paper demonstrates the first panel-based ultra-miniaturized filters with footprint smaller than half of the free-space wavelength at the operating frequencies of 28 and 39 GHz bands for 5G and mm-wave small-cell applications. The thin-film filters can be utilized either as ultra-thin integrated passive devices (IPDs) or embedded into the module substrates. Two filter types: lowpass and bandpass, with three topologies in total, are modeled, designed and fabricated on precision thin-film build-up layers on glass and traditional laminate cores. The modeling, design and optimization phase included the considerations of fabrication tolerances and testability of the filters. Glass is an ideal core material for mm-wave 5G modules and IPDs since it combines the benefits of ceramics for high frequency electrical performance, laminates for large panel processing and low cost, silicon-like dimensional stability and precision patterning, which is essential for mm-wave circuits. Unlike printing used in ceramics, or subtractive etching used in multilayer organics (MLO), this research utilizes semi-additive patterning (SAP) process to form high precision, multilayer redistribution layers (RDL) to design ultra-compact filter topologies with low insertion loss and improved stopband rejection, due to the close-to-ideal translation of lumped-to-distributed components. The simulated results of bandwidth, in-band insertion loss and out-of-band rejection of filters show excellent correlation with the measured results.
{"title":"Miniaturized High-Performance Filters for 5G Small-Cell Applications","authors":"Muhammad Ali, Fuhan Liu, A. Watanabe, P. Raj, V. Sundaram, M. Tentzeris, R. Tummala","doi":"10.1109/ECTC.2018.00164","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00164","url":null,"abstract":"This paper demonstrates the first panel-based ultra-miniaturized filters with footprint smaller than half of the free-space wavelength at the operating frequencies of 28 and 39 GHz bands for 5G and mm-wave small-cell applications. The thin-film filters can be utilized either as ultra-thin integrated passive devices (IPDs) or embedded into the module substrates. Two filter types: lowpass and bandpass, with three topologies in total, are modeled, designed and fabricated on precision thin-film build-up layers on glass and traditional laminate cores. The modeling, design and optimization phase included the considerations of fabrication tolerances and testability of the filters. Glass is an ideal core material for mm-wave 5G modules and IPDs since it combines the benefits of ceramics for high frequency electrical performance, laminates for large panel processing and low cost, silicon-like dimensional stability and precision patterning, which is essential for mm-wave circuits. Unlike printing used in ceramics, or subtractive etching used in multilayer organics (MLO), this research utilizes semi-additive patterning (SAP) process to form high precision, multilayer redistribution layers (RDL) to design ultra-compact filter topologies with low insertion loss and improved stopband rejection, due to the close-to-ideal translation of lumped-to-distributed components. The simulated results of bandwidth, in-band insertion loss and out-of-band rejection of filters show excellent correlation with the measured results.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"1068-1075"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82297299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Maniar, Georg Konstantin, A. Kabakchiev, P. Binkele, S. Schmauder
Solder joints in automotive electronic assemblies are exposed to thermomechanical and vibrational loads. Usually, passive thermal cycling results in thermomechanical loads in the low strain rate plastic and creep regime of the solder alloy. In the case of vibrational loads, high strain rate plastic deformations in solder interconnections are expected. In order to investigate the deformation and failure behavior of the solder material in the high strain rate regime, we performed several high cycle fatigue (HCF) experiments on standardized specimens of a SnAgCu alloy under varying mean stresses and ambient temperatures. As a first step, high cycle fatigue tests with a frequency of 40 Hz at room temperature have been performed. From a statistical evaluation of the number of cycles to failure at different stress amplitudes and zero mean stress, we obtained a high cycle fatigue Woehler curve. Subsequently, the mean stress and temperature levels were changed, and the load frequency has been kept constant. The aim of this high cycle fatigue Woehler experiments was to explore the temperature and mean stress effects on the fatigue performance of the solder alloy. In order to assess the reliability of a solder ball grid array (BGA) under vibrational loading by means of finite elements (FE) simulations, a viscoplastic material model is calibrated based on the experimentally observed stress-strain material behavior in the HCF measurement. FE simulations using a fatigue material model were used to address the lifetime of the BGA solder joints under vibration during electrodynamic shaker testing on board level. The FE-based lifetime prognosis is discussed and compared to experimental statistical failure data of real solder joints obtained from electrodynamic shaker testing.
{"title":"Experimental Investigation of Temperature and Mean Stress Effects on High Cycle Fatigue Behavior of SnAgCu-Solder Alloy","authors":"Y. Maniar, Georg Konstantin, A. Kabakchiev, P. Binkele, S. Schmauder","doi":"10.1109/ECTC.2018.00249","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00249","url":null,"abstract":"Solder joints in automotive electronic assemblies are exposed to thermomechanical and vibrational loads. Usually, passive thermal cycling results in thermomechanical loads in the low strain rate plastic and creep regime of the solder alloy. In the case of vibrational loads, high strain rate plastic deformations in solder interconnections are expected. In order to investigate the deformation and failure behavior of the solder material in the high strain rate regime, we performed several high cycle fatigue (HCF) experiments on standardized specimens of a SnAgCu alloy under varying mean stresses and ambient temperatures. As a first step, high cycle fatigue tests with a frequency of 40 Hz at room temperature have been performed. From a statistical evaluation of the number of cycles to failure at different stress amplitudes and zero mean stress, we obtained a high cycle fatigue Woehler curve. Subsequently, the mean stress and temperature levels were changed, and the load frequency has been kept constant. The aim of this high cycle fatigue Woehler experiments was to explore the temperature and mean stress effects on the fatigue performance of the solder alloy. In order to assess the reliability of a solder ball grid array (BGA) under vibrational loading by means of finite elements (FE) simulations, a viscoplastic material model is calibrated based on the experimentally observed stress-strain material behavior in the HCF measurement. FE simulations using a fatigue material model were used to address the lifetime of the BGA solder joints under vibration during electrodynamic shaker testing on board level. The FE-based lifetime prognosis is discussed and compared to experimental statistical failure data of real solder joints obtained from electrodynamic shaker testing.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"1651-1658"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86884813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masahiko Shigaki, M. Suzuki, Takashi Kobayashi, Kentarou Takano, Takaki Tsuchida, Sotaro Hiramatsu, Y. Ueno, Tsuyoshi Kida, Shuuji Yoshida, T. Oshima
Electronic materials capable of high speed transmission with ultra-low-loss are strongly desired in the semiconductor market. So novel BT (Bis-Maleimide Triazine) material dedicating to latest high speed applications has been developed. In this work, new BT laminate material was designed to reduce transmission loss especially in high frequency range. The study consisted of three steps to reach the low loss material. Firstly, molecular structures of each BT resin component were investigated to approach to excellent electrical properties with low moisture dependence and strong adhesion to ultra-low profile (roughness) copper foils. Generally, laminate materials are requested to have stable behavior against water absorption because it often causes serious deterioration of signal transmission at high frequency. And stronger adhesion is required to make it possible to use ultra-low profile copper foils to reduce conductor loss. Secondly, screening of inorganic fillers were conducted to understand relations between some mechanical parameters and electrical properties. In this step, strong candidates were selected for the new BT material. Finally, laminates were fabricated and several evaluations were performed. The new BT laminate material showed sufficient adhesion to low profile copper foils and lower transmission loss than conventional materials. Furthermore, it was also confirmed that excellent electrical properties were maintained after long time thermal treatment at high temperature. Thus the effectiveness of the new BT laminate material for high frequency was successfully demonstrated.
{"title":"Development of Novel BT Laminate Material for Low-Loss and High Speed Transmission","authors":"Masahiko Shigaki, M. Suzuki, Takashi Kobayashi, Kentarou Takano, Takaki Tsuchida, Sotaro Hiramatsu, Y. Ueno, Tsuyoshi Kida, Shuuji Yoshida, T. Oshima","doi":"10.1109/ECTC.2018.00011","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00011","url":null,"abstract":"Electronic materials capable of high speed transmission with ultra-low-loss are strongly desired in the semiconductor market. So novel BT (Bis-Maleimide Triazine) material dedicating to latest high speed applications has been developed. In this work, new BT laminate material was designed to reduce transmission loss especially in high frequency range. The study consisted of three steps to reach the low loss material. Firstly, molecular structures of each BT resin component were investigated to approach to excellent electrical properties with low moisture dependence and strong adhesion to ultra-low profile (roughness) copper foils. Generally, laminate materials are requested to have stable behavior against water absorption because it often causes serious deterioration of signal transmission at high frequency. And stronger adhesion is required to make it possible to use ultra-low profile copper foils to reduce conductor loss. Secondly, screening of inorganic fillers were conducted to understand relations between some mechanical parameters and electrical properties. In this step, strong candidates were selected for the new BT material. Finally, laminates were fabricated and several evaluations were performed. The new BT laminate material showed sufficient adhesion to low profile copper foils and lower transmission loss than conventional materials. Furthermore, it was also confirmed that excellent electrical properties were maintained after long time thermal treatment at high temperature. Thus the effectiveness of the new BT laminate material for high frequency was successfully demonstrated.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"21-27"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87127071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ly May Chew, W. Schmitt, Christian Schwarzer, Jens Nachreiner
Die attach on power semiconductor using leadfree technique has attracted considerable interest. Silver sinter has demonstrated significant develop over the past years to be considered one of frontrunner non-lead containing die attach solution. Pressure silver sintering by far offers superior thermal and electrical conductivity properties which enables power electronics applications to operate at high temperature. Eliminating precious metal finishing on substrate would represent significant compatibility to present supply chain and lower the entry barrier to adopt silver sinter solution. This paper explores the development of a safe-to-use micro-Ag sinter paste for pressure sintering on bare Cu for power electronics packaging. We attached Ag metallized mechanical Si dies on silicon nitride active metal brazed copper substrates with Ag and Au metallization as well as without metallization by silver sintering at 230°C with a pressure of 10 MPa for 3 min. We observed that the average initial die shear strength for Ag metallized substrate is higher than that for Au metallized and bare Cu substrates. This observation points to the self-diffusion of Ag is faster than the silver/gold and silver/copper interdiffusion. The average die shear strength for all the samples increased remarkable after temperature cycling test with a condition of -40°C/+150°C and after a long term storage at 250°C. It is highly likely that the sintering process is not yet completed under the mild sintering process conditions we used in this study and consequently Ag, Au and Cu continued to diffuse during temperature cycling test and high temperature storage and as a result strengthen the sintered joint. It is strongly believed that the sintering process is completed after a certain time of storage at 250°C as we observed no further increase in die shear strength after 250 h storage. The bending test results further confirm the increase of bonding strength by thermal cycling. It is worth noting that cohesive break in the Cu layer was observed for Ag metallized and bare Cu substrates after 1000 h storage at 250°C. Elemental analysis by energy dispersive X-ray spectroscopy demonstrates that interdiffusion between Ag and Cu occurred during high temperature storage in which Cu from the substrate diffused into the silver sintered layer and concurrently Ag from the silver sintered layer diffused into the substrate. In contrast, we observed cohesive break in the sintered layer after 1000 h storage at 250°C for Au metallized substrate indicating that Au metallized layer acts as a barrier to prevent Cu from the substrate from diffusion into the silver sintered layer.
{"title":"Micro-Silver Sinter Paste Developed for Pressure Sintering on Bare Cu Surfaces under Air or Inert Atmosphere","authors":"Ly May Chew, W. Schmitt, Christian Schwarzer, Jens Nachreiner","doi":"10.1109/ECTC.2018.00056","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00056","url":null,"abstract":"Die attach on power semiconductor using leadfree technique has attracted considerable interest. Silver sinter has demonstrated significant develop over the past years to be considered one of frontrunner non-lead containing die attach solution. Pressure silver sintering by far offers superior thermal and electrical conductivity properties which enables power electronics applications to operate at high temperature. Eliminating precious metal finishing on substrate would represent significant compatibility to present supply chain and lower the entry barrier to adopt silver sinter solution. This paper explores the development of a safe-to-use micro-Ag sinter paste for pressure sintering on bare Cu for power electronics packaging. We attached Ag metallized mechanical Si dies on silicon nitride active metal brazed copper substrates with Ag and Au metallization as well as without metallization by silver sintering at 230°C with a pressure of 10 MPa for 3 min. We observed that the average initial die shear strength for Ag metallized substrate is higher than that for Au metallized and bare Cu substrates. This observation points to the self-diffusion of Ag is faster than the silver/gold and silver/copper interdiffusion. The average die shear strength for all the samples increased remarkable after temperature cycling test with a condition of -40°C/+150°C and after a long term storage at 250°C. It is highly likely that the sintering process is not yet completed under the mild sintering process conditions we used in this study and consequently Ag, Au and Cu continued to diffuse during temperature cycling test and high temperature storage and as a result strengthen the sintered joint. It is strongly believed that the sintering process is completed after a certain time of storage at 250°C as we observed no further increase in die shear strength after 250 h storage. The bending test results further confirm the increase of bonding strength by thermal cycling. It is worth noting that cohesive break in the Cu layer was observed for Ag metallized and bare Cu substrates after 1000 h storage at 250°C. Elemental analysis by energy dispersive X-ray spectroscopy demonstrates that interdiffusion between Ag and Cu occurred during high temperature storage in which Cu from the substrate diffused into the silver sintered layer and concurrently Ag from the silver sintered layer diffused into the substrate. In contrast, we observed cohesive break in the sintered layer after 1000 h storage at 250°C for Au metallized substrate indicating that Au metallized layer acts as a barrier to prevent Cu from the substrate from diffusion into the silver sintered layer.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"323-330"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87906578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Synthetic fused quartz is an ideal material for devices in millimeter wave (mm-wave) band, particularly suited for devices and infrastructure in the 5G arena due to its excellent low loss, ultra low roughness, and low coefficient of thermal expansion. To realize such devices utilizing synthetic fused quartz, the accurate micromachining technology specialized for the material coupled with the material technology is essential. This paper discusses the dielectric characteristics of synthetic fused quartz and the high accuracy through quartz glass via formation (TQV) technology. The metallization technology for synthetic fused quartz is also discussed, which is also a key technology to make optimum use of the material. Finally, to validate the superiority of the ultra-low loss synthetic fused quartz and high accuracy TQVs, a 28 GHz band pass filter based on substrate integrated waveguide (SIW) is demonstrated and characterized. The measurement results corroborated well with the simulated results and showed extremely high efficiency, proving that AGC's material and the TQV formation technology are extremely useful for the 5G devices.
{"title":"Demonstration of 28GHz Band Pass Filter Toward 5G Using Ultra Low Loss and High Accuracy Through Quartz Vias","authors":"Y. Sato, N. Kidera","doi":"10.1109/ECTC.2018.00337","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00337","url":null,"abstract":"Synthetic fused quartz is an ideal material for devices in millimeter wave (mm-wave) band, particularly suited for devices and infrastructure in the 5G arena due to its excellent low loss, ultra low roughness, and low coefficient of thermal expansion. To realize such devices utilizing synthetic fused quartz, the accurate micromachining technology specialized for the material coupled with the material technology is essential. This paper discusses the dielectric characteristics of synthetic fused quartz and the high accuracy through quartz glass via formation (TQV) technology. The metallization technology for synthetic fused quartz is also discussed, which is also a key technology to make optimum use of the material. Finally, to validate the superiority of the ultra-low loss synthetic fused quartz and high accuracy TQVs, a 28 GHz band pass filter based on substrate integrated waveguide (SIW) is demonstrated and characterized. The measurement results corroborated well with the simulated results and showed extremely high efficiency, proving that AGC's material and the TQV formation technology are extremely useful for the 5G devices.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"54 1","pages":"2243-2247"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86514997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhaohui Chen, B. L. Lau, Zhipeng Ding, Eva Leong Ching Wai, B. Han, L. Bu, Hyun-Kee Chang, T. Chai
A Wafer Level Chip Scale Packaging (WLCSP) solution with CuPd wire in epoxy mold compound (EMC) as through mold interconnection (TMI) was proposed for the capacitive MEMS such as accelerometer packaging. The size of fabricated WLCSP is 2 mm × 2 mm × 0.83 mm. Silicon cap was designed as 1 mm × 2 mm × 0.1 mm. Device wafer and cap wafer was bonded with wafer level Al/Ge eutectic bonding process. Vertical CuPd wire with diameter of 2 mils embedded in the EMC was used as the TMI. Dummy ASIC die with the size of 1 mm × 1 mm × 0.15 mm can be mounted on the UBM above the RDL of the WLCSP with micro-bumps. MSL1, -40 ºC to 125 ºC thermal cycling (TC), unbiased highly accelerated stress test (HAST) and 150 ºC high temperature storage (HST) testing was conducted on the fabricated dummy test vehicle samples. Testing results show that the fabricated test vehicle can pass the tests without electrical failure. The WLCSP with CuPd wire in EMC as TMI has been successfully demonstrated, which provides the confidence for the next step fabrication of WLCSP with functional accelerometer.
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