S. Cardarelli, N. Calabretta, R. Stabile, K. Williams, Xiao Luo, J. Mink
A method to relax opto-electronic packaging tolerances is proposed and demonstrated using a low-power, bimorph, piezo-electric alignment system capable of compensating the misalignment between an InP waveguide and a lensed optical fiber in a 100 µm2 misalignment range. This is expected to enable the use of relaxed tolerance pick and place tools.
{"title":"Wide-Range 2D InP Chip-to-Fiber Alignment Through Bimorph Piezoelectric Actuators","authors":"S. Cardarelli, N. Calabretta, R. Stabile, K. Williams, Xiao Luo, J. Mink","doi":"10.1109/ECTC.2018.00172","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00172","url":null,"abstract":"A method to relax opto-electronic packaging tolerances is proposed and demonstrated using a low-power, bimorph, piezo-electric alignment system capable of compensating the misalignment between an InP waveguide and a lensed optical fiber in a 100 µm2 misalignment range. This is expected to enable the use of relaxed tolerance pick and place tools.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"1124-1129"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74127206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We demonstrate the importance of vertical position accuracy of formed core in the polymer optical waveguides fabricated using the Mosquito method for 3-dimensional wiring. We theoretically confirm the core vertical position deviation from the designed position is caused by the several fabrication parameters, the needle size and the needle-scanning speed. As an example of 3-dimensional wiring, we focus on the optical path conversion by 45-degree mirrors, and experimentally investigate the influence of the core vertical position on the coupling efficiency to other components via a 45-degree mirror. By forming the cores on appropriate height in the cladding, graded-index core optical waveguides exhibit a slight loss increment as low as 0.2 dB due to mirror structure, realizing the high efficient coupling via a 45-degree mirror.
{"title":"Accurate Core Alignment for Polymer Optical Waveguide in the Mosquito Method for High-Efficient Coupling","authors":"Y. Morimoto, Kumi Date, T. Ishigure","doi":"10.1109/ECTC.2018.00368","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00368","url":null,"abstract":"We demonstrate the importance of vertical position accuracy of formed core in the polymer optical waveguides fabricated using the Mosquito method for 3-dimensional wiring. We theoretically confirm the core vertical position deviation from the designed position is caused by the several fabrication parameters, the needle size and the needle-scanning speed. As an example of 3-dimensional wiring, we focus on the optical path conversion by 45-degree mirrors, and experimentally investigate the influence of the core vertical position on the coupling efficiency to other components via a 45-degree mirror. By forming the cores on appropriate height in the cladding, graded-index core optical waveguides exhibit a slight loss increment as low as 0.2 dB due to mirror structure, realizing the high efficient coupling via a 45-degree mirror.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"PP 1","pages":"2444-2449"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84170723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Chiu, Wei-Jie Yin, En-Yu Yeh, Yu-Ting Yang, Dao-Long Chen, Y. Tseng
Epoxy molding compound (EMC) is a key constituent in large overmolded panel or wafer. During various packaging thermal processes, the thermal expansion mismatch between EMC and Si die and the shrinkage of EMC due to chemical or physical aging would lead to residual stress and warpage. For accurately predicting warpage in fan-out reconstituted wafer, the viscoelastic constitutive behavior and the physical aging characteristics were investigated. The viscoelastic behavior of the EMC were measured by quasi-static relaxation and creep experiments. Consistency of the viscoelastic behaviors measured from these two experiments were examined and compared to the viscoelastic model constructed from time-harmonic dynamic experiment. From the comparisons of these test results, it was found that the viscoelastic behavior measured by creep and relaxation tests are highly consistent, and the presence of physical aging in the dynamic test specimen delays the viscoelastic relaxation. In addition, physical aging leads to stress-free shrinkage comparable to the chemical-aging induced shrinkage. The chemical-thermomechanical constitutive model was also implemented to simulate warpage evolution of a reconstituted wafer.
{"title":"Physical Aging of Epoxy Molding Compound and Its Influences on the Warpage of Reconstituted Wafer","authors":"T. Chiu, Wei-Jie Yin, En-Yu Yeh, Yu-Ting Yang, Dao-Long Chen, Y. Tseng","doi":"10.1109/ECTC.2018.00277","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00277","url":null,"abstract":"Epoxy molding compound (EMC) is a key constituent in large overmolded panel or wafer. During various packaging thermal processes, the thermal expansion mismatch between EMC and Si die and the shrinkage of EMC due to chemical or physical aging would lead to residual stress and warpage. For accurately predicting warpage in fan-out reconstituted wafer, the viscoelastic constitutive behavior and the physical aging characteristics were investigated. The viscoelastic behavior of the EMC were measured by quasi-static relaxation and creep experiments. Consistency of the viscoelastic behaviors measured from these two experiments were examined and compared to the viscoelastic model constructed from time-harmonic dynamic experiment. From the comparisons of these test results, it was found that the viscoelastic behavior measured by creep and relaxation tests are highly consistent, and the presence of physical aging in the dynamic test specimen delays the viscoelastic relaxation. In addition, physical aging leads to stress-free shrinkage comparable to the chemical-aging induced shrinkage. The chemical-thermomechanical constitutive model was also implemented to simulate warpage evolution of a reconstituted wafer.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"68 1","pages":"1848-1855"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72705540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Over the past decade, rechargeable batteries based on lithium metal ion chemistries have enabled the practical development of many new products and technologies. Today, Li-ion batteries are often the primary means of providing electrical power to a diverse and growing number of devices, from mobile phones to electric vehicles. Despite many advances, Li-ion battery technologies suffer from some limitations that can prevent their use in emerging market sectors such as wearables, IoT, and grid-scale energy storage. While still in the research and development phase, it is anticipated that divalent metal-ion battery chemistries based on zinc or magnesium will present viable alternatives to conventional lithium-ion cells in these markets. Lithium ion batteries have a high theoretical gravimetric capacity of 3829mAh/g but only a modest volumetric capacity of 2044mAh/cm3. By comparison, divalent batteries based on zinc or magnesium ions have theoretical volumetric capacities of 5854mAh/cm3 and 3882mAh/cm3 respectively. Volumetric capacity is especially important in IoT devices and wearables, where thin, flexible batteries which can cover large areas are ideal. In addition to a somewhat low volumetric capacity, lithium is far less common in the earth's crust than magnesium or zinc and possesses higher reactivity. Because of this, lithium-ion batteries are anticipated to be less environmentally friendly and cost effective than divalent metal-ion batteries in applications requiring many large battery cells. In this proceeding, we study the components of an experimental magnesium ion half-cell constructed from solid, flexible materials. A magnesium-ion cell was chosen due to its low material cost, good theoretical volumetric capacity, simple fabrication steps, and separator-free reaction chemistry. Flexible, insertion-type anodes and cathodes were fabricated using bismuth nanotubes and tungsten disulfide respectively. A polymer-based electrolyte made of PVDF-HFP and magnesium perchlorate was chosen for its demonstrated high ionic conductivity and mechanical flexibility. Each interface of the half-cell was characterized though the use of cyclic voltammetry. Cell fabrication, component/interface electrochemistry, electrode materials and packaging, will be described in detail.
{"title":"Electrochemical Analysis of Mechanically Flexible Magnesiumion Battery Electrodes in a Polymer Gel Perchlorate Electrolyte","authors":"Todd Houghton, Hongbin Yu","doi":"10.1109/ECTC.2018.00215","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00215","url":null,"abstract":"Over the past decade, rechargeable batteries based on lithium metal ion chemistries have enabled the practical development of many new products and technologies. Today, Li-ion batteries are often the primary means of providing electrical power to a diverse and growing number of devices, from mobile phones to electric vehicles. Despite many advances, Li-ion battery technologies suffer from some limitations that can prevent their use in emerging market sectors such as wearables, IoT, and grid-scale energy storage. While still in the research and development phase, it is anticipated that divalent metal-ion battery chemistries based on zinc or magnesium will present viable alternatives to conventional lithium-ion cells in these markets. Lithium ion batteries have a high theoretical gravimetric capacity of 3829mAh/g but only a modest volumetric capacity of 2044mAh/cm3. By comparison, divalent batteries based on zinc or magnesium ions have theoretical volumetric capacities of 5854mAh/cm3 and 3882mAh/cm3 respectively. Volumetric capacity is especially important in IoT devices and wearables, where thin, flexible batteries which can cover large areas are ideal. In addition to a somewhat low volumetric capacity, lithium is far less common in the earth's crust than magnesium or zinc and possesses higher reactivity. Because of this, lithium-ion batteries are anticipated to be less environmentally friendly and cost effective than divalent metal-ion batteries in applications requiring many large battery cells. In this proceeding, we study the components of an experimental magnesium ion half-cell constructed from solid, flexible materials. A magnesium-ion cell was chosen due to its low material cost, good theoretical volumetric capacity, simple fabrication steps, and separator-free reaction chemistry. Flexible, insertion-type anodes and cathodes were fabricated using bismuth nanotubes and tungsten disulfide respectively. A polymer-based electrolyte made of PVDF-HFP and magnesium perchlorate was chosen for its demonstrated high ionic conductivity and mechanical flexibility. Each interface of the half-cell was characterized though the use of cyclic voltammetry. Cell fabrication, component/interface electrochemistry, electrode materials and packaging, will be described in detail.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"59 1","pages":"1407-1413"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80538118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masaki Kanemoto, M. Aoki, A. Mochizuki, Y. Murakami, M. Tsunoda, N. Nakano
This work clarifies the warpage and thermal stress under thermal cycling test (TCT) by 3D multi-physics solver for SiC and Si power device chip systems using direct Ag sintering chip-attachment on Cu plate. We compare the simulated warpages to the warpage results measured at room temperature for SiC/Si test structures. Measured warpages were in good agreement with our simulation values, and the simulation accuracy at Cu thickness of 1 mm was within 10 percentages for SiC structure. It was also found that the warpage in SiC structure is considerably larger than that in Si structure due to larger Young's modulus of SiC. Our simulations also showed that the warpage and displacement difference become smaller, and the thermal stress becomes stronger as the Cu plate thickness increases for both SiC/Si structures. The simulated maximum stress values under TCT decrease as Ta increases and approaches the stress free temperature. It was found that thermal stress values do not vary linearly with Ta. This nonlinearity is thought to be caused by the temperature dependence of Young's modulus of Ag sintered layer. We also clarified that the maximum stress point in the whole system is at the corner of Ag sintered bonding layer at low temperatures, and shifts to the chip center for both SiC/Si structures as Ta increases.
{"title":"Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate","authors":"Masaki Kanemoto, M. Aoki, A. Mochizuki, Y. Murakami, M. Tsunoda, N. Nakano","doi":"10.1109/ECTC.2018.00049","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00049","url":null,"abstract":"This work clarifies the warpage and thermal stress under thermal cycling test (TCT) by 3D multi-physics solver for SiC and Si power device chip systems using direct Ag sintering chip-attachment on Cu plate. We compare the simulated warpages to the warpage results measured at room temperature for SiC/Si test structures. Measured warpages were in good agreement with our simulation values, and the simulation accuracy at Cu thickness of 1 mm was within 10 percentages for SiC structure. It was also found that the warpage in SiC structure is considerably larger than that in Si structure due to larger Young's modulus of SiC. Our simulations also showed that the warpage and displacement difference become smaller, and the thermal stress becomes stronger as the Cu plate thickness increases for both SiC/Si structures. The simulated maximum stress values under TCT decrease as Ta increases and approaches the stress free temperature. It was found that thermal stress values do not vary linearly with Ta. This nonlinearity is thought to be caused by the temperature dependence of Young's modulus of Ag sintered layer. We also clarified that the maximum stress point in the whole system is at the corner of Ag sintered bonding layer at low temperatures, and shifts to the chip center for both SiC/Si structures as Ta increases.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"68 1","pages":"273-278"},"PeriodicalIF":0.0,"publicationDate":"2018-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79035989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hanmin Lee, Seyong Lee, Jongho Park, C. Chung, Kyung-Woon Jang, I. Kim, Seo-Yoon Choi, K. Paik
In this study, flip chip assembly using NCFs was evaluated in Sn-Ag solder bump structure. Thermo-Compression (TC) flip chip bonding was performed within 5 seconds using an isothermal TC bonding method. Solder joint morphology was evaluated by adjusting curing properties of NCFs such as curing onset and peak temperature and degree of curing and also viscosities, and the best NCFs properties were optimized. In addition, bonding process conditions were also optimized in terms of solder gap heights and daisy chain electrical resistances. Finally, 85°C/85RH% test and temperature cycling (T/C) reliability test were performed to evaluate the thermo-mechanical and hygroscopic reliability performance of solder joint using NCFs.
{"title":"A Study on the Curing Properties and Viscosities of Non-Conductive Films (NCFs) for Sn-Ag Solder Bump Flip Chip Assembly","authors":"Hanmin Lee, Seyong Lee, Jongho Park, C. Chung, Kyung-Woon Jang, I. Kim, Seo-Yoon Choi, K. Paik","doi":"10.1109/ECTC.2018.00371","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00371","url":null,"abstract":"In this study, flip chip assembly using NCFs was evaluated in Sn-Ag solder bump structure. Thermo-Compression (TC) flip chip bonding was performed within 5 seconds using an isothermal TC bonding method. Solder joint morphology was evaluated by adjusting curing properties of NCFs such as curing onset and peak temperature and degree of curing and also viscosities, and the best NCFs properties were optimized. In addition, bonding process conditions were also optimized in terms of solder gap heights and daisy chain electrical resistances. Finally, 85°C/85RH% test and temperature cycling (T/C) reliability test were performed to evaluate the thermo-mechanical and hygroscopic reliability performance of solder joint using NCFs.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"2464-2469"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89042065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Hanna, A. Alam, T. Fukushima, S. Moran, William Whitehead, SivaChandra Jangam, Saptadeep Pal, G. Ezhilarasu, R. Irwin, A. Bajwa, S. Iyer
A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble >600 dies with co-planarity and tilt <1µm, average die-shift of 3.28 µm with ? < 2.23 µm. We have also engineered a novel corrugated topography of a stress buffer layer for metal interconnects on FlexTrateTM to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then tested for their mechanical bending reliability and have shown less than 0.4% change in resistance after bending at 1 mm radius for 1,000 cycles. Finally, we demonstrate integration of an array of 25 dielets interconnected in a daisy chain configuration at 40 µm interconnect pitch.
{"title":"Extremely Flexible (1mm Bending Radius) Biocompatible Heterogeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (<6 µm) and Reliable Flexible Cu-Based Interconnects","authors":"A. Hanna, A. Alam, T. Fukushima, S. Moran, William Whitehead, SivaChandra Jangam, Saptadeep Pal, G. Ezhilarasu, R. Irwin, A. Bajwa, S. Iyer","doi":"10.1109/ECTC.2018.00229","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00229","url":null,"abstract":"A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble >600 dies with co-planarity and tilt <1µm, average die-shift of 3.28 µm with ? < 2.23 µm. We have also engineered a novel corrugated topography of a stress buffer layer for metal interconnects on FlexTrateTM to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then tested for their mechanical bending reliability and have shown less than 0.4% change in resistance after bending at 1 mm radius for 1,000 cycles. Finally, we demonstrate integration of an array of 25 dielets interconnected in a daisy chain configuration at 40 µm interconnect pitch.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1505-1511"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90658059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For several decades, non-conductive pastes (NCPs) have been widely used for the mass production of ultrasound transducers assembly using piezoelectric ceramics and FPCs. The NCPs interconnection is established through direct metal to metal contact. In more details, the surface of piezoelectric ceramics is roughly grinded to make point contacts before metallization. And the NCPs are filled in non-contacted area between metallized piezoelectric ceramics and metal electrodes of FPCs. However, the point contacts result in higher electrical resistance. Also, the electrical conduction and the reliability of NCP interconnection can be deteriorated especially in moisture and at high temperature environment due to the polymer expansion. In addition, the piezoelectric ceramics such as PZT cannot maintain the polarization above its Curie temperature. Therefore, the curing temperature should be below 150°C. Therefore, longer curing times at 150°C are required for NCPs to avoid the depolarization of piezoelectric ceramics. Furthermore, sometimes surface grinding of piezoelectric ceramics may produce cracks which lead to the reduction of production yield. Therefore, it is desirable for lowering the electrical resistances, increasing the reliability and shorter curing time without grinding process. As a result, low temperature anisotropic conductive films (ACFs), which consist of adhesive polymer resin and conductive particles, were introduced in order to increase the electrical conduction and reliability without grinding process. In this study, various ACFs, including 3 types of conductive particles (Sn58Bi solder, Au/Ni coated polymer and Ni balls) and 3 types of thermosetting polymer resins (cationic epoxy, imidazole epoxy and acrylic resins), were investigated with respect to mechanical/electrical properties and reliability. In order to lower the ACFs bonding temperature below 150°C, low melting temperature eutectic Sn58Bi solder particles with the melting point of 138°C was used. For the thermo-compression bonding, the piezoelectric ceramics were placed at the bottom and flexible printed circuits boards (FPCBs) were placed on the top of piezoelectric ceramics to guarantee the real temperature of the piezoelectric ceramics below 150°C. As a result, piezoelectric ceramics and metal electrodes interconnection was successfully performed below 150°C with stable contact resistance and solder joint formation even after reliability test and the dicing process. After dicing into FPCBs, no short circuit was found between neighboring electrodes. And ACFs with Sn58Bi solder particles and cationic epoxy resin showed the lowest electrical resistance after bonding, excellent mechanical and electrical performance among various ACFs.
{"title":"Piezoelectric Ceramics and Flexible Printed Circuits (FPCs) Interconnection Using Anisotropic Conductive Films (ACFs) for Ultrasound Transducers Assembly","authors":"Jae-Hyeong Park, K. Paik","doi":"10.1109/ECTC.2018.00374","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00374","url":null,"abstract":"For several decades, non-conductive pastes (NCPs) have been widely used for the mass production of ultrasound transducers assembly using piezoelectric ceramics and FPCs. The NCPs interconnection is established through direct metal to metal contact. In more details, the surface of piezoelectric ceramics is roughly grinded to make point contacts before metallization. And the NCPs are filled in non-contacted area between metallized piezoelectric ceramics and metal electrodes of FPCs. However, the point contacts result in higher electrical resistance. Also, the electrical conduction and the reliability of NCP interconnection can be deteriorated especially in moisture and at high temperature environment due to the polymer expansion. In addition, the piezoelectric ceramics such as PZT cannot maintain the polarization above its Curie temperature. Therefore, the curing temperature should be below 150°C. Therefore, longer curing times at 150°C are required for NCPs to avoid the depolarization of piezoelectric ceramics. Furthermore, sometimes surface grinding of piezoelectric ceramics may produce cracks which lead to the reduction of production yield. Therefore, it is desirable for lowering the electrical resistances, increasing the reliability and shorter curing time without grinding process. As a result, low temperature anisotropic conductive films (ACFs), which consist of adhesive polymer resin and conductive particles, were introduced in order to increase the electrical conduction and reliability without grinding process. In this study, various ACFs, including 3 types of conductive particles (Sn58Bi solder, Au/Ni coated polymer and Ni balls) and 3 types of thermosetting polymer resins (cationic epoxy, imidazole epoxy and acrylic resins), were investigated with respect to mechanical/electrical properties and reliability. In order to lower the ACFs bonding temperature below 150°C, low melting temperature eutectic Sn58Bi solder particles with the melting point of 138°C was used. For the thermo-compression bonding, the piezoelectric ceramics were placed at the bottom and flexible printed circuits boards (FPCBs) were placed on the top of piezoelectric ceramics to guarantee the real temperature of the piezoelectric ceramics below 150°C. As a result, piezoelectric ceramics and metal electrodes interconnection was successfully performed below 150°C with stable contact resistance and solder joint formation even after reliability test and the dicing process. After dicing into FPCBs, no short circuit was found between neighboring electrodes. And ACFs with Sn58Bi solder particles and cationic epoxy resin showed the lowest electrical resistance after bonding, excellent mechanical and electrical performance among various ACFs.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"13 1","pages":"2484-2491"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78989203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SivaChandra Jangam, A. Bajwa, Kannan K Thankkappan, Premsagar Kittur, S. Iyer
The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous integration of dielets using a fine interconnect pitch (? 10 µm) and small inter-dielet spacing (? 100 µm) [1]. In our fine-pitch integration scheme, short links on Si-IF (? 500 µm) are used for inter-dielet communication, reducing the latency (? 35 ps) and energy /bit (? 0.04 pJ/b) [2]. In this paper, we demonstrate the excellent transfer characteristics of the Si-IF links, verified experimentally. The measured insertion loss in these short Si-IF links (? 500 µm) is ? 2 dB for frequencies up to 30 GHz. Further, the transfer characteristics show only a single pole, demonstrating an RC-link behavior. We show that assemblies on Si-IF have 16-25X lower parasitic inductance, and 6-40X lower parasitic capacitance compared to assemblies on interposers and PCBs. We illustrate that using the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol [2] for data transfer, data rates of ? 10 Gbps/link are realizable at an energy/bit of ? 0.04 pJ/b. Subsequently, due to the high interconnect density, the overall bandwidth/mm is ? 8 Tbps/mm. This corresponds to an improvement of 120-300X in bandwidth/mm and a reduction of 100-500X in energy/bit compared to a conventional PCB-based integration.
{"title":"Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric","authors":"SivaChandra Jangam, A. Bajwa, Kannan K Thankkappan, Premsagar Kittur, S. Iyer","doi":"10.1109/ECTC.2018.00197","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00197","url":null,"abstract":"The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous integration of dielets using a fine interconnect pitch (? 10 µm) and small inter-dielet spacing (? 100 µm) [1]. In our fine-pitch integration scheme, short links on Si-IF (? 500 µm) are used for inter-dielet communication, reducing the latency (? 35 ps) and energy /bit (? 0.04 pJ/b) [2]. In this paper, we demonstrate the excellent transfer characteristics of the Si-IF links, verified experimentally. The measured insertion loss in these short Si-IF links (? 500 µm) is ? 2 dB for frequencies up to 30 GHz. Further, the transfer characteristics show only a single pole, demonstrating an RC-link behavior. We show that assemblies on Si-IF have 16-25X lower parasitic inductance, and 6-40X lower parasitic capacitance compared to assemblies on interposers and PCBs. We illustrate that using the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol [2] for data transfer, data rates of ? 10 Gbps/link are realizable at an energy/bit of ? 0.04 pJ/b. Subsequently, due to the high interconnect density, the overall bandwidth/mm is ? 8 Tbps/mm. This corresponds to an improvement of 120-300X in bandwidth/mm and a reduction of 100-500X in energy/bit compared to a conventional PCB-based integration.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1283-1288"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84514886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bajwa, SivaChandra Jangam, Saptadeep Pal, Boris Vaisband, R. Irwin, M. Goorsky, S. Iyer
This paper describes the integration of a System-on-Wafer (SoW) assembly using test dielets mounted on a Silicon Interconnect Fabric (Si-IF) with an inter-dielet spacing of 100 µm and using 10 µm interconnect pitch. The continuity within and across the dielet assembly is shown using daisy chains of Au-capped Cu-Cu thermal compression bonds. The daisy chains run not only through every dielet but also across all the adjacently mounted dielets on the Si-IF. The interconnections exhibited an effective contact resistivity of 0.8-0.9 ?-µm2 and an average shear strength of 125 MPa. Our investigations showed that Argon plasma pre-treatment improves the shear strength of the metal bonds by a factor of 5X. Thermal simulation of the SoW assembly showed superior heat spreading across the assembly in a checkerboard configuration of alternate hot (0.5 W/mm2) and cold (0.1 W/mm2) dielets with an average temperature of 82 °C & 78 °C respectively.
{"title":"Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) Assembly","authors":"A. Bajwa, SivaChandra Jangam, Saptadeep Pal, Boris Vaisband, R. Irwin, M. Goorsky, S. Iyer","doi":"10.1109/ECTC.2018.00288","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00288","url":null,"abstract":"This paper describes the integration of a System-on-Wafer (SoW) assembly using test dielets mounted on a Silicon Interconnect Fabric (Si-IF) with an inter-dielet spacing of 100 µm and using 10 µm interconnect pitch. The continuity within and across the dielet assembly is shown using daisy chains of Au-capped Cu-Cu thermal compression bonds. The daisy chains run not only through every dielet but also across all the adjacently mounted dielets on the Si-IF. The interconnections exhibited an effective contact resistivity of 0.8-0.9 ?-µm2 and an average shear strength of 125 MPa. Our investigations showed that Argon plasma pre-treatment improves the shear strength of the metal bonds by a factor of 5X. Thermal simulation of the SoW assembly showed superior heat spreading across the assembly in a checkerboard configuration of alternate hot (0.5 W/mm2) and cold (0.1 W/mm2) dielets with an average temperature of 82 °C & 78 °C respectively.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"262 1","pages":"1926-1930"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85864007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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