B. Song, Fan Wu, K. Moon, R. Bahr, M. Tentzeris, C. Wong
The rapid growth of wearable electronics has driven the demand for new material solution in electronic packaging. Highly stretchable and electrically conductive composites can be of great use as stretchable conductors in wearable devices. Recently, the reduction in package size and increase in device functionalities have posed more stringent yet challenging requirements for stretchable conductors, including the capability to provide distinctive electrical signals under strains, perform exceptional reliability, and show compatibility with printing technologies to make high resolution patterns. In this work, we have developed a novel conductive composite consisting of a modified elastomer and silver nanostructures that combines high stretchability, conductivity, and printability with fine feature sizes. The formulated composites have been applied in smart wearable bands for Internet of Things (IoT) applications.
{"title":"Stretchable, Printable and Electrically Conductive Composites for Wearable RF Antennas","authors":"B. Song, Fan Wu, K. Moon, R. Bahr, M. Tentzeris, C. Wong","doi":"10.1109/ECTC.2018.00009","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00009","url":null,"abstract":"The rapid growth of wearable electronics has driven the demand for new material solution in electronic packaging. Highly stretchable and electrically conductive composites can be of great use as stretchable conductors in wearable devices. Recently, the reduction in package size and increase in device functionalities have posed more stringent yet challenging requirements for stretchable conductors, including the capability to provide distinctive electrical signals under strains, perform exceptional reliability, and show compatibility with printing technologies to make high resolution patterns. In this work, we have developed a novel conductive composite consisting of a modified elastomer and silver nanostructures that combines high stretchability, conductivity, and printability with fine feature sizes. The formulated composites have been applied in smart wearable bands for Internet of Things (IoT) applications.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"62 1","pages":"9-14"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83828119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ziyin Lin, V. Subramanian, P. Malatkar, N. Ananthakrishnan
Harsh advanced driver assistance systems (ADAS) user conditions lead to stringent reliability requirements for electronic packages. In order to develop packages that meet ADAS reliability target, it is necessary to not only have highly reliable packaging materials but also create quick turn monitor (QTM) materials screening processes to facilitate the development cycle. In this paper, we used underfill as an example to demonstrate that material degradation in reliability testing conditions is an important modulator for underfill performance. It was found that one of underfill materials in our study experienced significant fracture toughness degradation after temperature cycling or high temperature bake; and the toughness degradation explained the poor package level reliability performance. The root cause of fracture toughness degradation is found to be the thermal degradation of polymer resin in reliability conditions. Further fundamental study revealed that fracture toughness/thermal degradation could be attributed to the thermal stability of the raw material structures. It is demonstrated that the characterization of the properties of packaging materials post temperature cycling/high temperature bake can be used as a QTM for material screening. The QTM offers more than three times improvement in data turns and allows for faster materials screening without the need for extensive package level experiments.
{"title":"Understanding Underfill Degradation in Reliability Testing Conditions for ADAS Package Development","authors":"Ziyin Lin, V. Subramanian, P. Malatkar, N. Ananthakrishnan","doi":"10.1109/ECTC.2018.00032","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00032","url":null,"abstract":"Harsh advanced driver assistance systems (ADAS) user conditions lead to stringent reliability requirements for electronic packages. In order to develop packages that meet ADAS reliability target, it is necessary to not only have highly reliable packaging materials but also create quick turn monitor (QTM) materials screening processes to facilitate the development cycle. In this paper, we used underfill as an example to demonstrate that material degradation in reliability testing conditions is an important modulator for underfill performance. It was found that one of underfill materials in our study experienced significant fracture toughness degradation after temperature cycling or high temperature bake; and the toughness degradation explained the poor package level reliability performance. The root cause of fracture toughness degradation is found to be the thermal degradation of polymer resin in reliability conditions. Further fundamental study revealed that fracture toughness/thermal degradation could be attributed to the thermal stability of the raw material structures. It is demonstrated that the characterization of the properties of packaging materials post temperature cycling/high temperature bake can be used as a QTM for material screening. The QTM offers more than three times improvement in data turns and allows for faster materials screening without the need for extensive package level experiments.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"56 1","pages":"157-161"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79653281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wire bonding is popular first-level interconnect method used in the semiconductor device packaging. Gold (Ag) wire is often used in high-reliability applications. Typical wire diameters vary between 0.8mil to 2mil. Recent increases in the gold-price have motivated the industry to search for alternate materials candidates for use in wirebonding. Three of the leading candidates are Silver (Ag), Copper (Cu), and Palladium Coated Copper (PCC). The new material candidates are inexpensive in comparison with gold and may have better electrical, and thermal properties, which is advantageous for fine pitch-high density electronics. The transition, however, comes along with few trade-offs such as narrow process window, higher wire-hardness, increased propensity for chip-cratering, lack of reliability knowledge base of when deployed in harsh environment applications. Relationship between mechanical degradation of the wirebond and the change in electric response needs to be established for better understanding of the failure modes and their respective mechanisms. Understanding the physics of damage progression may provide insights into the process parameters for manufacture of more robust interconnects. In this paper, a detailed study of the electrical and mechanical degradation of wirebonds under high temperature exposure is presented. Four wirebond candidates (Au, Ag, Cu and PCC) bonded onto Aluminum (Al) pad were subjected to high temperature storage life until failure to study the degradation of the bond-wire interface. Same package architecture and electronic molding compound (EMC) were used for all four candidates. Detailed analysis of intermetallic (IMC) phase evolution is presented along with quantification of the phases and their evolution over time. Ball shear strength was measured after decapsulation. Measurements of shear strength, shear failure modes, and IMC composition have been correlated with the change in the electrical response. Change in shear strength and different shear failure modes for different wirebond systems are discussed in the paper.
{"title":"Reliability of Copper, Gold, Silver, and PCC Wirebonds Subjected to Harsh Environment","authors":"P. Lall, Shantanu Deshpande, L. Nguyen","doi":"10.1109/ECTC.2018.00113","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00113","url":null,"abstract":"Wire bonding is popular first-level interconnect method used in the semiconductor device packaging. Gold (Ag) wire is often used in high-reliability applications. Typical wire diameters vary between 0.8mil to 2mil. Recent increases in the gold-price have motivated the industry to search for alternate materials candidates for use in wirebonding. Three of the leading candidates are Silver (Ag), Copper (Cu), and Palladium Coated Copper (PCC). The new material candidates are inexpensive in comparison with gold and may have better electrical, and thermal properties, which is advantageous for fine pitch-high density electronics. The transition, however, comes along with few trade-offs such as narrow process window, higher wire-hardness, increased propensity for chip-cratering, lack of reliability knowledge base of when deployed in harsh environment applications. Relationship between mechanical degradation of the wirebond and the change in electric response needs to be established for better understanding of the failure modes and their respective mechanisms. Understanding the physics of damage progression may provide insights into the process parameters for manufacture of more robust interconnects. In this paper, a detailed study of the electrical and mechanical degradation of wirebonds under high temperature exposure is presented. Four wirebond candidates (Au, Ag, Cu and PCC) bonded onto Aluminum (Al) pad were subjected to high temperature storage life until failure to study the degradation of the bond-wire interface. Same package architecture and electronic molding compound (EMC) were used for all four candidates. Detailed analysis of intermetallic (IMC) phase evolution is presented along with quantification of the phases and their evolution over time. Ball shear strength was measured after decapsulation. Measurements of shear strength, shear failure modes, and IMC composition have been correlated with the change in the electrical response. Change in shear strength and different shear failure modes for different wirebond systems are discussed in the paper.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"401 1","pages":"724-734"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79675330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Dikhaminjia, J. He, H. Deng, M. Tsiklauri, J. Drewniak, A. Chada, B. Mutnury
The signal in channels with high-speed designs is attenuated by channel loss, inter-symbol interference, jitter, noise and crosstalk. The main way to recover the signal is by using equalizations, such as Feed-Forward Equalizer, Continuous Time-Linear Equalizer and Decision Feedback Equalizer. One of the important problems of high-speed design and channel simulations is to develop fast optimization algorithms for choosing best tap coefficients for equalizers. Equalization of multi-level signal is more complicated and optimization algorithms require specific approach. The paper proposes a new efficient optimization of Decision Feedback Equalization (DFE) for binary and multi-level signals. Mathematical formulation of the optimization is given. Simulations were conducted for channels with different characteristics and comparison results are shown.
{"title":"Effect of Improved Optimization of DFE Equalization on Crosstalk and Jitter in High Speed Links with Multi-level Signal","authors":"N. Dikhaminjia, J. He, H. Deng, M. Tsiklauri, J. Drewniak, A. Chada, B. Mutnury","doi":"10.1109/ECTC.2018.00315","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00315","url":null,"abstract":"The signal in channels with high-speed designs is attenuated by channel loss, inter-symbol interference, jitter, noise and crosstalk. The main way to recover the signal is by using equalizations, such as Feed-Forward Equalizer, Continuous Time-Linear Equalizer and Decision Feedback Equalizer. One of the important problems of high-speed design and channel simulations is to develop fast optimization algorithms for choosing best tap coefficients for equalizers. Equalization of multi-level signal is more complicated and optimization algorithms require specific approach. The paper proposes a new efficient optimization of Decision Feedback Equalization (DFE) for binary and multi-level signals. Mathematical formulation of the optimization is given. Simulations were conducted for channels with different characteristics and comparison results are shown.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"2101-2106"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83389377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vadim Heyfitch, Shen Dong, N. Na, Hong Shi, Jaspreet Gandhi, Jane Xi, Susan Wu
Several designs of High-Bandwidth Memory (HBM) interface have been reported so far, all on silicon interposer. With the promise of organic interposer to become a lower-cost alternative, complete understanding of electrical performance of such interface is required. HBM interface connects SoC (System on Chip) and HBM dies that are placed next to each other on a common substrate; therefore, it is only a few millimeters long. With all eight channels routed, it counts close to 1700 signals that run on three layers, as limited by today's process technology. As the HBM die and, subsequently, the interface width is only 6 millimeters, these signals have to be routed with very high density. This results in high crosstalk. Specific to the organic interface, the short HMB signal lines, in combination with the driver complex-valued output impedance and the capacitive input of the receiver, creates under-dampened LC(R) tank resonators circuit with natural frequency of oscillation around 3-4 GHz. Even a weak crosstalk excitation from an adjacent aggressor signals causes a quiet victim signal to undergo resonant oscillation, or ringing. The coupling between adjacent signals even within the breakout area is severe enough to reduce noise margins to zero. The resistive loss in signal traces must be sufficient to dampen this ringing. We consider various technology options to increase the loss and compare their relative efficacy. Two distinct types of crosstalk are identified and their respective effect on HBM2 timing and noise margin is discussed. Effects of the meshed (a.k.a. perforated) reference plane on intra -and interlayer crosstalk is studied. With the trace cross-sectional dimensions at 2x2um and Nyquist frequency of 1GHz, the signals operate at the onset of skin effect, with per-unit-length resistance and inductance undergoing severe dispersion. This differs from signals routed as wider traces on an organic package, where the skin effect develops at much lower frequencies. It is also in sharp contrast to on-die signal routing, where RC is an adequate model of the signal interconnect.
{"title":"High Bandwidth Memory Interface on Organic Substrate: Challenges to Electrical Design","authors":"Vadim Heyfitch, Shen Dong, N. Na, Hong Shi, Jaspreet Gandhi, Jane Xi, Susan Wu","doi":"10.1109/ECTC.2018.00198","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00198","url":null,"abstract":"Several designs of High-Bandwidth Memory (HBM) interface have been reported so far, all on silicon interposer. With the promise of organic interposer to become a lower-cost alternative, complete understanding of electrical performance of such interface is required. HBM interface connects SoC (System on Chip) and HBM dies that are placed next to each other on a common substrate; therefore, it is only a few millimeters long. With all eight channels routed, it counts close to 1700 signals that run on three layers, as limited by today's process technology. As the HBM die and, subsequently, the interface width is only 6 millimeters, these signals have to be routed with very high density. This results in high crosstalk. Specific to the organic interface, the short HMB signal lines, in combination with the driver complex-valued output impedance and the capacitive input of the receiver, creates under-dampened LC(R) tank resonators circuit with natural frequency of oscillation around 3-4 GHz. Even a weak crosstalk excitation from an adjacent aggressor signals causes a quiet victim signal to undergo resonant oscillation, or ringing. The coupling between adjacent signals even within the breakout area is severe enough to reduce noise margins to zero. The resistive loss in signal traces must be sufficient to dampen this ringing. We consider various technology options to increase the loss and compare their relative efficacy. Two distinct types of crosstalk are identified and their respective effect on HBM2 timing and noise margin is discussed. Effects of the meshed (a.k.a. perforated) reference plane on intra -and interlayer crosstalk is studied. With the trace cross-sectional dimensions at 2x2um and Nyquist frequency of 1GHz, the signals operate at the onset of skin effect, with per-unit-length resistance and inductance undergoing severe dispersion. This differs from signals routed as wider traces on an organic package, where the skin effect develops at much lower frequencies. It is also in sharp contrast to on-die signal routing, where RC is an adequate model of the signal interconnect.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"9 1","pages":"1289-1294"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88623298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, an investigation was carried out on how to improve bonding of electroless copper (Cu) to electroplated Cu by optimizing the activation process. First, interfacial structure between via and land pad was analyzed to identify the normal and abnormal features. Carbon inclusion was determined as an anomaly of Pd seed layer. Second, an experiment was performed to characterize the impact of activation dipping time and rinse time on the formation of carbon inclusions. A procedure was developed to quantitatively evaluate carbon inclusions in the via interface. It was found that, as expected, combination of shorter dipping time and longer rinse time resulted in fewer carbon inclusions in the Pd seed layer. Finally, based on the mechanism of Cu-Cu bonding and data from the experimental study, the quantity of carbon inclusions and the coverage of carbon on the interface are proposed for monitoring the quality of via/pad interface.
{"title":"Improve Interconnect Reliability of BGA Substrate with Stacked Vias by Reducing Carbon Inclusion in the Interface Between Via and Land Pad","authors":"K. Zeng, J. Williamson","doi":"10.1109/ECTC.2018.00031","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00031","url":null,"abstract":"In this paper, an investigation was carried out on how to improve bonding of electroless copper (Cu) to electroplated Cu by optimizing the activation process. First, interfacial structure between via and land pad was analyzed to identify the normal and abnormal features. Carbon inclusion was determined as an anomaly of Pd seed layer. Second, an experiment was performed to characterize the impact of activation dipping time and rinse time on the formation of carbon inclusions. A procedure was developed to quantitatively evaluate carbon inclusions in the via interface. It was found that, as expected, combination of shorter dipping time and longer rinse time resulted in fewer carbon inclusions in the Pd seed layer. Finally, based on the mechanism of Cu-Cu bonding and data from the experimental study, the quantity of carbon inclusions and the coverage of carbon on the interface are proposed for monitoring the quality of via/pad interface.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"150-156"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87347908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nieweglowski, Patrick Seiler, D. Fritsche, Sebastian Lüngen, D. Plettemeier, C. Carta, F. Ellinger, K. Bock
In this work, a polyimide (PI) foil-based wireless transceiver, which can be placed on the top of each node chip stack, is proposed. The transceivers with Butler matrix (BM) steered antenna arrays enable directed links from each node on one PCB towards any other node on the neighboring board in the rack. These passive components can be integrated into the foil whereas the active components (mm-wave ICs – MMICs) fabricated in SiGe-technology have to be connected with low parasitic, matched (wave impedance) interconnects. First the development of fabrication of low-loss transmission line structures on PI-foils will be described. The technology is based on foils with 50µm PI-thickness with Cr/Cu seed metallization and galvanic thickened Au layer. This allows for precise definition of coplanar transmission lines with low roughness (RMS roughness of 20-530nm). The measurements of characteristic parameters show good agreement with simulated data – the deviation of parasitic components (L and C) is below than 10%. A transmission loss of about 0.5 dB/cm at 60 GHz and about 1 dB/cm at 200 GHz has been measured. These substrates have been used for flip-chip assembly of chip components in order to characterize the performance of FC-interconnect at frequencies up to 220 GHz. For this analysis test-chips with transmission lines fabricated in a 130 nm SiGe-BiCMOS technology have been used. In order to mount these chips with Al pad finish on the PI-foil substrates Au studbumps with reduced size (50µm diameter on foot and 30µm height) and thermosonic flip-chip bonding have been used. From the measurements of FC bonded test chips with µ-strip lines on the PI-foils a FC-interconnect loss of about 0.28 ± 0.05 dB per bump at 60 GHz and of about 0.73 ± 0.14 dB per bump at 200 GHz could be derived.
{"title":"Interconnect Technology Development for 180GHz Wireless mm-Wave System-in-Foil Transceivers","authors":"K. Nieweglowski, Patrick Seiler, D. Fritsche, Sebastian Lüngen, D. Plettemeier, C. Carta, F. Ellinger, K. Bock","doi":"10.1109/ECTC.2018.00083","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00083","url":null,"abstract":"In this work, a polyimide (PI) foil-based wireless transceiver, which can be placed on the top of each node chip stack, is proposed. The transceivers with Butler matrix (BM) steered antenna arrays enable directed links from each node on one PCB towards any other node on the neighboring board in the rack. These passive components can be integrated into the foil whereas the active components (mm-wave ICs – MMICs) fabricated in SiGe-technology have to be connected with low parasitic, matched (wave impedance) interconnects. First the development of fabrication of low-loss transmission line structures on PI-foils will be described. The technology is based on foils with 50µm PI-thickness with Cr/Cu seed metallization and galvanic thickened Au layer. This allows for precise definition of coplanar transmission lines with low roughness (RMS roughness of 20-530nm). The measurements of characteristic parameters show good agreement with simulated data – the deviation of parasitic components (L and C) is below than 10%. A transmission loss of about 0.5 dB/cm at 60 GHz and about 1 dB/cm at 200 GHz has been measured. These substrates have been used for flip-chip assembly of chip components in order to characterize the performance of FC-interconnect at frequencies up to 220 GHz. For this analysis test-chips with transmission lines fabricated in a 130 nm SiGe-BiCMOS technology have been used. In order to mount these chips with Al pad finish on the PI-foil substrates Au studbumps with reduced size (50µm diameter on foot and 30µm height) and thermosonic flip-chip bonding have been used. From the measurements of FC bonded test chips with µ-strip lines on the PI-foils a FC-interconnect loss of about 0.28 ± 0.05 dB per bump at 60 GHz and of about 0.73 ± 0.14 dB per bump at 200 GHz could be derived.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"527-532"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87376179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Paré-Olivier, S. Ayotte, F. Costin, A. Babin, M. Morin, B. Filion, K. Bedard, Bilodeau Ghislain, É. Girard-Deschênes, P. Chrétien, Louis-Philippe Perron, Charles-André Davidson, D. D'amato, M. Laplante, J. Blanchet-Létourneau
A compact three-laser source for optical sensing is presented. It is based on a low-noise implementation of the Pound-Drever-Hall method and comprises high-bandwidth optical phase-locked loops. The outputs from three semiconductor distributed feedback lasers, mounted on thermo-electric coolers (TEC), are coupled with micro-lenses into a silicon photonics (SiP) chip that performs beat note detection and several other functions. The chip comprises phase modulators, variable optical attenuators, multi-mode-interference couplers, variable ratio tap couplers, integrated photodiodes and optical fiber butt-couplers. Electrical connections between a metallized ceramic and the TECs, lasers and SiP chip are achieved by wirebonds. All these components stand within a 35 mm by 35 mm package which is interfaced with 90 electrical pins and two fiber pigtails. One pigtail carries the signals from a master and slave lasers, while another carries that from a second slave laser. The pins are soldered to a printed circuit board featuring a micro-processor that controls and monitors the system to ensure stable operation over fluctuating environmental conditions. This highly adaptable multi-laser source can address various sensing applications requiring the tracking of up to three narrow spectral features with a high bandwidth. It is used to sense a fiber-based ring resonator emulating a resonant fiber optics gyroscope. The master laser is locked to the resonator with a loop bandwidth greater than 1 MHz. The slave lasers are offset frequency locked to the master laser with loop bandwidths greater than 100 MHz. This high performance source is compact, automated, robust, and remains locked for days.
{"title":"Integrated Multi-wavelength Laser Source for Sensing","authors":"G. Paré-Olivier, S. Ayotte, F. Costin, A. Babin, M. Morin, B. Filion, K. Bedard, Bilodeau Ghislain, É. Girard-Deschênes, P. Chrétien, Louis-Philippe Perron, Charles-André Davidson, D. D'amato, M. Laplante, J. Blanchet-Létourneau","doi":"10.1109/ECTC.2018.00133","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00133","url":null,"abstract":"A compact three-laser source for optical sensing is presented. It is based on a low-noise implementation of the Pound-Drever-Hall method and comprises high-bandwidth optical phase-locked loops. The outputs from three semiconductor distributed feedback lasers, mounted on thermo-electric coolers (TEC), are coupled with micro-lenses into a silicon photonics (SiP) chip that performs beat note detection and several other functions. The chip comprises phase modulators, variable optical attenuators, multi-mode-interference couplers, variable ratio tap couplers, integrated photodiodes and optical fiber butt-couplers. Electrical connections between a metallized ceramic and the TECs, lasers and SiP chip are achieved by wirebonds. All these components stand within a 35 mm by 35 mm package which is interfaced with 90 electrical pins and two fiber pigtails. One pigtail carries the signals from a master and slave lasers, while another carries that from a second slave laser. The pins are soldered to a printed circuit board featuring a micro-processor that controls and monitors the system to ensure stable operation over fluctuating environmental conditions. This highly adaptable multi-laser source can address various sensing applications requiring the tracking of up to three narrow spectral features with a high bandwidth. It is used to sense a fiber-based ring resonator emulating a resonant fiber optics gyroscope. The master laser is locked to the resonator with a loop bandwidth greater than 1 MHz. The slave lasers are offset frequency locked to the master laser with loop bandwidths greater than 100 MHz. This high performance source is compact, automated, robust, and remains locked for days.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"4012 2 1","pages":"859-864"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86701009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fengze Hou, Xueping Guo, Qidong Wang, Wenbo Wang, Tingyu Lin, Liqiang Cao, G. Zhang, J. Ferreira
In this paper, a high power-density 3D integrated synchronous buck converter with dual side cooling structure was designed and analyzed. A novel panel-level PCB embedded package technology for MOSFETs and planar LTCC inductor of the converter was proposed to address parasitic elements, heat dissipation, and reliability issues inherent with aluminum wires used in conventional wire-bonded package. The MOSFETs and LTCC inductor were embedded in the PCB, respectively, interconnected by RDL and PCB vias. Copper-clad BT laminate and BT prepreg with low CTE and high Tg were selected and characterized by TMA. Analysis showed that the selective PCB embedding materials were very ideal for MOSFETs and LTCC inductor packaging. Thermal simulation of the 3D module was performed using ANSYS ICEPAK. To improve accuracy and efficiency of the thermal simulation, equivalent thermal conductivity of a PCB via unit was extracted and equivalent model was built. Effects of PCB vias and heat spreader on the thermal performance of the 3D converter were analyzed. The study showed that PCB vias can improve the thermal performance of the 3D module with cap heat spreader. The highest junction temperature of the optimized 3D converter was limited to about 71.2 °C.
{"title":"High Power-Density 3D Integrated Power Supply Module Based on Panel-Level PCB Embedded Technology","authors":"Fengze Hou, Xueping Guo, Qidong Wang, Wenbo Wang, Tingyu Lin, Liqiang Cao, G. Zhang, J. Ferreira","doi":"10.1109/ECTC.2018.00208","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00208","url":null,"abstract":"In this paper, a high power-density 3D integrated synchronous buck converter with dual side cooling structure was designed and analyzed. A novel panel-level PCB embedded package technology for MOSFETs and planar LTCC inductor of the converter was proposed to address parasitic elements, heat dissipation, and reliability issues inherent with aluminum wires used in conventional wire-bonded package. The MOSFETs and LTCC inductor were embedded in the PCB, respectively, interconnected by RDL and PCB vias. Copper-clad BT laminate and BT prepreg with low CTE and high Tg were selected and characterized by TMA. Analysis showed that the selective PCB embedding materials were very ideal for MOSFETs and LTCC inductor packaging. Thermal simulation of the 3D module was performed using ANSYS ICEPAK. To improve accuracy and efficiency of the thermal simulation, equivalent thermal conductivity of a PCB via unit was extracted and equivalent model was built. Effects of PCB vias and heat spreader on the thermal performance of the 3D converter were analyzed. The study showed that PCB vias can improve the thermal performance of the 3D module with cap heat spreader. The highest junction temperature of the optimized 3D converter was limited to about 71.2 °C.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"42 1","pages":"1365-1370"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85275935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Hsu, Jackson Lin, Shuo-Mao Chen, P. Lin, Jerry Fang, Jin-Hua Wang, S. Jeng
Heterogeneous integration with advanced packaging has recently been the subject of intensive discussion and development to pursue optimum electronic system performance. The concept of miniaturized systems is particularly important for applications such as wearable and portable devices, as demands for more integrated functionality, better performance and smaller form factors persist. In this paper, we reveal a new multilayer 3D fan-out stacking integration approach and an ultra-thin 6-layer stacked fan-out package with low warpage. Compared to typical 3D IC stacking with TSV, the new structure exhibits both vertical and lateral integration flexibility. This new 3D fan-out stacking scheme inherits the thermal dissipation benefits from fanout packages with reduced thermal cross-talk and therefore offers a powerful solution for highly heterogeneous and complex systems.
{"title":"3D Heterogeneous Integration with Multiple Stacking Fan-Out Package","authors":"F. Hsu, Jackson Lin, Shuo-Mao Chen, P. Lin, Jerry Fang, Jin-Hua Wang, S. Jeng","doi":"10.1109/ECTC.2018.00058","DOIUrl":"https://doi.org/10.1109/ECTC.2018.00058","url":null,"abstract":"Heterogeneous integration with advanced packaging has recently been the subject of intensive discussion and development to pursue optimum electronic system performance. The concept of miniaturized systems is particularly important for applications such as wearable and portable devices, as demands for more integrated functionality, better performance and smaller form factors persist. In this paper, we reveal a new multilayer 3D fan-out stacking integration approach and an ultra-thin 6-layer stacked fan-out package with low warpage. Compared to typical 3D IC stacking with TSV, the new structure exhibits both vertical and lateral integration flexibility. This new 3D fan-out stacking scheme inherits the thermal dissipation benefits from fanout packages with reduced thermal cross-talk and therefore offers a powerful solution for highly heterogeneous and complex systems.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"68 1","pages":"337-342"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89816638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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