Kang Chen, Linda Chua, Won Kyung Choi, Seng Guan Chow, S. Yoon
To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, Embedded Wafer Level BGA (eWLB) is a fan-out WLP solution which can enable applications that require higher input/output (I/O) density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also provides integration of multiple dies vertically and horizontally in a single package without substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in 10x10~15x15mm 28nm eWLB fan-out WLP with multiple redistribution layers (RDLs). Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Electrical characterization was also studied for both simulation and experimental works. The influence of structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.
{"title":"28nm CPI (Chip/Package Interactions) in Large Size eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages","authors":"Kang Chen, Linda Chua, Won Kyung Choi, Seng Guan Chow, S. Yoon","doi":"10.1109/ECTC.2017.237","DOIUrl":"https://doi.org/10.1109/ECTC.2017.237","url":null,"abstract":"To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, Embedded Wafer Level BGA (eWLB) is a fan-out WLP solution which can enable applications that require higher input/output (I/O) density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also provides integration of multiple dies vertically and horizontally in a single package without substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in 10x10~15x15mm 28nm eWLB fan-out WLP with multiple redistribution layers (RDLs). Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Electrical characterization was also studied for both simulation and experimental works. The influence of structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"49 1","pages":"581-586"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78982707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design, simulation, and characterization of metamaterial-inspired terahertz filters, fabricated by aerosol-jet printing. Filters are designed for operation at 230, 245, and 510 GHz, for both band-pass and bandstop operation. Operation of each printed filter is compared to structures fabricated from copper metal using a photolithographic process. Each of the aerosol jet printed filters are found to have performance comparable to those fabricated using lithographic techniques, demonstrating the applicability of aerosol-jet printing to the fabrication of components operating in the terahertz regime.
{"title":"Aerosol-Jet Printed Quasi-Optical Terahertz Filters","authors":"Christopher Oakley, A. Kaur, J. Byford, P. Chahal","doi":"10.1109/ECTC.2017.233","DOIUrl":"https://doi.org/10.1109/ECTC.2017.233","url":null,"abstract":"This paper presents the design, simulation, and characterization of metamaterial-inspired terahertz filters, fabricated by aerosol-jet printing. Filters are designed for operation at 230, 245, and 510 GHz, for both band-pass and bandstop operation. Operation of each printed filter is compared to structures fabricated from copper metal using a photolithographic process. Each of the aerosol jet printed filters are found to have performance comparable to those fabricated using lithographic techniques, demonstrating the applicability of aerosol-jet printing to the fabrication of components operating in the terahertz regime.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"248-253"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79462788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Taneja, M. Volpert, G. Lasfargues, B. Chambion, B. Bouillard, Sylvie Jarjayes, T. Chaira, A. Vandeneynde, Y. Goiran, D. Henry, F. Hodaj
Several types of interconnects for the finer pitch assembly are currently being investigated across the globe. Here in this paper, a new type of interconnect Ni3Sn4 Interconnect is proposed and evaluated for assembly at 10 pitch and below. The proposed interconnect is compared to traditional solder interconnect. The comparison is done on the basis of shape of the joints in interconnects, the electric yield and mechanical properties. Later, Ni3Sn4 IMC interconnect is also compared to known Cu3Sn IMC Interconnect.
{"title":"Cu-SnAg Interconnects Evaluation for the Assembly at 10µm and 5µm Pitch","authors":"D. Taneja, M. Volpert, G. Lasfargues, B. Chambion, B. Bouillard, Sylvie Jarjayes, T. Chaira, A. Vandeneynde, Y. Goiran, D. Henry, F. Hodaj","doi":"10.1109/ECTC.2017.154","DOIUrl":"https://doi.org/10.1109/ECTC.2017.154","url":null,"abstract":"Several types of interconnects for the finer pitch assembly are currently being investigated across the globe. Here in this paper, a new type of interconnect Ni3Sn4 Interconnect is proposed and evaluated for assembly at 10 pitch and below. The proposed interconnect is compared to traditional solder interconnect. The comparison is done on the basis of shape of the joints in interconnects, the electric yield and mechanical properties. Later, Ni3Sn4 IMC interconnect is also compared to known Cu3Sn IMC Interconnect.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"47 1","pages":"376-383"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78387030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we have used nanoindentation methods to explore the creep behavior, and aging effects of SAC305 solder joints at several elevated testing temperatures from 25 to 125 oC. A special high temperature stage and test protocol was used within the nanoindentation system to carefully control the testing temperature, and make the measurements insensitive to thermal drift problems. Solder joints were extracted from 14 × 14 mm PBGA assemblies (0.8 mm ball pitch, 0.46 mm ball diameter) that were built as part of the iNEMI Characterization of Pb-Free Alloy Alternatives Project. Since the properties of SAC solder joints are highly dependent on crystal orientation, polarized light microscopy was utilized to determine the orientation of the tested joints. For all the experiments, only single grain solder joints were used to avoid introducing any unintentional variation from changes in the crystal orientation across the joint cross-section. After extraction, the single grain solder joints were subjected to various aging conditions. Nanoindentation testing was then performed on the aged specimens at five different testing temperatures (T = 25, 50, 75, 100, and 125 oC). In order to understand creep response of the solder joints at different temperatures, a constant force at max indentation was applied for 900 sec while the creep displacements were monitored. With this approach, we were able to measure the creep strain rate as a function of both temperature and prior aging conditions. As expected, our results have shown that indent/testing temperature has a significant impact on the mechanical properties and creep strain rate of solder joints. The measured data have also shown that the effects of aging on solder joints properties become much more significant as the testing temperature increases. In particular, the aging induced degradation rates at high temperatures (100-125 oC) were more than 100X those seen at room temperature. Nanoindentation pile-up effects, although insignificant at room temperature, were observed during high-temperature testing and corrections were made to limit their influence on the test results.
在这项工作中，我们使用纳米压痕方法来探索SAC305焊点在25至125℃的几种升高的测试温度下的蠕变行为和老化效应。在纳米压痕系统中采用了特殊的高温阶段和测试方案，以仔细控制测试温度，使测量不受热漂移问题的影响。焊点是从14 × 14 mm PBGA组件(0.8 mm球间距，0.46 mm球直径)中提取的，该组件是iNEMI无铅合金替代品表征项目的一部分。由于SAC焊点的性能高度依赖于晶体取向，因此利用偏振光显微镜来确定被测焊点的取向。在所有的实验中，只使用了单晶粒焊点，以避免在接头横截面上由于晶体取向的变化而引起任何无意的变化。提取后的单晶粒焊点进行了不同的时效处理。然后在5种不同的测试温度(T = 25、50、75、100和125℃)下对老化样品进行纳米压痕测试。为了了解焊点在不同温度下的蠕变响应，在最大压痕处施加恒定力900秒，同时监测蠕变位移。通过这种方法，我们能够测量蠕变应变率作为温度和先前老化条件的函数。正如预期的那样，我们的结果表明，压痕/测试温度对焊点的力学性能和蠕变应变率有显著影响。测试数据还表明，随着测试温度的升高，老化对焊点性能的影响更为显著。特别是，在高温(100-125℃)下，老化引起的降解率是室温下的100倍以上。纳米压痕堆积效应虽然在室温下不显著，但在高温测试中观察到，并进行了修正以限制其对测试结果的影响。
{"title":"Mechanical Characterization of SAC Solder Joints at High Temperature Using Nanoindentation","authors":"Sudan Ahmed, M. Hasnine, J. Suhling, P. Lall","doi":"10.1109/ECTC.2017.336","DOIUrl":"https://doi.org/10.1109/ECTC.2017.336","url":null,"abstract":"In this work, we have used nanoindentation methods to explore the creep behavior, and aging effects of SAC305 solder joints at several elevated testing temperatures from 25 to 125 oC. A special high temperature stage and test protocol was used within the nanoindentation system to carefully control the testing temperature, and make the measurements insensitive to thermal drift problems. Solder joints were extracted from 14 × 14 mm PBGA assemblies (0.8 mm ball pitch, 0.46 mm ball diameter) that were built as part of the iNEMI Characterization of Pb-Free Alloy Alternatives Project. Since the properties of SAC solder joints are highly dependent on crystal orientation, polarized light microscopy was utilized to determine the orientation of the tested joints. For all the experiments, only single grain solder joints were used to avoid introducing any unintentional variation from changes in the crystal orientation across the joint cross-section. After extraction, the single grain solder joints were subjected to various aging conditions. Nanoindentation testing was then performed on the aged specimens at five different testing temperatures (T = 25, 50, 75, 100, and 125 oC). In order to understand creep response of the solder joints at different temperatures, a constant force at max indentation was applied for 900 sec while the creep displacements were monitored. With this approach, we were able to measure the creep strain rate as a function of both temperature and prior aging conditions. As expected, our results have shown that indent/testing temperature has a significant impact on the mechanical properties and creep strain rate of solder joints. The measured data have also shown that the effects of aging on solder joints properties become much more significant as the testing temperature increases. In particular, the aging induced degradation rates at high temperatures (100-125 oC) were more than 100X those seen at room temperature. Nanoindentation pile-up effects, although insignificant at room temperature, were observed during high-temperature testing and corrections were made to limit their influence on the test results.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"69 1","pages":"1128-1135"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77896916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Boyer, Alexander Janta-Polczynski, J. Morissette, S. Martel, Ted W. Lichoulas, S. Kamlapurkar, S. Engelmann, P. Fortier, T. Barwicz
Cost-efficient assembly of single-mode fibers to silicon chips is a significant challenge for large-scale deployment of Si photonics. We have previously demonstrated a fully automated approach to parallelized assembly of fiber arrays to nanophotonic chips meant to be performed with standard high-throughput microelectronic tooling. Our original approach required a customization of a standard fiber component, which could limit cost-efficiency and scalability. Here, we demonstrate a novel approach to fiber assembly employing off-the-shelf fiber components only. The new concept employs a dual vacuum pick-tip that can be integrated in standard high-throughput microelectronic tooling. We validate this approach with assemblies of standard 12-fiber interfaces to nanophotonic chips. The assembly performance is assessed via x-ray tomography cross-sections, polished mechanical cross-sections, and optical coupling measurements.
{"title":"Novel, High-Throughput, Fiber-to-Chip Assembly Employing Only Off-the-Shelf Components","authors":"N. Boyer, Alexander Janta-Polczynski, J. Morissette, S. Martel, Ted W. Lichoulas, S. Kamlapurkar, S. Engelmann, P. Fortier, T. Barwicz","doi":"10.1109/ECTC.2017.185","DOIUrl":"https://doi.org/10.1109/ECTC.2017.185","url":null,"abstract":"Cost-efficient assembly of single-mode fibers to silicon chips is a significant challenge for large-scale deployment of Si photonics. We have previously demonstrated a fully automated approach to parallelized assembly of fiber arrays to nanophotonic chips meant to be performed with standard high-throughput microelectronic tooling. Our original approach required a customization of a standard fiber component, which could limit cost-efficiency and scalability. Here, we demonstrate a novel approach to fiber assembly employing off-the-shelf fiber components only. The new concept employs a dual vacuum pick-tip that can be integrated in standard high-throughput microelectronic tooling. We validate this approach with assemblies of standard 12-fiber interfaces to nanophotonic chips. The assembly performance is assessed via x-ray tomography cross-sections, polished mechanical cross-sections, and optical coupling measurements.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"52 1","pages":"1632-1639"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73369113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Phillips, J. Schwartz, A. Engler, Gerald Gourdin, P. Kohl
Transient electronics is an emerging field oftechnology where the controlled, programmable vaporizationof a device is needed because retrieval is not possible or adifferent form of disposal is desired. Decomposable polymersare of interest and may be used to form electronic componentsand packages. The ability to trigger these polymers todepolymerize and vaporize at ambient conditions can lead tomany applications. Low ceiling temperature polyaldehydeshave been evaluated for transience. Incorporation of morevolatile monomer units significantly increase the evaporationrate of decomposition products. The stimulus fordisappearance is a photochemical reaction that has beenextended from the ultraviolet to the visible region. Chemicalamplification of the trigger source has been demonstrated withacid amplifiers.
{"title":"Phototriggerable Transient Electronics: Materials and Concepts","authors":"O. Phillips, J. Schwartz, A. Engler, Gerald Gourdin, P. Kohl","doi":"10.1109/ECTC.2017.174","DOIUrl":"https://doi.org/10.1109/ECTC.2017.174","url":null,"abstract":"Transient electronics is an emerging field oftechnology where the controlled, programmable vaporizationof a device is needed because retrieval is not possible or adifferent form of disposal is desired. Decomposable polymersare of interest and may be used to form electronic componentsand packages. The ability to trigger these polymers todepolymerize and vaporize at ambient conditions can lead tomany applications. Low ceiling temperature polyaldehydeshave been evaluated for transience. Incorporation of morevolatile monomer units significantly increase the evaporationrate of decomposition products. The stimulus fordisappearance is a photochemical reaction that has beenextended from the ultraviolet to the visible region. Chemicalamplification of the trigger source has been demonstrated withacid amplifiers.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"772-779"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73823487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Che, M. Kawano, M. Ding, Y. Han, S. Bhattacharya
TSV-Free Interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. Co-design modelling methodology is established for TFI technology with considering wafer process, package assembly and package/board level reliability and thermal performance to optimize structure design, wafer process, assembly process and material selection. Experimental results are used for validating warpage modelling results. Through wafer level modelling, suitable carrier wafer and EMC materials are recommended to control wafer warpage less than 2mm. Effects of package substrate coefficient of thermal expansion (CTE) and stiffener on assembly induced package warpage are simulated to reduce package warpage. The recommended materials and geometry design based on reliability are aligned with that from wafer and package warpage simulation results. The final test vehicle (TV) design and material selection are determined based on co-design modelling results for achieving successful TFI wafer process and package assembly process and long term package/board level reliability.
{"title":"Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI)","authors":"F. Che, M. Kawano, M. Ding, Y. Han, S. Bhattacharya","doi":"10.1109/ECTC.2017.31","DOIUrl":"https://doi.org/10.1109/ECTC.2017.31","url":null,"abstract":"TSV-Free Interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. Co-design modelling methodology is established for TFI technology with considering wafer process, package assembly and package/board level reliability and thermal performance to optimize structure design, wafer process, assembly process and material selection. Experimental results are used for validating warpage modelling results. Through wafer level modelling, suitable carrier wafer and EMC materials are recommended to control wafer warpage less than 2mm. Effects of package substrate coefficient of thermal expansion (CTE) and stiffener on assembly induced package warpage are simulated to reduce package warpage. The recommended materials and geometry design based on reliability are aligned with that from wafer and package warpage simulation results. The final test vehicle (TV) design and material selection are determined based on co-design modelling results for achieving successful TFI wafer process and package assembly process and long term package/board level reliability.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"853-861"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73987271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nagarkar, Xiaoxiao Hou, N. Stoffel, E. Davis, Jeffrey M. Ashe, D. Borton
In this paper, we propose a fused silica packaging platform with a micro-cavity designed to house and protect active electronics for neural interfaces. Proof-of-concept test vehicles were specifically designed, fabricated, and packaged in order to evaluate the ability of the packaging to protect against water and ion incursion. Accelerated degradation testing of three test vehicles in physiological saline was performed in a custom-built encapsulation test system (ETS) at 57 °C for 16 days (nominally equivalent to 68 days at 37 °C). Leakage current, as well as gross functionality of the test circuit, was evaluated and is presented as preliminary results.
{"title":"Micro-Hermetic Packaging Technology for Active Implantable Neural Interfaces","authors":"K. Nagarkar, Xiaoxiao Hou, N. Stoffel, E. Davis, Jeffrey M. Ashe, D. Borton","doi":"10.1109/ECTC.2017.340","DOIUrl":"https://doi.org/10.1109/ECTC.2017.340","url":null,"abstract":"In this paper, we propose a fused silica packaging platform with a micro-cavity designed to house and protect active electronics for neural interfaces. Proof-of-concept test vehicles were specifically designed, fabricated, and packaged in order to evaluate the ability of the packaging to protect against water and ion incursion. Accelerated degradation testing of three test vehicles in physiological saline was performed in a custom-built encapsulation test system (ETS) at 57 °C for 16 days (nominally equivalent to 68 days at 37 °C). Leakage current, as well as gross functionality of the test circuit, was evaluated and is presented as preliminary results.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"218-223"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74234736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Hanss, E. Liu, M. Schmid, D. Müller, U. Karbowski, Robert Derix, G. Elger
A high reliability of light emitting diode (LED) light sources is essential for general and automotive lighting applications, where exchange of LED components is expensive. Thermal management of modern high power LEDs is crucial for their lifetime. An important aspect is the thermal path for heat conduction. Many different defects can have an influence on this path of an electronic system: on the one hand process failures during production, e.g. voids inside the solder joint, on the other hand typical failures induced by thermo-mechanical stress during their lifetime, like cracks in the solder joint or delamination in the package. The transient thermal analysis (TTA) is a powerful tool to detect changes in the thermal path. Due to improvements in the TTA method during the last years, not only cracks can be detected but also failure modes can be separated, and the root cause can be analyzed by support of transient finite element analysis. In this paper, transient thermal testing is applied and further developed, to monitor the structural integrity of new wafer level LED packages during thermal stress testing. Failure modes are defined and separated. For failure analysis the different defects are simulated by transient finite element analysis and correlated to the TTA results. The simulation results, that solder cracks increase the peak height of the derivative of the transient thermal curves (b(z)). A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 µs and 5 µs. Therefore a transient thermal measurement equipment with a dead time
{"title":"New Method to Separate Failure Modes by Transient Thermal Analysis of High Power LEDs","authors":"A. Hanss, E. Liu, M. Schmid, D. Müller, U. Karbowski, Robert Derix, G. Elger","doi":"10.1109/ECTC.2017.137","DOIUrl":"https://doi.org/10.1109/ECTC.2017.137","url":null,"abstract":"A high reliability of light emitting diode (LED) light sources is essential for general and automotive lighting applications, where exchange of LED components is expensive. Thermal management of modern high power LEDs is crucial for their lifetime. An important aspect is the thermal path for heat conduction. Many different defects can have an influence on this path of an electronic system: on the one hand process failures during production, e.g. voids inside the solder joint, on the other hand typical failures induced by thermo-mechanical stress during their lifetime, like cracks in the solder joint or delamination in the package. The transient thermal analysis (TTA) is a powerful tool to detect changes in the thermal path. Due to improvements in the TTA method during the last years, not only cracks can be detected but also failure modes can be separated, and the root cause can be analyzed by support of transient finite element analysis. In this paper, transient thermal testing is applied and further developed, to monitor the structural integrity of new wafer level LED packages during thermal stress testing. Failure modes are defined and separated. For failure analysis the different defects are simulated by transient finite element analysis and correlated to the TTA results. The simulation results, that solder cracks increase the peak height of the derivative of the transient thermal curves (b(z)). A delamination of an inner layer of the LED package creates additionally to the increase of the peak height also a separation of the b(z) curves between 1 µs and 5 µs. Therefore a transient thermal measurement equipment with a dead time","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"27 1","pages":"1136-1144"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73242413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Exploring along the road of More Moore with integration degree increasing significantly, different wafer level 3-D technologies are developed facing various circumstances. Thermal issue has become an important concern in IC designing and manufacturing. Fan-out wafer level package (FOWLP), as one of the most popular packaging trends lately, compared to high cost through silicon via (TSV) based 3D integration method, requires system level thermal management. Full scale numerical simulation as a critical procedure is facing huge difficulties, such as huge structure size variation, huge thermal properties variation, in-plane and off-plane displacement, etc. Equivalent thermal conductivity model (ETCM) based full scale numerical simulation for thermal management, which has already been applied to TSV based 3-D ICs with computation consumption significantly decreased, is applied to Fan-out packages in this paper. Equivalent and anisotropic thermal conductivity is calculated and modified concerning FOWLP structure and material thermal properties. A chip-first face-up fan-out package with 100 pads and 100 bumps is modeled and simulated, with mesh elements number drops from 874836 to 174810. With more than 80% computation consumption saved, less than 2% difference in total temperature rise is obtained compared with detail simulation.
{"title":"Equivalent Thermal Conductivity Model Based Full Scale Numerical Simulation for Thermal Management in Fan-Out Packages","authors":"Ningyu Wang, Yudan Pi, Wei Wang, Yufeng Jin","doi":"10.1109/ECTC.2017.82","DOIUrl":"https://doi.org/10.1109/ECTC.2017.82","url":null,"abstract":"Exploring along the road of More Moore with integration degree increasing significantly, different wafer level 3-D technologies are developed facing various circumstances. Thermal issue has become an important concern in IC designing and manufacturing. Fan-out wafer level package (FOWLP), as one of the most popular packaging trends lately, compared to high cost through silicon via (TSV) based 3D integration method, requires system level thermal management. Full scale numerical simulation as a critical procedure is facing huge difficulties, such as huge structure size variation, huge thermal properties variation, in-plane and off-plane displacement, etc. Equivalent thermal conductivity model (ETCM) based full scale numerical simulation for thermal management, which has already been applied to TSV based 3-D ICs with computation consumption significantly decreased, is applied to Fan-out packages in this paper. Equivalent and anisotropic thermal conductivity is calculated and modified concerning FOWLP structure and material thermal properties. A chip-first face-up fan-out package with 100 pads and 100 bumps is modeled and simulated, with mesh elements number drops from 874836 to 174810. With more than 80% computation consumption saved, less than 2% difference in total temperature rise is obtained compared with detail simulation.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"137 1","pages":"2054-2059"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80091122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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