Electronics in automotive applications may be used for a number of safety critical systems including lane-departure warning, collision avoidance, drive assist systems, and adaptive cruise control. Furthermore, electronics in fully-electric vehicles may be used for power generation and management. Automotive electronics may be mounted on engine or on transmission or in the base of the automobile and may be subjected to operational temperature excursions in addition to environmental temperature extremes. Further, automotive electronics systems may be subjected to prolonged periods of storage at ambient environmental low or high temperatures. There is need for tools and techniques for proactive assessment of consumed life, remaining useful-life, and spot assessment of thermo-mechanical reliability of electronics to assure reliable operation for the automotive benchmark of 10-years, 100,000 miles. In this study, the effect of thermal aging on thermal cycling reliability and the evolution of strain has been studied using digital image correlation. Leadfree assemblies which have been subjected to prolonged periods of aging have been subsequently subjected to thermal cycling and the strain amplitude experienced in the solder joints has been measured using digital image correlation. These strain state results then were correlated with microstructural damage rate (obtained from a separate study) to develop a damage mapping model. Finally, a new approach of life model along with Remaining Useful Life (RUL) estimation technique has been presented based upon microstructural damage rate.
{"title":"Effect of Mean Temperature on the Evolution of Strain-Amplitude in SAC Ball-Grid Arrays during Operation under Thermal Aging and Temperature Excursions","authors":"P. Lall, Kazi Mirza, J. Suhling, David Locker","doi":"10.1109/ECTC.2017.299","DOIUrl":"https://doi.org/10.1109/ECTC.2017.299","url":null,"abstract":"Electronics in automotive applications may be used for a number of safety critical systems including lane-departure warning, collision avoidance, drive assist systems, and adaptive cruise control. Furthermore, electronics in fully-electric vehicles may be used for power generation and management. Automotive electronics may be mounted on engine or on transmission or in the base of the automobile and may be subjected to operational temperature excursions in addition to environmental temperature extremes. Further, automotive electronics systems may be subjected to prolonged periods of storage at ambient environmental low or high temperatures. There is need for tools and techniques for proactive assessment of consumed life, remaining useful-life, and spot assessment of thermo-mechanical reliability of electronics to assure reliable operation for the automotive benchmark of 10-years, 100,000 miles. In this study, the effect of thermal aging on thermal cycling reliability and the evolution of strain has been studied using digital image correlation. Leadfree assemblies which have been subjected to prolonged periods of aging have been subsequently subjected to thermal cycling and the strain amplitude experienced in the solder joints has been measured using digital image correlation. These strain state results then were correlated with microstructural damage rate (obtained from a separate study) to develop a damage mapping model. Finally, a new approach of life model along with Remaining Useful Life (RUL) estimation technique has been presented based upon microstructural damage rate.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"1027-1038"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86817499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design, simulation, and characterization of metamaterial-inspired terahertz filters, fabricated by aerosol-jet printing. Filters are designed for operation at 230, 245, and 510 GHz, for both band-pass and bandstop operation. Operation of each printed filter is compared to structures fabricated from copper metal using a photolithographic process. Each of the aerosol jet printed filters are found to have performance comparable to those fabricated using lithographic techniques, demonstrating the applicability of aerosol-jet printing to the fabrication of components operating in the terahertz regime.
{"title":"Aerosol-Jet Printed Quasi-Optical Terahertz Filters","authors":"Christopher Oakley, A. Kaur, J. Byford, P. Chahal","doi":"10.1109/ECTC.2017.233","DOIUrl":"https://doi.org/10.1109/ECTC.2017.233","url":null,"abstract":"This paper presents the design, simulation, and characterization of metamaterial-inspired terahertz filters, fabricated by aerosol-jet printing. Filters are designed for operation at 230, 245, and 510 GHz, for both band-pass and bandstop operation. Operation of each printed filter is compared to structures fabricated from copper metal using a photolithographic process. Each of the aerosol jet printed filters are found to have performance comparable to those fabricated using lithographic techniques, demonstrating the applicability of aerosol-jet printing to the fabrication of components operating in the terahertz regime.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"248-253"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79462788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Li-Yin Gao, Li Liu, Zhi-Quan Liu, Jing Wang, Zhaoxia Zhou, Changqing Liu
The high temperature storage test (HTST) was conducted on the SnAgCu/Ni-W-P and Ni-Fe solder joints. While the conventional Ni-P solder joints were used as comparison to study the diffusion barrier effect of Ni-W-P and Ni-Fe under bump metallization (UBM). Both cross section and top view for the microstructural evolution of solder joints during 150°C aging were observed by the scanning electron microscope (SEM). After reflow, (Cu, Ni)6Sn5 in the forms of chunky and rod-like was formed with an average thickness of around 1µm in SAC/Ni-P solder joint. During the HTST, bulky (Cu, Ni)6Sn5 grains were formed with a 5µm in diameter due to the interconnections of multiple (Cu, Ni)6Sn5 grains. In terms of SAC/Ni-Fe solder joints, during the reflow process, FeSn2 layer and rod-like (Cu, Ni)6Sn5 grains were formed. During the aging at 150°C, rod-like dispersed (Cu, Ni)6Sn5 grains started to interconnect with each other which finally progressed into an outer IMC layer upon FeSn2 phase. In Ni-W-P solder joints, the morphology and composition of IMCs is similar to it in Ni-P solder joints. The thickness of (Cu, Ni)6Sn5 was much thicker during reflow but turned out to be below it in Ni-P solder joints after 120h aging. Experimentally, both Ni-W-P and Ni-Fe UBM show an excellent diffusion barrier effect to retard the Kirkendall voids formation compared to the conventional Ni-P UBM. Specifically, (Cu, Ni)6Sn5 were formed at the SnAgCu/ Ni-W-P interface with a total thickness around 2µm, while only a 1µm thick FeSn2 layer accompanying with several dispersing (Cu, Ni)6Sn5 grains outside were formed at the SnAgCu/Ni-Fe interface. The addition of Fe elements can dramatically supress the diffusion of Ni and the formation of Ni3Sn4, which shows superior diffusion barrier compared to Ni-P UBM. The addition of W into Ni-P significantly decreases the growth rate of the interfacial IMCs during the aging process, which shows potential for electronic devices operated under long-term aging process.
对SnAgCu/Ni-W-P和Ni-Fe焊点进行了高温贮存试验。以传统的Ni-P焊点为对照，研究了凹凸金属化过程中Ni-W-P和Ni-Fe的扩散阻挡效应。利用扫描电子显微镜(SEM)观察了焊点在150℃时效过程中的组织演变过程。回流后，SAC/Ni- p焊点中形成块状和棒状的(Cu, Ni)6Sn5，平均厚度约为1µm。在高温加热过程中，由于多个(Cu, Ni)6Sn5晶粒相互连接，形成了直径为5 μ m的大块(Cu, Ni)6Sn5晶粒。SAC/Ni- fe焊点在回流过程中形成了FeSn2层和棒状(Cu, Ni)6Sn5晶粒。在150℃时效过程中，棒状分散(Cu, Ni)6Sn5晶粒开始相互连接，最终在FeSn2相上形成外IMC层。在Ni-W-P焊点中，IMCs的形貌和组成与Ni-P焊点相似。(Cu, Ni)6Sn5在回流焊时厚度较厚，但时效120h后在Ni- p焊点中厚度低于该厚度。实验结果表明，与传统的Ni-P复合材料相比，Ni-W-P复合材料和Ni-Fe复合材料均表现出良好的扩散阻挡效应，可以抑制Kirkendall空洞的形成。其中，(Cu, Ni)6Sn5在SnAgCu/Ni- w - p界面形成，总厚度约为2µm，而在SnAgCu/Ni- fe界面形成的FeSn2层厚度仅为1µm，并在表面形成分散的(Cu, Ni)6Sn5晶粒。Fe元素的加入能显著抑制Ni的扩散和Ni3Sn4的形成，表现出比Ni- p UBM更强的扩散屏障。在Ni-P中加入W可显著降低老化过程中界面imc的生长速度，显示出在长期老化过程中工作的电子器件的潜力。
{"title":"Diffusion Barrier Effect of Ni-W-P and Ni-Fe UBMs during High Temperature Storage","authors":"Li-Yin Gao, Li Liu, Zhi-Quan Liu, Jing Wang, Zhaoxia Zhou, Changqing Liu","doi":"10.1109/ECTC.2017.51","DOIUrl":"https://doi.org/10.1109/ECTC.2017.51","url":null,"abstract":"The high temperature storage test (HTST) was conducted on the SnAgCu/Ni-W-P and Ni-Fe solder joints. While the conventional Ni-P solder joints were used as comparison to study the diffusion barrier effect of Ni-W-P and Ni-Fe under bump metallization (UBM). Both cross section and top view for the microstructural evolution of solder joints during 150°C aging were observed by the scanning electron microscope (SEM). After reflow, (Cu, Ni)6Sn5 in the forms of chunky and rod-like was formed with an average thickness of around 1µm in SAC/Ni-P solder joint. During the HTST, bulky (Cu, Ni)6Sn5 grains were formed with a 5µm in diameter due to the interconnections of multiple (Cu, Ni)6Sn5 grains. In terms of SAC/Ni-Fe solder joints, during the reflow process, FeSn2 layer and rod-like (Cu, Ni)6Sn5 grains were formed. During the aging at 150°C, rod-like dispersed (Cu, Ni)6Sn5 grains started to interconnect with each other which finally progressed into an outer IMC layer upon FeSn2 phase. In Ni-W-P solder joints, the morphology and composition of IMCs is similar to it in Ni-P solder joints. The thickness of (Cu, Ni)6Sn5 was much thicker during reflow but turned out to be below it in Ni-P solder joints after 120h aging. Experimentally, both Ni-W-P and Ni-Fe UBM show an excellent diffusion barrier effect to retard the Kirkendall voids formation compared to the conventional Ni-P UBM. Specifically, (Cu, Ni)6Sn5 were formed at the SnAgCu/ Ni-W-P interface with a total thickness around 2µm, while only a 1µm thick FeSn2 layer accompanying with several dispersing (Cu, Ni)6Sn5 grains outside were formed at the SnAgCu/Ni-Fe interface. The addition of Fe elements can dramatically supress the diffusion of Ni and the formation of Ni3Sn4, which shows superior diffusion barrier compared to Ni-P UBM. The addition of W into Ni-P significantly decreases the growth rate of the interfacial IMCs during the aging process, which shows potential for electronic devices operated under long-term aging process.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"1566-1571"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90927735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nan Wang, Yao Zhu, Chengliang Sun, Mingbin Yu, G. Chua, S. Merugu, Navab Singh, Y. Gu
This paper reports two types of in-house fabricated aluminium nitride (AlN) based piezoelectric resonators, namely the thickness mode resonator and the Lamb-wave mode resonator, which are capable to be integrated with Through Silicon Via (TSV) technology, forming the basis of advanced filters, duplexers and multiplexers. Both types of the resonators, which are fabricated using a CMOS compatible platform, consist of a layer of 1 µm thick piezoelectric layer and two layers of molybdenum (Mo) electrodes covering the top and the bottom surface of the AlN layer. Resonant frequencies above 2GHz, as well as motional impedance less than 10Ω, are obtained when the fabricated resonators are connected directly to the 50Ω terminations of a network analyzer, making both types of resonators suitable for high-band LTE applications. Furthermore, negligible performance drift was observed for both types of resonators fabricated upon undergoing accelerated thermal cycling test, indicating the superior reliability and long-term stability of the fabricated AlN based MEMS resonators and showing their great potential for communications applications in the automotive industry, where reliability and long-term stability is a key requirement for device performance.
{"title":"High-Band AlN Based RF-MEMS Resonator for TSV Integration","authors":"Nan Wang, Yao Zhu, Chengliang Sun, Mingbin Yu, G. Chua, S. Merugu, Navab Singh, Y. Gu","doi":"10.1109/ECTC.2017.220","DOIUrl":"https://doi.org/10.1109/ECTC.2017.220","url":null,"abstract":"This paper reports two types of in-house fabricated aluminium nitride (AlN) based piezoelectric resonators, namely the thickness mode resonator and the Lamb-wave mode resonator, which are capable to be integrated with Through Silicon Via (TSV) technology, forming the basis of advanced filters, duplexers and multiplexers. Both types of the resonators, which are fabricated using a CMOS compatible platform, consist of a layer of 1 µm thick piezoelectric layer and two layers of molybdenum (Mo) electrodes covering the top and the bottom surface of the AlN layer. Resonant frequencies above 2GHz, as well as motional impedance less than 10Ω, are obtained when the fabricated resonators are connected directly to the 50Ω terminations of a network analyzer, making both types of resonators suitable for high-band LTE applications. Furthermore, negligible performance drift was observed for both types of resonators fabricated upon undergoing accelerated thermal cycling test, indicating the superior reliability and long-term stability of the fabricated AlN based MEMS resonators and showing their great potential for communications applications in the automotive industry, where reliability and long-term stability is a key requirement for device performance.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"74 1","pages":"1868-1873"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80739667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, we have used nanoindentation methods to explore the creep behavior, and aging effects of SAC305 solder joints at several elevated testing temperatures from 25 to 125 oC. A special high temperature stage and test protocol was used within the nanoindentation system to carefully control the testing temperature, and make the measurements insensitive to thermal drift problems. Solder joints were extracted from 14 × 14 mm PBGA assemblies (0.8 mm ball pitch, 0.46 mm ball diameter) that were built as part of the iNEMI Characterization of Pb-Free Alloy Alternatives Project. Since the properties of SAC solder joints are highly dependent on crystal orientation, polarized light microscopy was utilized to determine the orientation of the tested joints. For all the experiments, only single grain solder joints were used to avoid introducing any unintentional variation from changes in the crystal orientation across the joint cross-section. After extraction, the single grain solder joints were subjected to various aging conditions. Nanoindentation testing was then performed on the aged specimens at five different testing temperatures (T = 25, 50, 75, 100, and 125 oC). In order to understand creep response of the solder joints at different temperatures, a constant force at max indentation was applied for 900 sec while the creep displacements were monitored. With this approach, we were able to measure the creep strain rate as a function of both temperature and prior aging conditions. As expected, our results have shown that indent/testing temperature has a significant impact on the mechanical properties and creep strain rate of solder joints. The measured data have also shown that the effects of aging on solder joints properties become much more significant as the testing temperature increases. In particular, the aging induced degradation rates at high temperatures (100-125 oC) were more than 100X those seen at room temperature. Nanoindentation pile-up effects, although insignificant at room temperature, were observed during high-temperature testing and corrections were made to limit their influence on the test results.
在这项工作中，我们使用纳米压痕方法来探索SAC305焊点在25至125℃的几种升高的测试温度下的蠕变行为和老化效应。在纳米压痕系统中采用了特殊的高温阶段和测试方案，以仔细控制测试温度，使测量不受热漂移问题的影响。焊点是从14 × 14 mm PBGA组件(0.8 mm球间距，0.46 mm球直径)中提取的，该组件是iNEMI无铅合金替代品表征项目的一部分。由于SAC焊点的性能高度依赖于晶体取向，因此利用偏振光显微镜来确定被测焊点的取向。在所有的实验中，只使用了单晶粒焊点，以避免在接头横截面上由于晶体取向的变化而引起任何无意的变化。提取后的单晶粒焊点进行了不同的时效处理。然后在5种不同的测试温度(T = 25、50、75、100和125℃)下对老化样品进行纳米压痕测试。为了了解焊点在不同温度下的蠕变响应，在最大压痕处施加恒定力900秒，同时监测蠕变位移。通过这种方法，我们能够测量蠕变应变率作为温度和先前老化条件的函数。正如预期的那样，我们的结果表明，压痕/测试温度对焊点的力学性能和蠕变应变率有显著影响。测试数据还表明，随着测试温度的升高，老化对焊点性能的影响更为显著。特别是，在高温(100-125℃)下，老化引起的降解率是室温下的100倍以上。纳米压痕堆积效应虽然在室温下不显著，但在高温测试中观察到，并进行了修正以限制其对测试结果的影响。
{"title":"Mechanical Characterization of SAC Solder Joints at High Temperature Using Nanoindentation","authors":"Sudan Ahmed, M. Hasnine, J. Suhling, P. Lall","doi":"10.1109/ECTC.2017.336","DOIUrl":"https://doi.org/10.1109/ECTC.2017.336","url":null,"abstract":"In this work, we have used nanoindentation methods to explore the creep behavior, and aging effects of SAC305 solder joints at several elevated testing temperatures from 25 to 125 oC. A special high temperature stage and test protocol was used within the nanoindentation system to carefully control the testing temperature, and make the measurements insensitive to thermal drift problems. Solder joints were extracted from 14 × 14 mm PBGA assemblies (0.8 mm ball pitch, 0.46 mm ball diameter) that were built as part of the iNEMI Characterization of Pb-Free Alloy Alternatives Project. Since the properties of SAC solder joints are highly dependent on crystal orientation, polarized light microscopy was utilized to determine the orientation of the tested joints. For all the experiments, only single grain solder joints were used to avoid introducing any unintentional variation from changes in the crystal orientation across the joint cross-section. After extraction, the single grain solder joints were subjected to various aging conditions. Nanoindentation testing was then performed on the aged specimens at five different testing temperatures (T = 25, 50, 75, 100, and 125 oC). In order to understand creep response of the solder joints at different temperatures, a constant force at max indentation was applied for 900 sec while the creep displacements were monitored. With this approach, we were able to measure the creep strain rate as a function of both temperature and prior aging conditions. As expected, our results have shown that indent/testing temperature has a significant impact on the mechanical properties and creep strain rate of solder joints. The measured data have also shown that the effects of aging on solder joints properties become much more significant as the testing temperature increases. In particular, the aging induced degradation rates at high temperatures (100-125 oC) were more than 100X those seen at room temperature. Nanoindentation pile-up effects, although insignificant at room temperature, were observed during high-temperature testing and corrections were made to limit their influence on the test results.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"69 1","pages":"1128-1135"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77896916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Taneja, M. Volpert, G. Lasfargues, B. Chambion, B. Bouillard, Sylvie Jarjayes, T. Chaira, A. Vandeneynde, Y. Goiran, D. Henry, F. Hodaj
Several types of interconnects for the finer pitch assembly are currently being investigated across the globe. Here in this paper, a new type of interconnect Ni3Sn4 Interconnect is proposed and evaluated for assembly at 10 pitch and below. The proposed interconnect is compared to traditional solder interconnect. The comparison is done on the basis of shape of the joints in interconnects, the electric yield and mechanical properties. Later, Ni3Sn4 IMC interconnect is also compared to known Cu3Sn IMC Interconnect.
{"title":"Cu-SnAg Interconnects Evaluation for the Assembly at 10µm and 5µm Pitch","authors":"D. Taneja, M. Volpert, G. Lasfargues, B. Chambion, B. Bouillard, Sylvie Jarjayes, T. Chaira, A. Vandeneynde, Y. Goiran, D. Henry, F. Hodaj","doi":"10.1109/ECTC.2017.154","DOIUrl":"https://doi.org/10.1109/ECTC.2017.154","url":null,"abstract":"Several types of interconnects for the finer pitch assembly are currently being investigated across the globe. Here in this paper, a new type of interconnect Ni3Sn4 Interconnect is proposed and evaluated for assembly at 10 pitch and below. The proposed interconnect is compared to traditional solder interconnect. The comparison is done on the basis of shape of the joints in interconnects, the electric yield and mechanical properties. Later, Ni3Sn4 IMC interconnect is also compared to known Cu3Sn IMC Interconnect.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"47 1","pages":"376-383"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78387030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kang Chen, Linda Chua, Won Kyung Choi, Seng Guan Chow, S. Yoon
To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, Embedded Wafer Level BGA (eWLB) is a fan-out WLP solution which can enable applications that require higher input/output (I/O) density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also provides integration of multiple dies vertically and horizontally in a single package without substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in 10x10~15x15mm 28nm eWLB fan-out WLP with multiple redistribution layers (RDLs). Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Electrical characterization was also studied for both simulation and experimental works. The influence of structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.
{"title":"28nm CPI (Chip/Package Interactions) in Large Size eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages","authors":"Kang Chen, Linda Chua, Won Kyung Choi, Seng Guan Chow, S. Yoon","doi":"10.1109/ECTC.2017.237","DOIUrl":"https://doi.org/10.1109/ECTC.2017.237","url":null,"abstract":"To meet the continued demand for form factor reduction and functional integration of electronic devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison with standard Ball Grid Array (BGA) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, Embedded Wafer Level BGA (eWLB) is a fan-out WLP solution which can enable applications that require higher input/output (I/O) density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also provides integration of multiple dies vertically and horizontally in a single package without substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in 10x10~15x15mm 28nm eWLB fan-out WLP with multiple redistribution layers (RDLs). Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Electrical characterization was also studied for both simulation and experimental works. The influence of structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"49 1","pages":"581-586"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78982707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Bellaredj, S. Mueller, A. Davis, Paul A. Kohl, Madhavan Swaminathan, Y. Mano
Integrated voltage regulators (IVRs) are considered nowadays as major elements in the development of power delivery networks for digital electronics because of their ability to implement point-of-load voltage regulation in multicore microprocessors and system-on-chip (SoC) architectures. Inductive regulators generally enable higher power efficiency over a wide range of conversion voltages. However, high efficiency IVRs require the integration of power inductors with low loss and reduced size at very high frequency. The use of a magnetic material core can reduce significantly the inductor area while increasing the inductance value at the same time. This paper focuses on the fabrication, characterization and modeling of Nickel Zinc (NiZn) Ferrite and Carbonyl Iron powder (CIP) epoxy composite magnet material which will be used as the magnetic core material of an embedded inductor in the PWB for SIP based buck type IVR. The fabricated composite materials and process are fully compatible with FR4 epoxy resin prepreg and laminate (PWB-compatible). The composite materials show (for 85% weigh loading, around 100 MHz at room temperature) a relative permeability between 7.5-8.1 for NiZn-composite (0.78 volume fraction) and between 5.2-5.6 for CIP composite (0.47 volume fraction) and a loss tangent value between 0.24-0.28 for NiZn-composite and 0.09- 0.1 for CIP-composite. The variation of the relative permeability and the frequency dispersion parameters of the magnetic composites are evaluated using Maxwell-Garnet Approximation (MGA) mixing rule and a simplified Lorentz and Landau-Lifshitz-Gilbert equation for Debye type relaxation. Evaluation of a buck type IVR based on the measured material properties shows that an embedded solenoidal inductor with an open core made with the NiZn Ferrite and CIP composite magnets can reach peak efficiencies of 91.7 % at 11 MHz for NiZn-composite, 91.6 % at 14 MHz for CIP-composite and 87.5 % (NiZn-composite) and 87.3 % (CIP-composite) efficiencies at 100 MHz for a 1.7V:1.05V conversion.
{"title":"Fabrication, Characterization and Comparison of FR4-Compatible Composite Magnetic Materials for High Efficiency Integrated Voltage Regulators with Embedded Magnetic Core Micro-Inductors","authors":"M. Bellaredj, S. Mueller, A. Davis, Paul A. Kohl, Madhavan Swaminathan, Y. Mano","doi":"10.1109/ECTC.2017.187","DOIUrl":"https://doi.org/10.1109/ECTC.2017.187","url":null,"abstract":"Integrated voltage regulators (IVRs) are considered nowadays as major elements in the development of power delivery networks for digital electronics because of their ability to implement point-of-load voltage regulation in multicore microprocessors and system-on-chip (SoC) architectures. Inductive regulators generally enable higher power efficiency over a wide range of conversion voltages. However, high efficiency IVRs require the integration of power inductors with low loss and reduced size at very high frequency. The use of a magnetic material core can reduce significantly the inductor area while increasing the inductance value at the same time. This paper focuses on the fabrication, characterization and modeling of Nickel Zinc (NiZn) Ferrite and Carbonyl Iron powder (CIP) epoxy composite magnet material which will be used as the magnetic core material of an embedded inductor in the PWB for SIP based buck type IVR. The fabricated composite materials and process are fully compatible with FR4 epoxy resin prepreg and laminate (PWB-compatible). The composite materials show (for 85% weigh loading, around 100 MHz at room temperature) a relative permeability between 7.5-8.1 for NiZn-composite (0.78 volume fraction) and between 5.2-5.6 for CIP composite (0.47 volume fraction) and a loss tangent value between 0.24-0.28 for NiZn-composite and 0.09- 0.1 for CIP-composite. The variation of the relative permeability and the frequency dispersion parameters of the magnetic composites are evaluated using Maxwell-Garnet Approximation (MGA) mixing rule and a simplified Lorentz and Landau-Lifshitz-Gilbert equation for Debye type relaxation. Evaluation of a buck type IVR based on the measured material properties shows that an embedded solenoidal inductor with an open core made with the NiZn Ferrite and CIP composite magnets can reach peak efficiencies of 91.7 % at 11 MHz for NiZn-composite, 91.6 % at 14 MHz for CIP-composite and 87.5 % (NiZn-composite) and 87.3 % (CIP-composite) efficiencies at 100 MHz for a 1.7V:1.05V conversion.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"4 1","pages":"2008-2014"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88471631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Lall, Nakul Kothari, John Deep, J. Foley, Ryan Lowe
Electronic fuze assemblies may be exposed to harsh environments during prolonged storage, transport and deployment. Under exposure to storage-transport environmental loads including mechanical shock, temperature, vibration and humidity the fuze assemblies may sustain damage without any surface signs of visible degradation. Further, the operational environment requires survivability under high-g loads often in excess of 10,000g. The need for non-destructive test methods to allow for determination of the internal damage and the assessment of expected operational reliability under the presence of accrued damage from prolonged storage is extremely desirable. While a number of non-destructive test methods such as x-ray, and acoustic imaging exist in the state-of-art – they are limited to the acquisition of imaging of the internal damage state without the ability of conducting measurement of deformation under the action of environment loads. In this paper, a new method has been presented for the creation of the finite element models using x-ray micro-computed tomography data. Further, a method has been presented for measurement of internal deformation in fuze assemblies under the action of environment temperature gradients prior to and subsequent to exposure to operational mechanical shock using a combination of x-ray micro-computed tomography and digital volume correlation.
{"title":"Development of FE Models and Measurement of Internal Deformations of Fuze Electronics Using X-Ray MicroCT Data with Digital Volume Correlation","authors":"P. Lall, Nakul Kothari, John Deep, J. Foley, Ryan Lowe","doi":"10.1109/ECTC.2017.302","DOIUrl":"https://doi.org/10.1109/ECTC.2017.302","url":null,"abstract":"Electronic fuze assemblies may be exposed to harsh environments during prolonged storage, transport and deployment. Under exposure to storage-transport environmental loads including mechanical shock, temperature, vibration and humidity the fuze assemblies may sustain damage without any surface signs of visible degradation. Further, the operational environment requires survivability under high-g loads often in excess of 10,000g. The need for non-destructive test methods to allow for determination of the internal damage and the assessment of expected operational reliability under the presence of accrued damage from prolonged storage is extremely desirable. While a number of non-destructive test methods such as x-ray, and acoustic imaging exist in the state-of-art – they are limited to the acquisition of imaging of the internal damage state without the ability of conducting measurement of deformation under the action of environment loads. In this paper, a new method has been presented for the creation of the finite element models using x-ray micro-computed tomography data. Further, a method has been presented for measurement of internal deformation in fuze assemblies under the action of environment temperature gradients prior to and subsequent to exposure to operational mechanical shock using a combination of x-ray micro-computed tomography and digital volume correlation.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"497-506"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88802734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fan-out wafer level packaging technology becomes more attractive and popular in the semiconductor packaging industry. The fan-out wafer level package (FOWLP) has the feature of integrating various devices in a tiny form factor. Since the FOWLP size is compact and small, its package strength is critical to its reliability. In this work, the three-point bending test method and finite element method was used to evaluate the FOWLP strength. Two different structural FOWLP were built, and their numerical models were created. The results showed that the FOWLP experiment and simulation flexure strength results matched each other in the lower failure possibility area closely. However, the simulation results under-estimated the FOWLP failure possibility to compare with the experiment results in the upper failure possibility area.
{"title":"Numerical and Experimental Study of Fan-Out Wafer Level Package Strength","authors":"Cheng Xu, Z. Zhong, W. Choi","doi":"10.1109/ECTC.2017.152","DOIUrl":"https://doi.org/10.1109/ECTC.2017.152","url":null,"abstract":"Fan-out wafer level packaging technology becomes more attractive and popular in the semiconductor packaging industry. The fan-out wafer level package (FOWLP) has the feature of integrating various devices in a tiny form factor. Since the FOWLP size is compact and small, its package strength is critical to its reliability. In this work, the three-point bending test method and finite element method was used to evaluate the FOWLP strength. Two different structural FOWLP were built, and their numerical models were created. The results showed that the FOWLP experiment and simulation flexure strength results matched each other in the lower failure possibility area closely. However, the simulation results under-estimated the FOWLP failure possibility to compare with the experiment results in the upper failure possibility area.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"18 1","pages":"2187-2192"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91163845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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