Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310388
Chul Kim, Siddharth Joshi, Hristos S. Courellis, Jun Wang, Cory T. Miller, G. Cauwenberghs
High-density multi-channel neural recording is critical to driving advances in neuroscience and neuroengineering through increasing the spatial resolution and dynamic range of brain-machine interfaces. Neural-signal-acquisition ICs have conventionally been designed composed of two distinct functional blocks per recording channel: a low-noise amplifier front-end (AFE), and an analog-digital converter (ADC) [1,2]. Hybrid architectures utilizing oversampling ADCs with digital feedback [3-5] have seen recent adoption due to their increased power and area efficiency. Still, input dynamic range (DR) is relatively limited due to aggressive supply voltage scaling and/or kT/C sampling noise. This paper presents a neural-recording ADC chip with 92dB input dynamic range and 0.99μVrms of noise at 0.8μW power consumption per channel over 500Hz signal bandwidth, owing to 1) a predictive digital autoranging (PDA) scheme in a hybrid analog-digital 2nd-order oversampling ADC architecture, 2) no specific sampling process through capacitors, avoiding kT/C noise altogether. Digitally predicting the analog input at 12b resolution from a 1b quantization of the continuously integrated residue at effective 32 oversampling ratio (OSR), the PDA handles a ±130mV electrode differential offset (EDO) and recovers from >200mVpp transient artifacts within <1ms. Furthermore, using digital circuits for integration ensures the architecture benefits from process scaling and the resulting compactness makes it suitable for incorporation in high-density recording arrays.
{"title":"A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autoranging","authors":"Chul Kim, Siddharth Joshi, Hristos S. Courellis, Jun Wang, Cory T. Miller, G. Cauwenberghs","doi":"10.1109/ISSCC.2018.8310388","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310388","url":null,"abstract":"High-density multi-channel neural recording is critical to driving advances in neuroscience and neuroengineering through increasing the spatial resolution and dynamic range of brain-machine interfaces. Neural-signal-acquisition ICs have conventionally been designed composed of two distinct functional blocks per recording channel: a low-noise amplifier front-end (AFE), and an analog-digital converter (ADC) [1,2]. Hybrid architectures utilizing oversampling ADCs with digital feedback [3-5] have seen recent adoption due to their increased power and area efficiency. Still, input dynamic range (DR) is relatively limited due to aggressive supply voltage scaling and/or kT/C sampling noise. This paper presents a neural-recording ADC chip with 92dB input dynamic range and 0.99μVrms of noise at 0.8μW power consumption per channel over 500Hz signal bandwidth, owing to 1) a predictive digital autoranging (PDA) scheme in a hybrid analog-digital 2nd-order oversampling ADC architecture, 2) no specific sampling process through capacitors, avoiding kT/C noise altogether. Digitally predicting the analog input at 12b resolution from a 1b quantization of the continuously integrated residue at effective 32 oversampling ratio (OSR), the PDA handles a ±130mV electrode differential offset (EDO) and recovers from >200mVpp transient artifacts within <1ms. Furthermore, using digital circuits for integration ensures the architecture benefits from process scaling and the resulting compactness makes it suitable for incorporation in high-density recording arrays.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"112 1","pages":"470-472"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75655102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310190
S. Shahramian, M. Holyoak, Amit Singh, B. J. Farahani, Y. Baeyens
Advanced SiGe BiCMOS and CMOS processes continue to push the frontier on millimeter-wave (mm-wave) and highly integrated phased-array systems for a variety of communication applications [1,3]. Furthermore, next-generation mobile technology (5G) demands ultra-low latency and high data-rates with ubiquitous deployment supporting multi-users through the use of pico-cells. These cells may require up to hundreds of active elements capable of producing thousands of beam patterns. In order to make wide adoption of such mm-wave systems a reality, the overall cost of the system must be significantly reduced. This can be accomplished through several means. First, producing highly-integrated phased arrays eliminates the need for additional external components (such as expensive mm-wave synthesizers, amplifiers and switches), which reduces the overall system costs. Second, eliminating exotic packaging processes and materials would allow low-cost traditional manufacturing techniques to be applied to mm-wave systems. Lastly, incorporating self-test, fault-detection, health-monitoring and self-calibration into the RFIC significantly reduces the costs of factory testing (by eliminating the need for any mm-wave verifications) and enables remote-maintenance and system-reconfiguration in case of failures.
{"title":"A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test","authors":"S. Shahramian, M. Holyoak, Amit Singh, B. J. Farahani, Y. Baeyens","doi":"10.1109/ISSCC.2018.8310190","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310190","url":null,"abstract":"Advanced SiGe BiCMOS and CMOS processes continue to push the frontier on millimeter-wave (mm-wave) and highly integrated phased-array systems for a variety of communication applications [1,3]. Furthermore, next-generation mobile technology (5G) demands ultra-low latency and high data-rates with ubiquitous deployment supporting multi-users through the use of pico-cells. These cells may require up to hundreds of active elements capable of producing thousands of beam patterns. In order to make wide adoption of such mm-wave systems a reality, the overall cost of the system must be significantly reduced. This can be accomplished through several means. First, producing highly-integrated phased arrays eliminates the need for additional external components (such as expensive mm-wave synthesizers, amplifiers and switches), which reduces the overall system costs. Second, eliminating exotic packaging processes and materials would allow low-cost traditional manufacturing techniques to be applied to mm-wave systems. Lastly, incorporating self-test, fault-detection, health-monitoring and self-calibration into the RFIC significantly reduces the costs of factory testing (by eliminating the need for any mm-wave verifications) and enables remote-maintenance and system-reconfiguration in case of failures.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"66 1","pages":"74-76"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80009346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310348
S. Chen, Lei Zhou, Ian Zhuang, J. Im, Didem Turkur Melek, Jinyung Namkoong, M. Raj, Jaewook Shin, Y. Frans, Ken Chang
As ever-increasing bandwidth demand pushes wireline transceiver data-rates beyond 25Gb/s, the clocking solution for multi-protocol support over a wide range of data-rates becomes a key design challenge. In [1], an injection-locked multi-phase clock generator demonstrated wideband operation and a high-resolution phase rotator using CML in 28nm FDSOI CMOS. However, in 7nm FinFET technology, the CML implementation suffers from the reduced supply level and output impedance degradation at high temperatures. In order to scale power consumption with data-rate, CML implementation also needs to employ bias current and load programmability, further impacting its performance. For these reasons, the supply-regulated inverter-based clocking scheme is proposed. Furthermore, the full inverter-based clock chain generates smaller random jitter (RJ) because of the faster edge-rate compared to a CML implementation. Supply regulation, applied as part of the calibration loop, mitigates the sensitivity to inverter delay and edge-rate over the process and temperature variations. This design, benefiting from its mostly-digital structure, adopts “sea of gates” layout style with optimized via patterns and uniform metal tracks, which effectively alleviate the significant parasitic resistance variations on low level metals fabricated by multiple patterning in 7nm FinFET.
{"title":"A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET","authors":"S. Chen, Lei Zhou, Ian Zhuang, J. Im, Didem Turkur Melek, Jinyung Namkoong, M. Raj, Jaewook Shin, Y. Frans, Ken Chang","doi":"10.1109/ISSCC.2018.8310348","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310348","url":null,"abstract":"As ever-increasing bandwidth demand pushes wireline transceiver data-rates beyond 25Gb/s, the clocking solution for multi-protocol support over a wide range of data-rates becomes a key design challenge. In [1], an injection-locked multi-phase clock generator demonstrated wideband operation and a high-resolution phase rotator using CML in 28nm FDSOI CMOS. However, in 7nm FinFET technology, the CML implementation suffers from the reduced supply level and output impedance degradation at high temperatures. In order to scale power consumption with data-rate, CML implementation also needs to employ bias current and load programmability, further impacting its performance. For these reasons, the supply-regulated inverter-based clocking scheme is proposed. Furthermore, the full inverter-based clock chain generates smaller random jitter (RJ) because of the faster edge-rate compared to a CML implementation. Supply regulation, applied as part of the calibration loop, mitigates the sensitivity to inverter delay and edge-rate over the process and temperature variations. This design, benefiting from its mostly-digital structure, adopts “sea of gates” layout style with optimized via patterns and uniform metal tracks, which effectively alleviate the significant parasitic resistance variations on low level metals fabricated by multiple patterning in 7nm FinFET.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"28 1","pages":"390-392"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78002700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310376
M. Ding, Xiaoyang Wang, P. Zhang, Yuming He, Stefano Traferro, K. Shibata, Minyoung Song, Hannu Korpela, Keisuke Ueda, Yao-Hong Liu, Christian Bachmann, K. Philips
This paper presents a low-voltage (0.8V) ultra-low-power Bluetooth 5(BT5)/Bluetooth Low Energy(BLE) digitally-intensive transceiver for IoT applications. In comparison to BLE, BT5 has a 2x higher data-rate and 4x longer range, while having >8x longer packet. The BLE prior arts [1-5] have made significant efforts to minimize the power consumption for longer battery life, as well as the chip area. However, the prior-art Cartesian BLE radios consume namely 6 to 10mW [1-3] to achieve a <-94dBm sensitivity but with a relatively high supply voltage (VDD) (>1.0V). Operating a BLE RF transceiver at a lower VDD (e.g., <0.85V) not only extends the battery life by up to 50% [3], and reduces the Power-Management-Unit complexity, but also can accommodate a wider range of energy sources (e.g., harvesters). A recent single-channel phase-tracking RX [5] demonstrated a potential to reduce the chip area and the power consumption at a VDD down to 0.85V. However, it suffers from a degraded sensitivity due to a poor deviation frequency control and an excessive loop delay, limited ACR (Adjacent-Channel-Rejection) due to the digitally-controlled-oscillator (DCO) side-lobe energy, and an undefined initial carrier frequency due to the lack of a PLL/FLL that could have a risk of tracking to an interference. This work presents a fully-integrated 0.8V phase-domain BT5/BLE-combo transceiver, including a PHY-layer digital baseband (DBB), and addresses the above-mentioned issues by employing two key techniques: 1) a hybrid loop filter with a loop-delay compensation for DCO side-lobe suppression to enhance interference tolerance, and 2) an all-digital PLL(ADPLL)-based digital FM interface shared between RX and TX is employed, including a deviation frequency calibration, and it also precisely defines the initial frequency. Moreover, the PHY-layer DBB that supports a packet-mode phase-tracking RX operation is also demonstrated.
{"title":"A 0.8V 0.8mm2 bluetooth 5/BLE digital-intensive transceiver with a 2.3mW phase-tracking RX utilizing a hybrid loop filter for interference resilience in 40nm CMOS","authors":"M. Ding, Xiaoyang Wang, P. Zhang, Yuming He, Stefano Traferro, K. Shibata, Minyoung Song, Hannu Korpela, Keisuke Ueda, Yao-Hong Liu, Christian Bachmann, K. Philips","doi":"10.1109/ISSCC.2018.8310376","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310376","url":null,"abstract":"This paper presents a low-voltage (0.8V) ultra-low-power Bluetooth 5(BT5)/Bluetooth Low Energy(BLE) digitally-intensive transceiver for IoT applications. In comparison to BLE, BT5 has a 2x higher data-rate and 4x longer range, while having >8x longer packet. The BLE prior arts [1-5] have made significant efforts to minimize the power consumption for longer battery life, as well as the chip area. However, the prior-art Cartesian BLE radios consume namely 6 to 10mW [1-3] to achieve a <-94dBm sensitivity but with a relatively high supply voltage (VDD) (>1.0V). Operating a BLE RF transceiver at a lower VDD (e.g., <0.85V) not only extends the battery life by up to 50% [3], and reduces the Power-Management-Unit complexity, but also can accommodate a wider range of energy sources (e.g., harvesters). A recent single-channel phase-tracking RX [5] demonstrated a potential to reduce the chip area and the power consumption at a VDD down to 0.85V. However, it suffers from a degraded sensitivity due to a poor deviation frequency control and an excessive loop delay, limited ACR (Adjacent-Channel-Rejection) due to the digitally-controlled-oscillator (DCO) side-lobe energy, and an undefined initial carrier frequency due to the lack of a PLL/FLL that could have a risk of tracking to an interference. This work presents a fully-integrated 0.8V phase-domain BT5/BLE-combo transceiver, including a PHY-layer digital baseband (DBB), and addresses the above-mentioned issues by employing two key techniques: 1) a hybrid loop filter with a loop-delay compensation for DCO side-lobe suppression to enhance interference tolerance, and 2) an all-digital PLL(ADPLL)-based digital FM interface shared between RX and TX is employed, including a deviation frequency calibration, and it also precisely defines the initial frequency. Moreover, the PHY-layer DBB that supports a packet-mode phase-tracking RX operation is also demonstrated.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"217 1","pages":"446-448"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76061763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.
{"title":"A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference","authors":"Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, R. Staszewski","doi":"10.1109/ISSCC.2018.8310377","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310377","url":null,"abstract":"The current paradigm of frequency synthesis for short-range wireless transceivers, such as BLE, is to use a crystal oscillator (XO) in the tens-of-MHz range as a frequency reference (FREF) to phase lock an RF oscillator [1-4]. This ensures a sufficiently wide PLL bandwidth of tens to hundreds of kHz to quickly acquire a new channel and to suppress lower-frequency phase noise (PN) of the RF oscillator. The latter requirement can be alleviated by substantially lowering the flicker PN of a digitally controlled oscillator (DCO) thus allowing to freeze its tuning word updates during receive (RX) packets and further directly FM-modulating the DCO during transmit (TX) packets [1]. However, an all-digital PLL (ADPLL) is still needed just to quickly settle the DCO to each new channel.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"30 1","pages":"448-450"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79645696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310227
Yifeng Cai, Y. Manoli
Harvesting energy from ambient vibrations with piezoelectric transducers is an alternative solution for the surging needs of self-powered devices, such as IoT devices, condition and structural monitoring devices, or biomedical implants. A limiting factor for piezoelectric transducer is the narrow bandwidth due to the high mechanical quality factor. Therefore, the output power drops significantly when the excitation frequency deviates from the resonant frequency in a real environment. One solution is to introduce time delays into active harvesting-interface concepts such as Synchronous Electric-Charge Extraction (SECE) or Synchronized Switch Harvesting on Inductor (SSHI). This emulates conjugate impedance, which matches that of the transducer, resulting in higher power from vibrations at non-resonant frequencies.
{"title":"A piezoelectric energy-harvesting interface circuit with fully autonomous conjugate impedance matching, 156% extended bandwidth, and 0.38μW power consumption","authors":"Yifeng Cai, Y. Manoli","doi":"10.1109/ISSCC.2018.8310227","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310227","url":null,"abstract":"Harvesting energy from ambient vibrations with piezoelectric transducers is an alternative solution for the surging needs of self-powered devices, such as IoT devices, condition and structural monitoring devices, or biomedical implants. A limiting factor for piezoelectric transducer is the narrow bandwidth due to the high mechanical quality factor. Therefore, the output power drops significantly when the excitation frequency deviates from the resonant frequency in a real environment. One solution is to introduce time delays into active harvesting-interface concepts such as Synchronous Electric-Charge Extraction (SECE) or Synchronized Switch Harvesting on Inductor (SSHI). This emulates conjugate impedance, which matches that of the transducer, resulting in higher power from vibrations at non-resonant frequencies.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"76 1","pages":"148-150"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83221528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310244
Jae-Sung An, Sang-Hyun Han, Kyeong-Bin Park, Ju Eon Kim, J. Ye, Seung-Hwan Lee, Ji-Yong Jeong, Jung Soo Kim, K. Baek, Ki-Seok Chung, Seongkwan Hong, O. Kwon
There have been many recent advances in capacitive touch systems (CTSs) [1-5]. Multiple-way interactive CTSs (MI-CTSs) that can simultaneously communicate with each other on a real-time basis have been demanded; however, such MI-CTSs have not yet been reported. In addition, palm rejection in an active stylus would be a very useful feature for when the palm inevitably touches a touch screen panel (TSP) [5]. In this paper, an MI-CTS with the palm rejection for an active stylus is reported. This allows simultaneous interaction between CTSs on a real-time basis, while lessening the computational load.
{"title":"Multi-way interactive capacitive touch system with palm rejection of active stylus for 86” touch screen panels","authors":"Jae-Sung An, Sang-Hyun Han, Kyeong-Bin Park, Ju Eon Kim, J. Ye, Seung-Hwan Lee, Ji-Yong Jeong, Jung Soo Kim, K. Baek, Ki-Seok Chung, Seongkwan Hong, O. Kwon","doi":"10.1109/ISSCC.2018.8310244","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310244","url":null,"abstract":"There have been many recent advances in capacitive touch systems (CTSs) [1-5]. Multiple-way interactive CTSs (MI-CTSs) that can simultaneously communicate with each other on a real-time basis have been demanded; however, such MI-CTSs have not yet been reported. In addition, palm rejection in an active stylus would be a very useful feature for when the palm inevitably touches a touch screen panel (TSP) [5]. In this paper, an MI-CTS with the palm rejection for an active stylus is reported. This allows simultaneous interaction between CTSs on a real-time basis, while lessening the computational load.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"69 9 1","pages":"182-184"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83426718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310279
L. Bertulessi, Luigi Grimaldi, Dmytro Cherniak, C. Samori, S. Levantino
Digital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed.
{"title":"A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range","authors":"L. Bertulessi, Luigi Grimaldi, Dmytro Cherniak, C. Samori, S. Levantino","doi":"10.1109/ISSCC.2018.8310279","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310279","url":null,"abstract":"Digital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"2 1","pages":"252-254"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89363323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310402
Xiang Gao
PLLs and frequency synthesizers are key building blocks in wireless transceivers. With the trend of higher data-rate, higher carrier frequency and higher order of modulation, the jitter or phase noise requirement becomes more demanding given a limited power budget. This tutorial starts from the fundamentals of PLL jitter and power consumption. Various sources of PLL jitter and power will be identified and analyzed, and design methodologies to optimize them on both the block and system level will be presented. Finally, the working principle and recent advances of the low jitter sub-sampling PLL architecture will be discussed.
{"title":"Tutorials: Low-Jitter PLLs for wireless transceivers","authors":"Xiang Gao","doi":"10.1109/ISSCC.2018.8310402","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310402","url":null,"abstract":"PLLs and frequency synthesizers are key building blocks in wireless transceivers. With the trend of higher data-rate, higher carrier frequency and higher order of modulation, the jitter or phase noise requirement becomes more demanding given a limited power budget. This tutorial starts from the fundamentals of PLL jitter and power consumption. Various sources of PLL jitter and power will be identified and analyzed, and design methodologies to optimize them on both the block and system level will be presented. Finally, the working principle and recent advances of the low jitter sub-sampling PLL architecture will be discussed.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"13 1","pages":"499-501"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90609603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310295
Ali Fazli Yeknami, Xiaoyang Wang, Somayeh Imani, Ali Nikoofard, Itthipon Jeerapan, Joseph Wang, P. Mercier
Wearable physiochemical biosensors offer an exciting opportunity to monitor the concentration of ions and metabolites in bodily fluids such as sweat, saliva, and interstitial fluids for emerging applications in health and fitness monitoring [1]. However, current physiochemical sensing prototypes rely on batteries and DC-DC converters to provide power for instrumentation, which may result in a large, obtrusive form factor with limited lifetime [1]. This paper presents a wireless physiochemical sensing system capable of monitoring glucose or lactate when powered via an enzymatic biofuel cell (BFC) based on energy naturally present in the underlying analytes to be sensed. Unlike prior-art BFC harvesters, which utilize bulky boost converters to increase the 0.3-to-0.4V BFC voltage to a higher level suitable for conventional CMOS circuits [2], this work forgoes any DC-DC converter, and instead the entire system, including a ΔΣ ADC and 920mHz RF transmitter, is designed to operate directly from the dynamic 0.3-to-0.4V BFC output.
{"title":"A 0.3V biofuel-cell-powered glucose/lactate biosensing system employing a 180nW 64dB SNR passive δς ADC and a 920MHz wireless transmitter","authors":"Ali Fazli Yeknami, Xiaoyang Wang, Somayeh Imani, Ali Nikoofard, Itthipon Jeerapan, Joseph Wang, P. Mercier","doi":"10.1109/ISSCC.2018.8310295","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310295","url":null,"abstract":"Wearable physiochemical biosensors offer an exciting opportunity to monitor the concentration of ions and metabolites in bodily fluids such as sweat, saliva, and interstitial fluids for emerging applications in health and fitness monitoring [1]. However, current physiochemical sensing prototypes rely on batteries and DC-DC converters to provide power for instrumentation, which may result in a large, obtrusive form factor with limited lifetime [1]. This paper presents a wireless physiochemical sensing system capable of monitoring glucose or lactate when powered via an enzymatic biofuel cell (BFC) based on energy naturally present in the underlying analytes to be sensed. Unlike prior-art BFC harvesters, which utilize bulky boost converters to increase the 0.3-to-0.4V BFC voltage to a higher level suitable for conventional CMOS circuits [2], this work forgoes any DC-DC converter, and instead the entire system, including a ΔΣ ADC and 920mHz RF transmitter, is designed to operate directly from the dynamic 0.3-to-0.4V BFC output.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"104 1","pages":"284-286"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80669072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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