Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310380
Angad S. Rekhi, A. Arbabian
The next generation of the Internet of Things is envisioned to include unobtrusive, distributed mm-sized nodes capable of sensing and communicating information about their surroundings. Wake-up receivers (WuRXs) — ultra-low-power receivers that monitor their environment for a wake-up signature — are an important part of this vision, as they can extend the lifetime of a wireless node by keeping it asleep until interrogated. The state of the art in WuRXs, measured in terms of sensitivity and power, has recently been advanced by streamlining the signal path to include fewer power-hungry gain stages and instead obtaining the gain at the chip-antenna interface [1,2]. This has led to excellent power-sensitivity performance, but the accompanying increase in size hampers the applicability of these techniques in size-conscious applications, such as surveillance, asset tracking, and ubiquitous sensing. Moreover, size-reduction methods based on RF antenna miniaturization are fundamentally limited by high antenna Qs at low size-to-wavelength ratios [3]; efficiently matching to these antennas requires, in turn, high-Q passives that are generally unavailable at mm-scale.
{"title":"A 14.5mm2 8nW −59.7dBm-sensitivity ultrasonic wake-up receiver for power-, area-, and interference-constrained applications","authors":"Angad S. Rekhi, A. Arbabian","doi":"10.1109/ISSCC.2018.8310380","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310380","url":null,"abstract":"The next generation of the Internet of Things is envisioned to include unobtrusive, distributed mm-sized nodes capable of sensing and communicating information about their surroundings. Wake-up receivers (WuRXs) — ultra-low-power receivers that monitor their environment for a wake-up signature — are an important part of this vision, as they can extend the lifetime of a wireless node by keeping it asleep until interrogated. The state of the art in WuRXs, measured in terms of sensitivity and power, has recently been advanced by streamlining the signal path to include fewer power-hungry gain stages and instead obtaining the gain at the chip-antenna interface [1,2]. This has led to excellent power-sensitivity performance, but the accompanying increase in size hampers the applicability of these techniques in size-conscious applications, such as surveillance, asset tracking, and ubiquitous sensing. Moreover, size-reduction methods based on RF antenna miniaturization are fundamentally limited by high antenna Qs at low size-to-wavelength ratios [3]; efficiently matching to these antennas requires, in turn, high-Q passives that are generally unavailable at mm-scale.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"44 1","pages":"454-456"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84586568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310170
S. Tam, H. Muljono, Min Huang, Sitaraman V. Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, S. Vora, Eddie Wang
SkyLake-SP (Scalable Performance), code name SKX, is the next generation Xeon® server processor fabricated on the Intel® 14nm tri-gate CMOS technology with 11-metal layers [1,2]. The SKX processor family has three core-count configurations. Each SKX core is accompanied by 1MB of dedicated L2 (2nd level cache) and 1.375MB of non-exclusive L3 (3rd level cache). At its maximum configuration of 28 cores, the SKX processor supports 6 DDR4 channels (2666MT/s), 3×20-lanes UPI processor-to-processor links (10.4GT/s) and x48+4 PCIE links (8GT/s). SKX supports per-core power-performance optimization enabled by on-die integrated voltage regulators (FIVR) [3, 4]. A new 2-dimensional synchronous on-die MESH fabric interconnects all the on-die components. Fig. 2.1.1 shows the overall architecture of the SKX processor.
{"title":"SkyLake-SP: A 14nm 28-Core xeon® processor","authors":"S. Tam, H. Muljono, Min Huang, Sitaraman V. Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, S. Vora, Eddie Wang","doi":"10.1109/ISSCC.2018.8310170","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310170","url":null,"abstract":"SkyLake-SP (Scalable Performance), code name SKX, is the next generation Xeon® server processor fabricated on the Intel® 14nm tri-gate CMOS technology with 11-metal layers [1,2]. The SKX processor family has three core-count configurations. Each SKX core is accompanied by 1MB of dedicated L2 (2nd level cache) and 1.375MB of non-exclusive L3 (3rd level cache). At its maximum configuration of 28 cores, the SKX processor supports 6 DDR4 channels (2666MT/s), 3×20-lanes UPI processor-to-processor links (10.4GT/s) and x48+4 PCIE links (8GT/s). SKX supports per-core power-performance optimization enabled by on-die integrated voltage regulators (FIVR) [3, 4]. A new 2-dimensional synchronous on-die MESH fabric interconnects all the on-die components. Fig. 2.1.1 shows the overall architecture of the SKX processor.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"33 1","pages":"34-36"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84626774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310340
Chee-Cheow Lim, Jun Yin, Pui-in Mak, H. Ramiah, R. Martins
Second-harmonic common-mode (CM) resonance has been explored for LC oscillators to improve their phase noise (PN) in the past. Its implementation evolves from an explicit design [1] that relies on an extra tail tank, to a recent implicit design [2], where the resonator itself offers a CM impedance peak at 2x the oscillation frequency (FLO): Explicit design (Fig. 23.5.1-upper): a high-Q tail tank (QTAIL) is desirable to raise its impedance |ZTAIL| at 2FLO and to prevent the loss of LTAIL from penalizing the PN in the 1/f2 region [3]. To compare with the theoretical limit (FOMMAX), the FOM in the 1/f2 PN region is plotted against LTAIL at different QTAIL. Closing the gap between FOMMAX and FOM imposes an excessive QTAIL of 20 or beyond, which can hardly be achieved and maintained over a wide tuning range.
{"title":"An inverse-class-F CMOS VCO with intrinsic-high-Q 1st- and 2nd-harmonic resonances for 1/f2-to-1/f3 phase-noise suppression achieving 196.2dBc/Hz FOM","authors":"Chee-Cheow Lim, Jun Yin, Pui-in Mak, H. Ramiah, R. Martins","doi":"10.1109/ISSCC.2018.8310340","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310340","url":null,"abstract":"Second-harmonic common-mode (CM) resonance has been explored for LC oscillators to improve their phase noise (PN) in the past. Its implementation evolves from an explicit design [1] that relies on an extra tail tank, to a recent implicit design [2], where the resonator itself offers a CM impedance peak at 2x the oscillation frequency (F<inf>LO</inf>): Explicit design (Fig. 23.5.1-upper): a high-Q tail tank (Q<inf>TAIL</inf>) is desirable to raise its impedance |Z<inf>TAIL</inf>| at 2FLO and to prevent the loss of L<inf>TAIL</inf> from penalizing the PN in the 1/f<sup>2</sup> region [3]. To compare with the theoretical limit (FOM<inf>MAX</inf>), the FOM in the 1/f<sup>2</sup> PN region is plotted against L<inf>TAIL</inf> at different QTAIL. Closing the gap between FOM<inf>MAX</inf> and FOM imposes an excessive Q<inf>TAIL</inf> of 20 or beyond, which can hardly be achieved and maintained over a wide tuning range.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"8 1","pages":"374-376"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82080958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310342
D. Turker, Ade Bekele, P. Upadhyaya, B. Verbruggen, Ying Cao, Shaojun Ma, C. Erdmann, B. Farley, Y. Frans, Ken Chang
Direct-RF data converters [1,2] have seen increased adoption in remote-radio-head TX and RX, due to their unparalleled bandwidth and flexibility. However, since these converters need to directly synthesize and sample multi-GHz radio signals, the sampling clock must exhibit excellent phase-noise performance, to minimize self- and adjacent-channel mixing, and strong suppression of reference and harmonic spurs, to meet stringent out-of-band emissions and minimize aliased energy. Furthermore, a wide range of sampling frequencies is required for the flexibility to cover multiple bands. Due to these stringent requirements, typically, external PLLs are employed, adding to the BOM cost. This work presents techniques for a fully integrated 7.4-to-14GHz PLL in 16nm FinFET that has 54fsrms jitter to satisfy the low noise requirements of RF data converters.
{"title":"A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs","authors":"D. Turker, Ade Bekele, P. Upadhyaya, B. Verbruggen, Ying Cao, Shaojun Ma, C. Erdmann, B. Farley, Y. Frans, Ken Chang","doi":"10.1109/ISSCC.2018.8310342","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310342","url":null,"abstract":"Direct-RF data converters [1,2] have seen increased adoption in remote-radio-head TX and RX, due to their unparalleled bandwidth and flexibility. However, since these converters need to directly synthesize and sample multi-GHz radio signals, the sampling clock must exhibit excellent phase-noise performance, to minimize self- and adjacent-channel mixing, and strong suppression of reference and harmonic spurs, to meet stringent out-of-band emissions and minimize aliased energy. Furthermore, a wide range of sampling frequencies is required for the flexibility to cover multiple bands. Due to these stringent requirements, typically, external PLLs are employed, adding to the BOM cost. This work presents techniques for a fully integrated 7.4-to-14GHz PLL in 16nm FinFET that has 54fsrms jitter to satisfy the low noise requirements of RF data converters.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"6 1","pages":"378-380"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84120457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310303
Christos Vezyrtzis, T. Strach, P. Chuang, P. Lobo, R. Rizzolo, Tobias Webel, Pawel Owczarczyk, A. Buyuktosunoglu, Ramon Bertran Monfort, D. Hui, Susan M. Eickhoff, M. Floyd, G. Salem, S. Carey, Stelios G. Tsapepas, P. Restle
Enterprise server processor designs, which operate at extreme high frequencies and power envelopes, depend critically on power supply noise mitigation techniques. With supply voltage scaling, very high current draws, and broad usage of clock gating, advanced solutions are needed for next-generation products to minimize droop mitigation response time, which can be defined as the latency from when a dangerous droop begins until a countermeasure is effective.
{"title":"Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor","authors":"Christos Vezyrtzis, T. Strach, P. Chuang, P. Lobo, R. Rizzolo, Tobias Webel, Pawel Owczarczyk, A. Buyuktosunoglu, Ramon Bertran Monfort, D. Hui, Susan M. Eickhoff, M. Floyd, G. Salem, S. Carey, Stelios G. Tsapepas, P. Restle","doi":"10.1109/ISSCC.2018.8310303","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310303","url":null,"abstract":"Enterprise server processor designs, which operate at extreme high frequencies and power envelopes, depend critically on power supply noise mitigation techniques. With supply voltage scaling, very high current draws, and broad usage of clock gating, advanced solutions are needed for next-generation products to minimize droop mitigation response time, which can be defined as the latency from when a dangerous droop begins until a countermeasure is effective.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"59 1","pages":"300-302"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83969957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Expanding signal bandwidths in high-speed links is increasing intersymbol interference (ISI), which necessitates the enhancement of spectral efficiency. Recently, various modulation schemes including pulse amplitude modulation (PAM) [1], pulsewidth modulation (PWM) [2], permutation modulation (PM) [3] and duo-binary signaling [4] have been investigated in high-speed wireline links to increase spectral efficiency. However, multi-level signaling schemes suffer from SNR reduction and tighter linearity requirements when compared to conventional NRZ signaling. In this work, a 20Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the SNR degradation without linearity requirement is presented. The FPWM scheme encodes data at the location and the width of pulses in a frame spanning multiple UIs while maintaining a minimum pulsewidth equal to 1UI. The test-chip achieves a coding gain of 33%, which allows the total throughput of 20Gb/s while keeping the baud rate of 15Gb/s. The equalization core incorporates programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver, to compensate for channel insertion loss of up to 12dB at the baud frequency. The transceiver IC is implemented in 40nm CMOS and consumes 90.6mW from a 0.9V supply.
{"title":"A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS","authors":"Sejun Jeon, Woohyun Kwon, Taehun Yoon, Jong-Hyeok Yoon, Kyeongha Kwon, Jaehyeok Yang, Hyeon-Min Bae","doi":"10.1109/ISSCC.2018.8310288","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310288","url":null,"abstract":"Expanding signal bandwidths in high-speed links is increasing intersymbol interference (ISI), which necessitates the enhancement of spectral efficiency. Recently, various modulation schemes including pulse amplitude modulation (PAM) [1], pulsewidth modulation (PWM) [2], permutation modulation (PM) [3] and duo-binary signaling [4] have been investigated in high-speed wireline links to increase spectral efficiency. However, multi-level signaling schemes suffer from SNR reduction and tighter linearity requirements when compared to conventional NRZ signaling. In this work, a 20Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the SNR degradation without linearity requirement is presented. The FPWM scheme encodes data at the location and the width of pulses in a frame spanning multiple UIs while maintaining a minimum pulsewidth equal to 1UI. The test-chip achieves a coding gain of 33%, which allows the total throughput of 20Gb/s while keeping the baud rate of 15Gb/s. The equalization core incorporates programmable 3-tap pre-emphasis at the transmitter and a continuous-time linear equalizer (CTLE) at the receiver, to compensate for channel insertion loss of up to 12dB at the baud frequency. The transceiver IC is implemented in 40nm CMOS and consumes 90.6mW from a 0.9V supply.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"38 1","pages":"270-272"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82415516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310415
D. Friedman
Advances in artificial intelligence are already changing how computing systems interact with users and interact with their environments, with further dramatic changes on the horizon. In this context, machine learning and inference operations have become a critically important computational workload, and the importance of this workload will continue to increase. Today, GPU-, CPU-, and FPGA-based engines dominate the compute landscape for learning and for inference, but the exploration of alternative, enhanced, or complementary compute capability in this problem space is an active and growing research area. In this short course, we will provide a framework for understanding some of the computational challenges in machine learning and inference and discuss emerging technical approaches aimed at meeting those challenges.
{"title":"SC: Hardware approaches to machine learning and inference","authors":"D. Friedman","doi":"10.1109/ISSCC.2018.8310415","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310415","url":null,"abstract":"Advances in artificial intelligence are already changing how computing systems interact with users and interact with their environments, with further dramatic changes on the horizon. In this context, machine learning and inference operations have become a critically important computational workload, and the importance of this workload will continue to increase. Today, GPU-, CPU-, and FPGA-based engines dominate the compute landscape for learning and for inference, but the exploration of alternative, enhanced, or complementary compute capability in this problem space is an active and growing research area. In this short course, we will provide a framework for understanding some of the computational challenges in machine learning and inference and discuss emerging technical approaches aimed at meeting those challenges.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"19 1","pages":"533-534"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80987781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310319
Z. Cai, R. V. Veldhoven, H. Suy, G. D. Graaf, K. Makinwa, M. Pertijs
The measurement of carbon-dioxide (CO2) concentration is very important in home and building automation, e.g. to control ventilation in energy-efficient buildings. This application requires compact, low-cost sensors that can measure CO2 concentration with a resolution of <200 ppm over a 2500ppm range. Conventional optical (NDIR-based) CO2 sensors require components that are CMOS-incompatible, difficult to miniaturize and power-hungry [1]. Due to their CMOS compatibility, thermal-conductivity-based sensors are an attractive alternative [2,3]. They exploit the fact that the thermal conductivity (TC) of CO2 is lower than that of the other constituents of air, so that CO2 concentration can be indirectly measured via the heat loss of a hot wire to ambient. However, this approach requires the detection of very small changes in TC (0.25 ppm per ppm CO2 [3]).
二氧化碳(CO2)浓度的测量在家庭和建筑自动化中非常重要，例如在节能建筑中控制通风。这种应用需要紧凑，低成本的传感器，可以在2500ppm范围内以< 200ppm的分辨率测量二氧化碳浓度。传统的光学(基于ndir的)CO2传感器需要的组件与cmos不兼容，难以小型化并且耗电[1]。由于其CMOS兼容性，基于热导率的传感器是一个有吸引力的替代方案[2,3]。他们利用二氧化碳的热导率(TC)低于空气中其他成分的事实，因此可以通过热丝向环境的热损失间接测量二氧化碳浓度。然而，这种方法需要检测非常小的TC变化(每ppm CO2 0.25 ppm)[3]。
{"title":"A phase-domain readout circuit for a CMOS-compatible thermal-conductivity-based carbon dioxide sensor","authors":"Z. Cai, R. V. Veldhoven, H. Suy, G. D. Graaf, K. Makinwa, M. Pertijs","doi":"10.1109/ISSCC.2018.8310319","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310319","url":null,"abstract":"The measurement of carbon-dioxide (CO2) concentration is very important in home and building automation, e.g. to control ventilation in energy-efficient buildings. This application requires compact, low-cost sensors that can measure CO2 concentration with a resolution of <200 ppm over a 2500ppm range. Conventional optical (NDIR-based) CO2 sensors require components that are CMOS-incompatible, difficult to miniaturize and power-hungry [1]. Due to their CMOS compatibility, thermal-conductivity-based sensors are an attractive alternative [2,3]. They exploit the fact that the thermal conductivity (TC) of CO2 is lower than that of the other constituents of air, so that CO2 concentration can be indirectly measured via the heat loss of a hot wire to ambient. However, this approach requires the detection of very small changes in TC (0.25 ppm per ppm CO2 [3]).","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"59 1","pages":"332-334"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78717573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310301
Gerard O’Leary, Mohammad Reza Pazhouhandeh, Michael Chang, David M. Groppe, T. Valiante, N. Verma, R. Genov
The advancement of closed-loop neuromodulation for treating neurological disorders demands: (1) analog circuits monitoring the brain activity uninterruptedly even during neurostimulation, (2) energy-efficient high-efficacy processors for responsive, adaptive, personalized neurostimulation, and (3) safe neurostimulation paradigms with rich spatio-temporal stimuli for controlling the brain's complex dynamics. This paper presents an implantable neural interface processor (NURIP) that addresses these requirements — it performs brain state classification for reliable seizure prediction and contingent seizure abortion.
{"title":"A recursive-memory brain-state classifier with 32-channel track-and-zoom Δ2 Σ ADCs and Charge-Balanced Programmable Waveform Neurostimulators","authors":"Gerard O’Leary, Mohammad Reza Pazhouhandeh, Michael Chang, David M. Groppe, T. Valiante, N. Verma, R. Genov","doi":"10.1109/ISSCC.2018.8310301","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310301","url":null,"abstract":"The advancement of closed-loop neuromodulation for treating neurological disorders demands: (1) analog circuits monitoring the brain activity uninterruptedly even during neurostimulation, (2) energy-efficient high-efficacy processors for responsive, adaptive, personalized neurostimulation, and (3) safe neurostimulation paradigms with rich spatio-temporal stimuli for controlling the brain's complex dynamics. This paper presents an implantable neural interface processor (NURIP) that addresses these requirements — it performs brain state classification for reliable seizure prediction and contingent seizure abortion.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"32 1","pages":"296-298"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91254292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310258
Kyu-Dong Hwang, Boram Kim, Sangyeon Byeon, Kyu-Young Kim, Daehan Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-young Jang, Seung-Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, J. Chun, Jonghoon Oh, Jinkook Kim, S. Lee
Recently the demand for high-bandwidth graphic DRAM, for game consoles and graphic cards, has dramatically increased due to the development of virtual reality, artificial intelligence, deep learning, autonomous driving cars, etc. These applications require greater data transfer speeds than pervious devices, GDDR5 [1] and GDDR5X [2], which are limited to 12Gb/s/pin. This paper introduces an 8Gb GDDR6 operating at up to 16Gb/s/pin. To exceed the prior speed limit various bandwidth extension techniques are proposed. WCK is driven with a dividing scheme to overcome speed limitations and to reduce power consumption. In addition, a dual-band architecture with different types of nibble drivers is proposed in order to cover stability of CML-to-CMOS in all frequency regions; CML nibble is used for high-speed, while CMOS nibble is used for low-speed. A DC-split scheme is implemented for duty-cycle correction and skew compensation. The bandwidth of the high-frequency divider is extended by using a proposed mode-changed flip-flop. The receiver uses a loop-unrolled one-tap decision-feedback equalizer (DFE) designed to eliminate channel inter-symbol interference (ISI). A two-stage pre-amplifier is also used for bandwidth extension. The transmitter uses a 4:1 multiplexer using a half-rate sampler, where a 1UI pulse is unnecessary to minimize the full-rate operation. To secure on-chip signal transmission characteristic, the bandwidth limitation of transistor in a DRAM process is extended by adopting an on-chip feedback EQ filter.
{"title":"A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications","authors":"Kyu-Dong Hwang, Boram Kim, Sangyeon Byeon, Kyu-Young Kim, Daehan Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-young Jang, Seung-Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, J. Chun, Jonghoon Oh, Jinkook Kim, S. Lee","doi":"10.1109/ISSCC.2018.8310258","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310258","url":null,"abstract":"Recently the demand for high-bandwidth graphic DRAM, for game consoles and graphic cards, has dramatically increased due to the development of virtual reality, artificial intelligence, deep learning, autonomous driving cars, etc. These applications require greater data transfer speeds than pervious devices, GDDR5 [1] and GDDR5X [2], which are limited to 12Gb/s/pin. This paper introduces an 8Gb GDDR6 operating at up to 16Gb/s/pin. To exceed the prior speed limit various bandwidth extension techniques are proposed. WCK is driven with a dividing scheme to overcome speed limitations and to reduce power consumption. In addition, a dual-band architecture with different types of nibble drivers is proposed in order to cover stability of CML-to-CMOS in all frequency regions; CML nibble is used for high-speed, while CMOS nibble is used for low-speed. A DC-split scheme is implemented for duty-cycle correction and skew compensation. The bandwidth of the high-frequency divider is extended by using a proposed mode-changed flip-flop. The receiver uses a loop-unrolled one-tap decision-feedback equalizer (DFE) designed to eliminate channel inter-symbol interference (ISI). A two-stage pre-amplifier is also used for bandwidth extension. The transmitter uses a 4:1 multiplexer using a half-rate sampler, where a 1UI pulse is unnecessary to minimize the full-rate operation. To secure on-chip signal transmission characteristic, the bandwidth limitation of transistor in a DRAM process is extended by adopting an on-chip feedback EQ filter.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"240 1","pages":"210-212"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86700642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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