Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310372
Moataz Abdelfattah, M. Swilam, B. Dupaix, D. Smith, A. Fayed, W. Khalil
Near-threshold computing (NTC) is a promising approach to address the increasing demand for energy efficiency in computing platforms. In NTC, the supply voltage is scaled down to realize quadratic energy savings while degrading the operating frequency only linearly, which can be compensated by using many-core architectures. However, practical implementation of many-core NTC systems requires a large number of on-chip DC-DC converters to provide each core with independent voltages and fast dynamic voltage scaling at a reduced cost. Moreover, these converters must support heavy loads (a few hundreds of milliamps) to supply the current required per core, or cluster of cores, while occupying minimal area (i.e. high current density) and achieving high power-conversion efficiency at low output voltages.
{"title":"An on-chip resonant-gate-drive switched-capacitor converter for near-threshold computing achieving 70.2% efficiency at 0.92A/mm2 current density and 0.4V output","authors":"Moataz Abdelfattah, M. Swilam, B. Dupaix, D. Smith, A. Fayed, W. Khalil","doi":"10.1109/ISSCC.2018.8310372","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310372","url":null,"abstract":"Near-threshold computing (NTC) is a promising approach to address the increasing demand for energy efficiency in computing platforms. In NTC, the supply voltage is scaled down to realize quadratic energy savings while degrading the operating frequency only linearly, which can be compensated by using many-core architectures. However, practical implementation of many-core NTC systems requires a large number of on-chip DC-DC converters to provide each core with independent voltages and fast dynamic voltage scaling at a reduced cost. Moreover, these converters must support heavy loads (a few hundreds of milliamps) to supply the current required per core, or cluster of cores, while occupying minimal area (i.e. high current density) and achieving high power-conversion efficiency at low output voltages.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"30 1","pages":"438-440"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89943981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310297
Maged ElAnsary, N. Soltani, Hossein Kassiri, Ruben Machado, Suzie Dufour, P. Carlen, M. Thompson, R. Genov
Potassium (K+) and sodium (Na+) ions are the main signal carriers in the nervous system. The difference in the concentration of both K+ and Na+ across the neuron cell membrane, as regulated by respective ion channels, plays a critical role in the propagation of action potentials, the spike-like signals neurons communicate with, as shown in Fig. 17.5.1 (top, left and middle). Due to their significant role in neuronal signaling, K+ channel malfunctions are linked to over 100 neurological disorders, such as schizophrenia, Alzheimer's disease, spreading depression, and epilepsy. Selective real-time sensing of K+ concentration (denoted as [K+]) is therefore critical for the advancement of many neurological therapies.
{"title":"50nW 5kHz-BW opamp-less ΔΣ impedance analyzer for brain neurochemistry monitoring","authors":"Maged ElAnsary, N. Soltani, Hossein Kassiri, Ruben Machado, Suzie Dufour, P. Carlen, M. Thompson, R. Genov","doi":"10.1109/ISSCC.2018.8310297","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310297","url":null,"abstract":"Potassium (K+) and sodium (Na+) ions are the main signal carriers in the nervous system. The difference in the concentration of both K+ and Na+ across the neuron cell membrane, as regulated by respective ion channels, plays a critical role in the propagation of action potentials, the spike-like signals neurons communicate with, as shown in Fig. 17.5.1 (top, left and middle). Due to their significant role in neuronal signaling, K+ channel malfunctions are linked to over 100 neurological disorders, such as schizophrenia, Alzheimer's disease, spreading depression, and epilepsy. Selective real-time sensing of K+ concentration (denoted as [K+]) is therefore critical for the advancement of many neurological therapies.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"15 1","pages":"288-290"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81665977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310384
Daniel DeDorigo, C. Moranz, Hagen Graf, M. Marx, Boyu Shui, M. Kuhl, Y. Manoli
The evolution of tissue-penetrating probes for high-density deep-brain recording of in vivo neural activity is limited by the level of electronic integration on the probe shaft. As the number of electrodes increases, conventional devices need either a large number of interconnects at the base of the probe or allow only a reduced number of electrodes to be read out simultaneously [1,2]. Active probes are used to improve the signal quality and reduce parasitic effects in situ, but still need to route these signals from the electrodes to a base where the readout electronics is located on a large area [3,4]. In this work, we present a modular and scalable architecture of a needle probe, which, instead of routing or prebuffering noise-sensitive analog signals along the shaft, integrates analog-to-digital conversion under each electrode in an area of 70×70μm2. The design eliminates the need for any additional readout circuitry at the top of the probe and connects with a digital 4-wire interface. The presented reconfigurable 11.5mm probe features a constant width of 70μm and thickness of 50μm from top to bottom for minimal tissue damage with 144 integrated recording sites and can be fully immersed in tissue for deep-brain recording applications.
{"title":"A fully immersible deep-brain neural probe with modular architecture and a delta-sigma ADC integrated under each electrode for parallel readout of 144 recording sites","authors":"Daniel DeDorigo, C. Moranz, Hagen Graf, M. Marx, Boyu Shui, M. Kuhl, Y. Manoli","doi":"10.1109/ISSCC.2018.8310384","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310384","url":null,"abstract":"The evolution of tissue-penetrating probes for high-density deep-brain recording of in vivo neural activity is limited by the level of electronic integration on the probe shaft. As the number of electrodes increases, conventional devices need either a large number of interconnects at the base of the probe or allow only a reduced number of electrodes to be read out simultaneously [1,2]. Active probes are used to improve the signal quality and reduce parasitic effects in situ, but still need to route these signals from the electrodes to a base where the readout electronics is located on a large area [3,4]. In this work, we present a modular and scalable architecture of a needle probe, which, instead of routing or prebuffering noise-sensitive analog signals along the shaft, integrates analog-to-digital conversion under each electrode in an area of 70×70μm2. The design eliminates the need for any additional readout circuitry at the top of the probe and connects with a digital 4-wire interface. The presented reconfigurable 11.5mm probe features a constant width of 70μm and thickness of 50μm from top to bottom for minimal tissue damage with 144 integrated recording sites and can be fully immersed in tissue for deep-brain recording applications.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"170 1","pages":"462-464"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72751108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310294
Jaeeun Jang, Jihee Lee, Kyoung-Rog Lee, Jiwon Lee, Minseo Kim, Yongsu Lee, Joonsung Bae, H. Yoo
Recently, capsule endoscopes are emerging as an alternative to the cable-attached endoscopes since not only mitigating pain and fear of patients but also acquiring additional information about unexplained lesions for accurate diagnoses. Nevertheless, their applicability has been mainly limited by insufficient viewing angles and image qualities [1]. Especially, a single end-facing camera with VGA resolution images suffers from blurred and blind zone through digestive canal, increasing its overall miss-rate up to 20%, which is fatal in diagnosis [2]. A 4-camera capsule was proposed to support 360°-visual angle [1], however, full 360° images were just stored on a Flash EPROM without wireless image transmission, real-time image viewing and capsule tracking. Full 360° high resolution images with multi-cameras inherently require high data-rate wireless telemetry inside the capsule, but previous wireless capsule endoscopes [3] did not support wireless transmission of panoramic view images because of their limited bandwidth with the coin battery.
{"title":"4-Camera VGA-resolution capsule endoscope with 80Mb/s body-channel communication transceiver and Sub-cm range capsule localization","authors":"Jaeeun Jang, Jihee Lee, Kyoung-Rog Lee, Jiwon Lee, Minseo Kim, Yongsu Lee, Joonsung Bae, H. Yoo","doi":"10.1109/ISSCC.2018.8310294","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310294","url":null,"abstract":"Recently, capsule endoscopes are emerging as an alternative to the cable-attached endoscopes since not only mitigating pain and fear of patients but also acquiring additional information about unexplained lesions for accurate diagnoses. Nevertheless, their applicability has been mainly limited by insufficient viewing angles and image qualities [1]. Especially, a single end-facing camera with VGA resolution images suffers from blurred and blind zone through digestive canal, increasing its overall miss-rate up to 20%, which is fatal in diagnosis [2]. A 4-camera capsule was proposed to support 360°-visual angle [1], however, full 360° images were just stored on a Flash EPROM without wireless image transmission, real-time image viewing and capsule tracking. Full 360° high resolution images with multi-cameras inherently require high data-rate wireless telemetry inside the capsule, but previous wireless capsule endoscopes [3] did not support wireless transmission of panoramic view images because of their limited bandwidth with the coin battery.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"1 1","pages":"282-284"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75654108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310337
Farshad Piri, M. Bassi, Niccolo Lacaita, A. Mazzanti, F. Svelto
The development of next-generation 5G networks is ongoing. The large available bandwidth at mm-waves allows increasing channel capacity well beyond the levels offered by LTE. Wide ranges of spectra, with sub-bands centered at 28GHz, 37GHz, and 39GHz, have been appointed for 5G development to facilitate international roaming and intra-networks connections [1]. In this scenario, generation of ultra-low phase-noise quadrature (IQ) signals with >40dB image rejection ratio (IRR) over >40% fractional bandwidth is key to efficiently deliver extreme data-rates through high-order spectrally efficient modulations. Quadrature voltage-controlled oscillators are disregarded because of their limited tuning range and also due to a severe trade-off between phase noise and phase accuracy. Solutions leveraging single-phase VCOs followed by quadrature generators is seen as a better strategy. Still, the challenging phase noise, required to support higher-order modulations trading-off with tuning range, mandates at least two VCOs covering half bandwidth each. For quadrature generation, distributed couplers, e.g., Lange couplers, are bulky and not amenable to integration. Hybrid couplers based on coupled inductors offer a compact footprint with low loss, but they are disregarded, because a few percent variation in the coupling coefficient, k, leads to unacceptable phase deviations. Polyphase filters (PPFs) and their improvements are widely adopted at RF [2]. In [3], the PPF operation at mm-waves is proven through careful layout techniques. Still, wideband operation can be achieved only by cascading several stages, severely increasing signal loss and power consumption.
{"title":"A >40dB IRR, 44% fractional-bandwidth ultra-wideband mm-wave quadrature LO generator for 5G networks in 55nm CMOS","authors":"Farshad Piri, M. Bassi, Niccolo Lacaita, A. Mazzanti, F. Svelto","doi":"10.1109/ISSCC.2018.8310337","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310337","url":null,"abstract":"The development of next-generation 5G networks is ongoing. The large available bandwidth at mm-waves allows increasing channel capacity well beyond the levels offered by LTE. Wide ranges of spectra, with sub-bands centered at 28GHz, 37GHz, and 39GHz, have been appointed for 5G development to facilitate international roaming and intra-networks connections [1]. In this scenario, generation of ultra-low phase-noise quadrature (IQ) signals with >40dB image rejection ratio (IRR) over >40% fractional bandwidth is key to efficiently deliver extreme data-rates through high-order spectrally efficient modulations. Quadrature voltage-controlled oscillators are disregarded because of their limited tuning range and also due to a severe trade-off between phase noise and phase accuracy. Solutions leveraging single-phase VCOs followed by quadrature generators is seen as a better strategy. Still, the challenging phase noise, required to support higher-order modulations trading-off with tuning range, mandates at least two VCOs covering half bandwidth each. For quadrature generation, distributed couplers, e.g., Lange couplers, are bulky and not amenable to integration. Hybrid couplers based on coupled inductors offer a compact footprint with low loss, but they are disregarded, because a few percent variation in the coupling coefficient, k, leads to unacceptable phase deviations. Polyphase filters (PPFs) and their improvements are widely adopted at RF [2]. In [3], the PPF operation at mm-waves is proven through careful layout techniques. Still, wideband operation can be achieved only by cascading several stages, severely increasing signal loss and power consumption.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"22 1","pages":"368-370"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86610714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310256
K. Chun, Yonggyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soo-Won Kim, Hui-Kap Yang, Mijo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, S. Cha, Hyung-Jin Kim, Young-Sik Kim, Kyung-Soo Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, I. Moon, Young-Ju Kim, Junha Lee, Young-Ryeol Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, W. Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, H. Shin, Hangyun Jung, Sanghyuk Kwon, K. Kang, Jongmyung Lee, Y. Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, S. Hyun, Seung-Bum Ko, J. Choi, Y. Sohn, Kwang-il Park, Seong-Jin Jang
High-density and high-speed DRAM requirements have been ever-increasing to achieve a better user experience for mobile systems, by adopting QHD (2560×1440), and higher display resolutions, dual cameras, augmented reality, and advanced driver-assistance systems. LPDDR4X has been the hand-held and mobile memory of choice due to its high speed (5.0Gb/s/pin [1]) and low-power data retention (<0.1mW/Gb [2-3]), as well as reliability due to in-DRAM ECC. The DRAM process continues to scale down to the 10nm era to meet the ever increasing density requirements (LPDDR4X density doubles every two years for flagship smart-phones). However, poor data retention characteristics due to smaller storage capacitances and device issues, such as reliability (NBTI) and leakage (especially core transistors), with the traditional poly-gate and planarbulk technology becomes a primary concern for mobile DRAM. In-DRAM ECC is fully supported by the JEDEC LPDDR4 specification by the introduction of the new masked-write command (MWR; fCCDMW=32fCK), however the area overhead (6.25%), due to the additional parity arrays for a (136, 128) single-error-correction code [4], is currently limiting for mass production in terms of chip cost. This overhead can be mitigated by adopting a scaled technology node that enables a smaller chip size as well as better retention time due to ECC. This paper presents several circuit techniques to maintain LPDDR4X's high speed and low power in a 10nm class process, thereby enabling a cost-effective DRAM design with inDRAM ECC: using (1) an NBTI-tolerant circuit solution that covers whole high-speed circuit regions, (2) a sub-WL driver (SWD) PMOS GIDL-reduction technique ensures stable power recovery, (3) an adaptive IO buffer current gear-down scheme based on user-scenarios, and (4) a metastable-free DQS aligner. Figure 12.2.1 shows the top-level block diagram of the 8Gb/1channel macro, with an in-DRAM ECC using a (136, 128) single-error-correction code, similar to that of previous 20nm designs [2-4].
{"title":"A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process","authors":"K. Chun, Yonggyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soo-Won Kim, Hui-Kap Yang, Mijo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, S. Cha, Hyung-Jin Kim, Young-Sik Kim, Kyung-Soo Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, I. Moon, Young-Ju Kim, Junha Lee, Young-Ryeol Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, W. Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, H. Shin, Hangyun Jung, Sanghyuk Kwon, K. Kang, Jongmyung Lee, Y. Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, S. Hyun, Seung-Bum Ko, J. Choi, Y. Sohn, Kwang-il Park, Seong-Jin Jang","doi":"10.1109/ISSCC.2018.8310256","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310256","url":null,"abstract":"High-density and high-speed DRAM requirements have been ever-increasing to achieve a better user experience for mobile systems, by adopting QHD (2560×1440), and higher display resolutions, dual cameras, augmented reality, and advanced driver-assistance systems. LPDDR4X has been the hand-held and mobile memory of choice due to its high speed (5.0Gb/s/pin [1]) and low-power data retention (<0.1mW/Gb [2-3]), as well as reliability due to in-DRAM ECC. The DRAM process continues to scale down to the 10nm era to meet the ever increasing density requirements (LPDDR4X density doubles every two years for flagship smart-phones). However, poor data retention characteristics due to smaller storage capacitances and device issues, such as reliability (NBTI) and leakage (especially core transistors), with the traditional poly-gate and planarbulk technology becomes a primary concern for mobile DRAM. In-DRAM ECC is fully supported by the JEDEC LPDDR4 specification by the introduction of the new masked-write command (MWR; fCCDMW=32fCK), however the area overhead (6.25%), due to the additional parity arrays for a (136, 128) single-error-correction code [4], is currently limiting for mass production in terms of chip cost. This overhead can be mitigated by adopting a scaled technology node that enables a smaller chip size as well as better retention time due to ECC. This paper presents several circuit techniques to maintain LPDDR4X's high speed and low power in a 10nm class process, thereby enabling a cost-effective DRAM design with inDRAM ECC: using (1) an NBTI-tolerant circuit solution that covers whole high-speed circuit regions, (2) a sub-WL driver (SWD) PMOS GIDL-reduction technique ensures stable power recovery, (3) an adaptive IO buffer current gear-down scheme based on user-scenarios, and (4) a metastable-free DQS aligner. Figure 12.2.1 shows the top-level block diagram of the 8Gb/1channel macro, with an in-DRAM ECC using a (136, 128) single-error-correction code, similar to that of previous 20nm designs [2-4].","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"2016 1","pages":"206-208"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86667055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310178
Thije Rooijers, J. Huijsing, K. Makinwa
The readout of high impedance sensors and sampled voltage references [1] requires amplifiers with both low offset and low input current. Chopper amplifiers can achieve low offset, but the switching of their input chopper gives rise to significant input current (40 to 110pA) [2-4]. Auto-zero (AZ) amplifiers require less input switching, but exhibit more voltage noise. However, ping-pong amplifiers continuously swap two auto-zeroed input stages, leading to more switching [5,7]. In this work, an AZ stabilized topology is proposed, in which a single amplifier is always present in the signal path. Only one input switch is required, resulting in an input current of 0.6pA (max), a 66x improvement on the state-of-the art [4]. Furthermore, a digitally assisted offset-reduction scheme reduces its low-frequency (LF) noise to the theoretical V5x limit. It also achieves a state-of-the-art maximum offset of 0.6μΥ.
{"title":"A quiet digitally assisted auto-zero-stabilized voltage buffer with 0.6pA input current and offset","authors":"Thije Rooijers, J. Huijsing, K. Makinwa","doi":"10.1109/ISSCC.2018.8310178","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310178","url":null,"abstract":"The readout of high impedance sensors and sampled voltage references [1] requires amplifiers with both low offset and low input current. Chopper amplifiers can achieve low offset, but the switching of their input chopper gives rise to significant input current (40 to 110pA) [2-4]. Auto-zero (AZ) amplifiers require less input switching, but exhibit more voltage noise. However, ping-pong amplifiers continuously swap two auto-zeroed input stages, leading to more switching [5,7]. In this work, an AZ stabilized topology is proposed, in which a single amplifier is always present in the signal path. Only one input switch is required, resulting in an input current of 0.6pA (max), a 66x improvement on the state-of-the art [4]. Furthermore, a digitally assisted offset-reduction scheme reduces its low-frequency (LF) noise to the theoretical V5x limit. It also achieves a state-of-the-art maximum offset of 0.6μΥ.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"9 1","pages":"50-52"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87308956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310206
M. S. Jalali, M. H. Taghavi, A. McLaren, J. Pham, K. Farzan, D. DiClemente, Marcus van Ierssel, William Song, S. Asgaran, C. Holdenried, Saman Sadr
The scaling of CMOS technology together with continued innovations in circuit and system design techniques is fueling a rising demand for increasingly high throughput serial data interfaces. However, advances in CMOS technology have little impact on channel performance, making channel impairments a bottleneck in wireline links. Furthermore, links are typically designed to cover multiple standards and are expected to operate over a wide range of data rates, making their design challenging [1-5]. This work presents a 4-lane 1.25–28.05Gb/s transceiver in 14nm FinFet technology. We measure a bit error rate (BER) lower than 1e-15 with a channel loss of 40dB at 28.05Gb/s.
{"title":"A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support","authors":"M. S. Jalali, M. H. Taghavi, A. McLaren, J. Pham, K. Farzan, D. DiClemente, Marcus van Ierssel, William Song, S. Asgaran, C. Holdenried, Saman Sadr","doi":"10.1109/ISSCC.2018.8310206","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310206","url":null,"abstract":"The scaling of CMOS technology together with continued innovations in circuit and system design techniques is fueling a rising demand for increasingly high throughput serial data interfaces. However, advances in CMOS technology have little impact on channel performance, making channel impairments a bottleneck in wireline links. Furthermore, links are typically designed to cover multiple standards and are expected to operate over a wide range of data rates, making their design challenging [1-5]. This work presents a 4-lane 1.25–28.05Gb/s transceiver in 14nm FinFet technology. We measure a bit error rate (BER) lower than 1e-15 with a channel loss of 40dB at 28.05Gb/s.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"11 1","pages":"106-108"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88085590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310234
David J. McLaurin, K. Gard, Richard P. Schubert, M. Manglani, Haiyang Zhu, D. Alldred, Zhao Li, Steve Bal, Jianxun Fan, Oliver E. Gysel, Chris Mayer, T. Montalvo
This paper presents a 65nm 2-TX, 2-RX RF-to-bits basestation transceiver with 200MHz large-signal BW and 450MHz DPD synthesis/observation BW, and LO frequencies from 400MHz to 6GHz. For FDD operation the TRX supports a low-IF mode that meets the dynamic range requirements of GSM basestations. It provides full-band multicarrier (MC) operation in all TDD/FDD 3GPP bands for 2G/3G/4G/5G radios. The SoC includes an 8×16Gb/s SERDES interface, two receivers, two transmitters, and a digital pre-distortion (DPD) feedback RX (FBRX) (Fig. 9.3.1). The FBRX employs a “stitching” system that combines the outputs of both RX basebands to provide 450MHz of observation BW. Three PLLs provide the digital/converter/SERDES clocks, a calibration LO, and an RF LO that meets GSM TX phase-noise requirements. Digital interpolation, decimation, AGC, TX Power control, and calibrations are managed by an integrated ARM Cortex M3. Internal calibration timing is adaptable to support 3G/4G/5G subframe timing requirements. The SoC is a single-chip solution for TDD, and a two-chip set for FDD. GSM requires an external Lo for the RX. Power dissipation in the maximum BW mode (2T/2R/1FBRX, 450/200/450MHz, 0dB RF attenuation, 50% TX/RX duty cycle for TDD) is 4.1W for TDD and 6.6W for FDD.
{"title":"A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestations","authors":"David J. McLaurin, K. Gard, Richard P. Schubert, M. Manglani, Haiyang Zhu, D. Alldred, Zhao Li, Steve Bal, Jianxun Fan, Oliver E. Gysel, Chris Mayer, T. Montalvo","doi":"10.1109/ISSCC.2018.8310234","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310234","url":null,"abstract":"This paper presents a 65nm 2-TX, 2-RX RF-to-bits basestation transceiver with 200MHz large-signal BW and 450MHz DPD synthesis/observation BW, and LO frequencies from 400MHz to 6GHz. For FDD operation the TRX supports a low-IF mode that meets the dynamic range requirements of GSM basestations. It provides full-band multicarrier (MC) operation in all TDD/FDD 3GPP bands for 2G/3G/4G/5G radios. The SoC includes an 8×16Gb/s SERDES interface, two receivers, two transmitters, and a digital pre-distortion (DPD) feedback RX (FBRX) (Fig. 9.3.1). The FBRX employs a “stitching” system that combines the outputs of both RX basebands to provide 450MHz of observation BW. Three PLLs provide the digital/converter/SERDES clocks, a calibration LO, and an RF LO that meets GSM TX phase-noise requirements. Digital interpolation, decimation, AGC, TX Power control, and calibrations are managed by an integrated ARM Cortex M3. Internal calibration timing is adaptable to support 3G/4G/5G subframe timing requirements. The SoC is a single-chip solution for TDD, and a two-chip set for FDD. GSM requires an external Lo for the RX. Power dissipation in the maximum BW mode (2T/2R/1FBRX, 450/200/450MHz, 0dB RF attenuation, 50% TX/RX duty cycle for TDD) is 4.1W for TDD and 6.6W for FDD.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"34 1 1","pages":"162-164"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91270871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310305
A. Quelen, G. Pillonnet, P. Flatresse, E. Beigné
Worst-case design and post-silicon tuning are well established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations, but they suffer from extra power consumption due to overdesign [1]. Adaptive voltage scaling (AVS) [2] and body bias modulation [1] are well-known strategies to dynamically ensure that the digital core can operate at a targeted frequency, even in the presence of delay degradation due to variations. In a multiple voltage islands context, AVS requires many integrated supply generators, such as switched capacitor converters that need to be controlled accurately. Also, for fine-grained compensation, level shifters are required, impacting circuit performance. As FDSOI technology offers the ability to adjust transistor speed through high sensitivity (85mV/VBB) VTH tuning by acting on buried Nwell (NW) and Pwell (PW) voltages, back-biasing generators have been investigated [3-5]. However, they require an external controller to reach the optimal Back Bias (BB) voltages (no self-adjustment) ([3-4] and [5]), imposing a non-negligible area overhead for a sub-mm2 digital core having a narrow compensation range limited to 0.35–0.45V VDD. We therefore propose a variation-aware BB compensation unit (BBC), which dynamically self-adjusts the N- and PMOS transistors' BB voltages to maintain the target frequency with low-latency tuning (100μs) across a wide range of supply voltage (0.35–1V) and temperature (−40–125°C). The low reported area of 0.0067mm2 makes it affordable for a small digital core area (0.1–2mm2). Requiring only a reference frequency signal FTGT, the self-operating BBC exhibits 2.5μW quiescent current without any external components. Compared to a worst-case design strategy, the BBC unit brings up to 50% leakage reduction @0.45VDD, 120°C and reduces the energy per cycle up to 32% compared to worst-case design. By providing continuous BB voltage adjustment (continuous VTH tuning), the target frequency is maintained within ±3.5% accuracy.
{"title":"A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range","authors":"A. Quelen, G. Pillonnet, P. Flatresse, E. Beigné","doi":"10.1109/ISSCC.2018.8310305","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310305","url":null,"abstract":"Worst-case design and post-silicon tuning are well established digital design practices reducing timing violations in presence of process, temperature, aging and voltage variations, but they suffer from extra power consumption due to overdesign [1]. Adaptive voltage scaling (AVS) [2] and body bias modulation [1] are well-known strategies to dynamically ensure that the digital core can operate at a targeted frequency, even in the presence of delay degradation due to variations. In a multiple voltage islands context, AVS requires many integrated supply generators, such as switched capacitor converters that need to be controlled accurately. Also, for fine-grained compensation, level shifters are required, impacting circuit performance. As FDSOI technology offers the ability to adjust transistor speed through high sensitivity (85mV/VBB) VTH tuning by acting on buried Nwell (NW) and Pwell (PW) voltages, back-biasing generators have been investigated [3-5]. However, they require an external controller to reach the optimal Back Bias (BB) voltages (no self-adjustment) ([3-4] and [5]), imposing a non-negligible area overhead for a sub-mm2 digital core having a narrow compensation range limited to 0.35–0.45V VDD. We therefore propose a variation-aware BB compensation unit (BBC), which dynamically self-adjusts the N- and PMOS transistors' BB voltages to maintain the target frequency with low-latency tuning (100μs) across a wide range of supply voltage (0.35–1V) and temperature (−40–125°C). The low reported area of 0.0067mm2 makes it affordable for a small digital core area (0.1–2mm2). Requiring only a reference frequency signal FTGT, the self-operating BBC exhibits 2.5μW quiescent current without any external components. Compared to a worst-case design strategy, the BBC unit brings up to 50% leakage reduction @0.45VDD, 120°C and reduces the energy per cycle up to 32% compared to worst-case design. By providing continuous BB voltage adjustment (continuous VTH tuning), the target frequency is maintained within ±3.5% accuracy.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"29 1","pages":"304-306"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81403066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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