Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310398
Sujan Kumar Gonugondla, Mingu Kang, Naresh R Shanbhag
Embedded sensory systems (Fig. 31.2.1) continuously acquire and process data for inference and decision-making purposes under stringent energy constraints. These always-ON systems need to track changing data statistics and environmental conditions, such as temperature, with minimal energy consumption. Digital inference architectures [1,2] are not well-suited for such energy-constrained sensory systems due to their high energy consumption, which is dominated (>75%) by the energy cost of memory read accesses and digital computations. In-memory architectures [3,4] significantly reduce the energy cost by embedding pitch-matched analog computations in the periphery of the SRAM bitcell array (BCA). However, their analog nature combined with stringent area constraints makes these architectures susceptible to process, voltage, and temperature (PVT) variation. Previously, off-chip training [4] has been shown to be effective in compensating for PVT variations of in-memory architectures. However, PVT variations are die-specific and data statistics in always-ON sensory systems can change over time. Thus, on-chip training is critical to address both sources of variation and to enable the design of energy efficient always-ON sensory systems based on in-memory architectures. The stochastic gradient descent (SGD) algorithm is widely used to train machine learning algorithms such as support vector machines (SVMs), deep neural networks (DNNs) and others. This paper demonstrates the use of on-chip SGD-based training to compensate for PVT and data statistics variation to design a robust in-memory SVM classifier.
{"title":"A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training","authors":"Sujan Kumar Gonugondla, Mingu Kang, Naresh R Shanbhag","doi":"10.1109/ISSCC.2018.8310398","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310398","url":null,"abstract":"Embedded sensory systems (Fig. 31.2.1) continuously acquire and process data for inference and decision-making purposes under stringent energy constraints. These always-ON systems need to track changing data statistics and environmental conditions, such as temperature, with minimal energy consumption. Digital inference architectures [1,2] are not well-suited for such energy-constrained sensory systems due to their high energy consumption, which is dominated (>75%) by the energy cost of memory read accesses and digital computations. In-memory architectures [3,4] significantly reduce the energy cost by embedding pitch-matched analog computations in the periphery of the SRAM bitcell array (BCA). However, their analog nature combined with stringent area constraints makes these architectures susceptible to process, voltage, and temperature (PVT) variation. Previously, off-chip training [4] has been shown to be effective in compensating for PVT variations of in-memory architectures. However, PVT variations are die-specific and data statistics in always-ON sensory systems can change over time. Thus, on-chip training is critical to address both sources of variation and to enable the design of energy efficient always-ON sensory systems based on in-memory architectures. The stochastic gradient descent (SGD) algorithm is widely used to train machine learning algorithms such as support vector machines (SVMs), deep neural networks (DNNs) and others. This paper demonstrates the use of on-chip SGD-based training to compensate for PVT and data statistics variation to design a robust in-memory SVM classifier.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"16 1","pages":"490-492"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80694790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310317
Sechang Oh, Yao Shi, Gyouho Kim, Yejoong Kim, Taewook Kang, Seokhyeon Jeong, D. Sylvester, D. Blaauw
Small form-factor piezoresistive MEMS sensors, often configured in a Wheatstone bridge, are widely used to measure physical signals such as pressure [1-3], temperature [4], force [1], and gas concentration. A common method to realize a digital output from the bridge involves biasing the bridge with a DC voltage source and using a low-noise amplifier followed by an ADC. While a bridge measurement can achieve high resolution and linearity, it is very power hungry [3] because the bridge resistance is low (typically 1–10kΩ). Both the high power and high instantaneous current make it unsuitable as a sensing interface in miniaturized microsystems with battery capacities of <10μAh and ∼15kΩ internal resistance [5]. Duty cycled excitation was proposed in [1] to reduce power in moderate dynamic range (DR) applications, lowering bridge excitation energy by up to 125x compared to static biasing. However, the excitation energy consumption (∼250nJ) is still much larger than the interface circuit conversion energy, and therefore limits overall sensor energy efficiency. To address this challenge, we propose an energy-efficient highly duty-cycled excitation bridge-sensor readout circuit for small battery-operated systems. Due to high battery resistances, the excitation voltage (VEX) is sourced from an on-chip decoupling capacitance that drops ∼100mV during excitation and then slowly recharges from the battery. To avoid accuracy degradation from this voltage fluctuation, the design samples not only the inputs (VIN+/−) but also VEX, from which it generates a DAC reference voltage (VDAC). We also propose an offset calibration and input-range matching method. We demonstrate operation of the bridge-to-digital converter (BDC) integrated with a complete and fully functional pressure-sensing system, including a processor, battery, power management unit, RF transmitter, and optical receiver.
{"title":"A 2.5nJ duty-cycled bridge-to-digital converter integrated in a 13mm3 pressure-sensing system","authors":"Sechang Oh, Yao Shi, Gyouho Kim, Yejoong Kim, Taewook Kang, Seokhyeon Jeong, D. Sylvester, D. Blaauw","doi":"10.1109/ISSCC.2018.8310317","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310317","url":null,"abstract":"Small form-factor piezoresistive MEMS sensors, often configured in a Wheatstone bridge, are widely used to measure physical signals such as pressure [1-3], temperature [4], force [1], and gas concentration. A common method to realize a digital output from the bridge involves biasing the bridge with a DC voltage source and using a low-noise amplifier followed by an ADC. While a bridge measurement can achieve high resolution and linearity, it is very power hungry [3] because the bridge resistance is low (typically 1–10kΩ). Both the high power and high instantaneous current make it unsuitable as a sensing interface in miniaturized microsystems with battery capacities of <10μAh and ∼15kΩ internal resistance [5]. Duty cycled excitation was proposed in [1] to reduce power in moderate dynamic range (DR) applications, lowering bridge excitation energy by up to 125x compared to static biasing. However, the excitation energy consumption (∼250nJ) is still much larger than the interface circuit conversion energy, and therefore limits overall sensor energy efficiency. To address this challenge, we propose an energy-efficient highly duty-cycled excitation bridge-sensor readout circuit for small battery-operated systems. Due to high battery resistances, the excitation voltage (VEX) is sourced from an on-chip decoupling capacitance that drops ∼100mV during excitation and then slowly recharges from the battery. To avoid accuracy degradation from this voltage fluctuation, the design samples not only the inputs (VIN+/−) but also VEX, from which it generates a DAC reference voltage (VDAC). We also propose an offset calibration and input-range matching method. We demonstrate operation of the bridge-to-digital converter (BDC) integrated with a complete and fully functional pressure-sensing system, including a processor, battery, power management unit, RF transmitter, and optical receiver.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"18 1","pages":"328-330"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75844916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310393
Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Y. Shih, Y. Chih, T. Chang, D. Blaauw, D. Sylvester
1T1R spin-transfer-torque (STT) MRAM is a promising candidate for next-generation high-density embedded non-volatile memory [1-2]. However, 1T1R STT-MRAM suffers from limited sensing margin and high write power. As shown in Fig. 30.2.1(a), sense amplifier design is challenging due to the small difference (only 2x) between the high-resistance state (RAP) and the low-resistance state (RP), as well as RAP degradation with increasing temperature. Moreover, RP and RAP resistance distributions shift with process variation, requiring a read reference (Vref) that tracks process. To improve the sensing margin, several offset-cancellation methods have been reported to reduce sense amplifier mismatch [3]. However, these methods use multiple capacitors and hence incur significant area overheads. To address this issue, we propose an offset-cancelled sense amplifier that uses only a single capacitor to significantly improve the sensing margin by more than 60%. A second design challenge for STT-MRAM stems from the high current needed to flip a cell during a write operation. For non-volatile memory applications with a 10-year retention time requirement, the write current can be as high as several hundred μA. However, as shown in Fig. 30.2.1(b), the required write time varies with the state change required (0→1 or 1→0), process variation, and temperature. As a result, a fixed write time that ensures successful write for all conditions wastes a significant energy for typical or average conditions. We propose an in situ write-self-termination method to reduce write energy in most scenarios. The sense amplifier is reconfigured to continuously monitor the write operation and automatically shuts off the write drivers when the state transition is detected, without an area or timing penalty. In addition, dual dummy columns are added in each array to provide read Vref tracking of row-wise PVT variation. A 1Mb STT-MRAM was fabricated in 28nm technology, and achieves a 2.8ns read-access time at 25°C and 3.6ns at 120°C, respectively. With in-situ self-write-termination the write power is reduced by 47% with a 20ns write-access time at 25°C and by 60% at 120°C.
{"title":"A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination","authors":"Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Y. Shih, Y. Chih, T. Chang, D. Blaauw, D. Sylvester","doi":"10.1109/ISSCC.2018.8310393","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310393","url":null,"abstract":"1T1R spin-transfer-torque (STT) MRAM is a promising candidate for next-generation high-density embedded non-volatile memory [1-2]. However, 1T1R STT-MRAM suffers from limited sensing margin and high write power. As shown in Fig. 30.2.1(a), sense amplifier design is challenging due to the small difference (only 2x) between the high-resistance state (RAP) and the low-resistance state (RP), as well as RAP degradation with increasing temperature. Moreover, RP and RAP resistance distributions shift with process variation, requiring a read reference (Vref) that tracks process. To improve the sensing margin, several offset-cancellation methods have been reported to reduce sense amplifier mismatch [3]. However, these methods use multiple capacitors and hence incur significant area overheads. To address this issue, we propose an offset-cancelled sense amplifier that uses only a single capacitor to significantly improve the sensing margin by more than 60%. A second design challenge for STT-MRAM stems from the high current needed to flip a cell during a write operation. For non-volatile memory applications with a 10-year retention time requirement, the write current can be as high as several hundred μA. However, as shown in Fig. 30.2.1(b), the required write time varies with the state change required (0→1 or 1→0), process variation, and temperature. As a result, a fixed write time that ensures successful write for all conditions wastes a significant energy for typical or average conditions. We propose an in situ write-self-termination method to reduce write energy in most scenarios. The sense amplifier is reconfigured to continuously monitor the write operation and automatically shuts off the write drivers when the state transition is detected, without an area or timing penalty. In addition, dual dummy columns are added in each array to provide read Vref tracking of row-wise PVT variation. A 1Mb STT-MRAM was fabricated in 28nm technology, and achieves a 2.8ns read-access time at 25°C and 3.6ns at 120°C, respectively. With in-situ self-write-termination the write power is reduced by 47% with a 20ns write-access time at 25°C and by 60% at 120°C.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"10 1","pages":"480-482"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81305257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310246
Chao Chen, Zhao Chen, D. Bera, Emile Noothout, Z. Chang, Mingliang Tan, H. Vos, J. Bosch, M. Verweij, N. Jong, M. Pertijs
Data acquisition from 2D transducer arrays is one of the main challenges for the development of emerging miniature 3D ultrasound imaging devices, such as 3D trans-esophageal (TEE) and intra-cardiac echocardiography (ICE) probes (Fig. 10.5.1). The main obstacle lies in the mismatch between the large number of transducer elements (103 to 104) and the limited cable count (<200). Recent advances in transducer-on-CMOS integration have enabled the use of in-probe subarray beamforming based on delay-and-sum (DAS) circuits [1] to reduce the channel count by an order of magnitude. Further reduction calls for in-probe digitization to enable more advanced data processing and compression in the digital domain. However, prior designs [2-4] compromise on transducer pitch (> half wavelength) to accommodate the ADC and consume >9mW/element, which translates into unacceptable self-heating in miniature 3D probes.
{"title":"A 0.91mW/element pitch-matched front-end ASIC with integrated subarray beamforming ADC for miniature 3D ultrasound probes","authors":"Chao Chen, Zhao Chen, D. Bera, Emile Noothout, Z. Chang, Mingliang Tan, H. Vos, J. Bosch, M. Verweij, N. Jong, M. Pertijs","doi":"10.1109/ISSCC.2018.8310246","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310246","url":null,"abstract":"Data acquisition from 2D transducer arrays is one of the main challenges for the development of emerging miniature 3D ultrasound imaging devices, such as 3D trans-esophageal (TEE) and intra-cardiac echocardiography (ICE) probes (Fig. 10.5.1). The main obstacle lies in the mismatch between the large number of transducer elements (103 to 104) and the limited cable count (<200). Recent advances in transducer-on-CMOS integration have enabled the use of in-probe subarray beamforming based on delay-and-sum (DAS) circuits [1] to reduce the channel count by an order of magnitude. Further reduction calls for in-probe digitization to enable more advanced data processing and compression in the digital domain. However, prior designs [2-4] compromise on transducer pitch (> half wavelength) to accommodate the ADC and consume >9mW/element, which translates into unacceptable self-heating in miniature 3D probes.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"190 1","pages":"186-188"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77240133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310243
Q. Guo, William Deng, O. Bebek, M. C. Cavusoglu, C. Mastrangelo, D. Young
An accurate personal inertial navigation system under GPS-denied environment is highly critical for demanding applications such as firefighting, rescue missions, and military operations. Location-aware computation for large-area mixed reality also calls for accurate personal position tracking. Position calculation can be accomplished by using an inertial measurement unit (IMU) composed of a 3-axis accelerometer, 3-axis gyroscope, and 3-axis magnetometer. A gyroscope and magnetometer together can provide the orientation information, while the displacement can be obtained by integrating the acceleration data over time. A MEMS-based IMU is attractive for its small size, low power and low cost. However, such devices exhibit a limited accuracy, large offset, and time drift, which can result in an excessive position error over time. To achieve high-performance navigation, it is critical to accurately reset the IMU time-integration during each step when the foot contacts the ground. Furthermore, correcting the IMU inherent inaccuracy, bias, and time drift becomes important for improving system performance.
{"title":"Personal inertial navigation system employing MEMS wearable ground reaction sensor array and interface ASIC achieving a position accuracy of 5.5m over 3km walking distance without GPS","authors":"Q. Guo, William Deng, O. Bebek, M. C. Cavusoglu, C. Mastrangelo, D. Young","doi":"10.1109/ISSCC.2018.8310243","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310243","url":null,"abstract":"An accurate personal inertial navigation system under GPS-denied environment is highly critical for demanding applications such as firefighting, rescue missions, and military operations. Location-aware computation for large-area mixed reality also calls for accurate personal position tracking. Position calculation can be accomplished by using an inertial measurement unit (IMU) composed of a 3-axis accelerometer, 3-axis gyroscope, and 3-axis magnetometer. A gyroscope and magnetometer together can provide the orientation information, while the displacement can be obtained by integrating the acceleration data over time. A MEMS-based IMU is attractive for its small size, low power and low cost. However, such devices exhibit a limited accuracy, large offset, and time drift, which can result in an excessive position error over time. To achieve high-performance navigation, it is critical to accurately reset the IMU time-integration during each step when the foot contacts the ground. Furthermore, correcting the IMU inherent inaccuracy, bias, and time drift becomes important for improving system performance.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"101 9 1","pages":"180-182"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83332598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310278
Daniel Weyer, M. B. Dayanik, Sunmin Jang, M. Flynn
Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-digital PLLs (ADPLLs) promise greater flexibility and area efficiency. However, existing mm-wave ADPLLs are large, fail to offer low in-band phase noise [1] or must rely on extensive calibration [2]. Performance limitations of conventional TDCs still remain a major roadblock for the adoption of high-frequency ADPLLs. To address this problem, this work introduces a noise-shaping TDC based on a 4th-order bandpass ΔΣ modulator (BPDSM) to achieve low integrated noise (183fsrms) and high linearity. Our approach enables low in-band phase noise (−85dBc/Hz @ 100kHz) for wide loop bandwidths (>1MHz) in a calibration-free single-loop digital 36.3-to-38.2GHz PLL. The prototype PLL effectively generates fast (500MHz/55μs) and precise (824kHzrms frequency error) triangular chirps for FMCW radar applications.
{"title":"A 36.3-to-38.2GHz −216dBc/Hz2 40nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter","authors":"Daniel Weyer, M. B. Dayanik, Sunmin Jang, M. Flynn","doi":"10.1109/ISSCC.2018.8310278","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310278","url":null,"abstract":"Automotive radar and other mm-wave applications require high-quality frequency synthesizers that offer fast settling and low phase noise. Analog PLLs still dominate in the mm-wave range, but all-digital PLLs (ADPLLs) promise greater flexibility and area efficiency. However, existing mm-wave ADPLLs are large, fail to offer low in-band phase noise [1] or must rely on extensive calibration [2]. Performance limitations of conventional TDCs still remain a major roadblock for the adoption of high-frequency ADPLLs. To address this problem, this work introduces a noise-shaping TDC based on a 4th-order bandpass ΔΣ modulator (BPDSM) to achieve low integrated noise (183fsrms) and high linearity. Our approach enables low in-band phase noise (−85dBc/Hz @ 100kHz) for wide loop bandwidths (>1MHz) in a calibration-free single-loop digital 36.3-to-38.2GHz PLL. The prototype PLL effectively generates fast (500MHz/55μs) and precise (824kHzrms frequency error) triangular chirps for FMCW radar applications.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"124 1","pages":"250-252"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76745448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310261
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, J. Kadomoto, T. Miyata, M. Hamada, T. Kuroda, M. Motomura
A key consideration for deep neural network (DNN) inference accelerators is the need for large and high-bandwidth external memories. Although an architectural concept for stacking a DNN accelerator with DRAMs has been proposed previously, long DRAM latency remains problematic and limits the performance [1]. Recent algorithm-level optimizations, such as network pruning and compression, have shown success in reducing the DNN memory size [2]; however, since networks become irregular and sparse, they induce an additional need for agile random accesses to the memory systems.
{"title":"QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS","authors":"Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, J. Kadomoto, T. Miyata, M. Hamada, T. Kuroda, M. Motomura","doi":"10.1109/ISSCC.2018.8310261","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310261","url":null,"abstract":"A key consideration for deep neural network (DNN) inference accelerators is the need for large and high-bandwidth external memories. Although an architectural concept for stacking a DNN accelerator with DRAMs has been proposed previously, long DRAM latency remains problematic and limits the performance [1]. Recent algorithm-level optimizations, such as network pruning and compression, have shown success in reducing the DNN memory size [2]; however, since networks become irregular and sparse, they induce an additional need for agile random accesses to the memory systems.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"135 1","pages":"216-218"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77428256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310383
S. Stanslaski, Jeffrey A. Herron, Elizabeth Fehrmann, Rob Corey, Heather Orser, E. Opri, V. Kremen, B. Brinkmann, A. Gunduz, K. Foote, G. Worrell, T. Denison
While first-generation implantable systems exist today that modulate the nervous system, there is a critical need for advancing neurotechnology to better serve patient populations. The convergence of neuroscience and technologies in circuits, algorithms, and energy transfer methods, combined with the growing burden of neurological diseases, make this a timely opportunity. Significantly improving systems arguably requires more than an incremental advancement of “deep brain stimulation;” we propose a fundamental shift in mindset in how engineered bioelectronic systems are interfaced with the body to treat disease.
{"title":"Creating neural “co-processors” to explore treatments for neurological disorders","authors":"S. Stanslaski, Jeffrey A. Herron, Elizabeth Fehrmann, Rob Corey, Heather Orser, E. Opri, V. Kremen, B. Brinkmann, A. Gunduz, K. Foote, G. Worrell, T. Denison","doi":"10.1109/ISSCC.2018.8310383","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310383","url":null,"abstract":"While first-generation implantable systems exist today that modulate the nervous system, there is a critical need for advancing neurotechnology to better serve patient populations. The convergence of neuroscience and technologies in circuits, algorithms, and energy transfer methods, combined with the growing burden of neurological diseases, make this a timely opportunity. Significantly improving systems arguably requires more than an incremental advancement of “deep brain stimulation;” we propose a fundamental shift in mindset in how engineered bioelectronic systems are interfaced with the body to treat disease.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"27 1","pages":"460-462"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84542297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310349
Karim M. Megawer, Ahmed Elkholy, Daniel Coombs, M. Ahmed, A. Elmallah, P. Hanumolu
Phase noise performance of ring-oscillator-based (RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (FBW). While FBW depends on the type of clock multiplier, the maximum achievable FBW is limited by the reference frequency (Fref). For instance, in phase-locked loops (PLLs) FBW = Fref/10, while multiplying delay-locked loops (MDLLs) [1] and injection-locked clock multipliers (ILCMs) [2] can achieve FBW of Fref/4 and Fref/6, respectively. Exploiting this behavior, the MDLL in [1] and the ILCM in [2] achieved excellent performance at the expense of using a high-frequency low-noise reference (REF) clock and a small multiplication factor (N < 10). One promising way to reduce Fref in MDLLs/ILCMs involves increasing the injection rate by using both the positive and negative edges of the REF clock [3, 4] but at the cost of making jitter/spurious performance susceptible to duty cycle errors in the REF clock. While [3] demonstrated an effective means to correct such errors, it still needed a relatively high Fref of 125MHz. In view of this, we present a method to quadruple the frequency of a conventional 54MHz Pierce XO and demonstrate its application using an RO-based ILCM achieving less than 370fsrms integrated jitter at a 5GHz output. The proposed quadrupler acts as a low noise XO frequency multiplier and can be used to increase the bandwidth of MDLLs and ring/LC-based integer-or fractional-N PLLs also.
{"title":"A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS","authors":"Karim M. Megawer, Ahmed Elkholy, Daniel Coombs, M. Ahmed, A. Elmallah, P. Hanumolu","doi":"10.1109/ISSCC.2018.8310349","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310349","url":null,"abstract":"Phase noise performance of ring-oscillator-based (RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (FBW). While FBW depends on the type of clock multiplier, the maximum achievable FBW is limited by the reference frequency (Fref). For instance, in phase-locked loops (PLLs) FBW = Fref/10, while multiplying delay-locked loops (MDLLs) [1] and injection-locked clock multipliers (ILCMs) [2] can achieve FBW of Fref/4 and Fref/6, respectively. Exploiting this behavior, the MDLL in [1] and the ILCM in [2] achieved excellent performance at the expense of using a high-frequency low-noise reference (REF) clock and a small multiplication factor (N < 10). One promising way to reduce Fref in MDLLs/ILCMs involves increasing the injection rate by using both the positive and negative edges of the REF clock [3, 4] but at the cost of making jitter/spurious performance susceptible to duty cycle errors in the REF clock. While [3] demonstrated an effective means to correct such errors, it still needed a relatively high Fref of 125MHz. In view of this, we present a method to quadruple the frequency of a conventional 54MHz Pierce XO and demonstrate its application using an RO-based ILCM achieving less than 370fsrms integrated jitter at a 5GHz output. The proposed quadrupler acts as a low noise XO frequency multiplier and can be used to increase the bandwidth of MDLLs and ring/LC-based integer-or fractional-N PLLs also.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"1 1","pages":"392-394"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89589488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-08DOI: 10.1109/ISSCC.2018.8310226
Inho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim
As a newly emerging energy source, a triboelectric nanogenerator (TENG) was introduced in 2012, and various types of energy harvesters and active sensors based on the TENG have since been developed. Although research in the material-engineering field is actively conducted, there is not much research on TENG energy-harvesting circuits in the integrated-circuits field. From the viewpoint of material engineering, much research focuses on the applications and the analysis of instantaneous power. However, topics such as rms maximum power point (MPP), spice modeling, and impedance matching are more important from the circuit designer's viewpoint. This paper presents a TENG energy-harvesting circuit designed as a high-voltage (HV) dual-input (DI) buck converter with MPP tracking (MPPT) based on the proposed MPP analysis for the TENG.
{"title":"A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage","authors":"Inho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim","doi":"10.1109/ISSCC.2018.8310226","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310226","url":null,"abstract":"As a newly emerging energy source, a triboelectric nanogenerator (TENG) was introduced in 2012, and various types of energy harvesters and active sensors based on the TENG have since been developed. Although research in the material-engineering field is actively conducted, there is not much research on TENG energy-harvesting circuits in the integrated-circuits field. From the viewpoint of material engineering, much research focuses on the applications and the analysis of instantaneous power. However, topics such as rms maximum power point (MPP), spice modeling, and impedance matching are more important from the circuit designer's viewpoint. This paper presents a TENG energy-harvesting circuit designed as a high-voltage (HV) dual-input (DI) buck converter with MPP tracking (MPPT) based on the proposed MPP analysis for the TENG.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"566 1","pages":"146-148"},"PeriodicalIF":0.0,"publicationDate":"2018-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89966579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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