Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310187
Min-Yu Huang, T. Chi, Fei Wang, Tso-Wei Li, Hua Wang
Millimeter-wave massive MIMOs leverage large array size to enhance the link budget and spatial selectivity, but their resulting narrow beamwidth substantially complicates the transmitter-receiver (TX-RX) alignment. Unlike most existing “static” applications (e.g., mm-wave HDTV transmission), many future mm-wave links will operate in highly “dynamic” environments, such as wireless AR/VR and vehicle-/drone-/machine-based links, necessitating rapid and precise beam-forming/-tracking for high link reliability and low latency. Densely deployed mm-wave nodes will also result in future congested/contested environments, requiring spatially tracking/rejecting unknown blockers (unknown frequency, angle-of-arrival AoA, or modulation).
{"title":"A 23-to-30GHz hybrid beamforming MIMO receiver array with closed-loop multistage front-end beamformers for full-FoV dynamic and autonomous unknown signal tracking and blocker rejection","authors":"Min-Yu Huang, T. Chi, Fei Wang, Tso-Wei Li, Hua Wang","doi":"10.1109/ISSCC.2018.8310187","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310187","url":null,"abstract":"Millimeter-wave massive MIMOs leverage large array size to enhance the link budget and spatial selectivity, but their resulting narrow beamwidth substantially complicates the transmitter-receiver (TX-RX) alignment. Unlike most existing “static” applications (e.g., mm-wave HDTV transmission), many future mm-wave links will operate in highly “dynamic” environments, such as wireless AR/VR and vehicle-/drone-/machine-based links, necessitating rapid and precise beam-forming/-tracking for high link reliability and low latency. Densely deployed mm-wave nodes will also result in future congested/contested environments, requiring spatially tracking/rejecting unknown blockers (unknown frequency, angle-of-arrival AoA, or modulation).","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"99 1","pages":"68-70"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85856578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310315
Long Xu, J. Huijsing, K. Makinwa
This paper presents a fully integrated ±4A current sensor that supports a 25V input common-mode voltage range (CMVR) while operating from a single 1.5V supply. It consists of an on-chip metal shunt, a beyond-the-rails ADC [1] and a temperature-dependent voltage reference. The beyond-the-rails ADC facilitates high-side current sensing without the need for external resistive dividers or level shifters, thus reducing power consumption and system complexity. To compensate for the shunt's temperature dependence, the ADC employs a proportional-to-absolute-temperature (PTAT) reference voltage. Compared to digital temperature compensation schemes [2,3], this analog scheme eliminates the need for a temperature sensor, a band-gap voltage reference and calibration logic. As a result, the current sensor draws only 10.9μA and is 10x more energy efficient than [2]. Over a ±4A range, and after a one-point trim, the sensor exhibits a 0.9% (max) gain error from −40°C to 85°C and a 0.05% gain error at room temperature. The former is comparable with that of other fully-integrated current sensors [2-4], while the latter represents the state-of-the-art.
{"title":"A ±4A high-side current sensor with 25V input CM range and 0.9% gain error from −40°C to 85°C using an analog temperature compensation technique","authors":"Long Xu, J. Huijsing, K. Makinwa","doi":"10.1109/ISSCC.2018.8310315","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310315","url":null,"abstract":"This paper presents a fully integrated ±4A current sensor that supports a 25V input common-mode voltage range (CMVR) while operating from a single 1.5V supply. It consists of an on-chip metal shunt, a beyond-the-rails ADC [1] and a temperature-dependent voltage reference. The beyond-the-rails ADC facilitates high-side current sensing without the need for external resistive dividers or level shifters, thus reducing power consumption and system complexity. To compensate for the shunt's temperature dependence, the ADC employs a proportional-to-absolute-temperature (PTAT) reference voltage. Compared to digital temperature compensation schemes [2,3], this analog scheme eliminates the need for a temperature sensor, a band-gap voltage reference and calibration logic. As a result, the current sensor draws only 10.9μA and is 10x more energy efficient than [2]. Over a ±4A range, and after a one-point trim, the sensor exhibits a 0.9% (max) gain error from −40°C to 85°C and a 0.05% gain error at room temperature. The former is comparable with that of other fully-integrated current sensors [2-4], while the latter represents the state-of-the-art.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"29 1","pages":"324-326"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86852172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310345
A. Seidel, B. Wicht
Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ∼1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.
{"title":"A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors","authors":"A. Seidel, B. Wicht","doi":"10.1109/ISSCC.2018.8310345","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310345","url":null,"abstract":"Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ∼1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"26 1","pages":"384-386"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76013657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modulation schemes employed in long-term-evolution advanced (LTE-A) services for higher data-rate with high peak-to-average power ratios (PAPR) are becoming more complicated, which degrades the efficiency of RF power amplifiers (PA). Envelope-tracking modulators (ETM) have been proposed to improve the PA efficiency and linearity by dynamically adjusting the supply voltage of the RF PA according to the envelope of the transmitted signal.
{"title":"An 87.1% efficiency RF-PA envelope-tracking modulator for 80MHz LTE-Advanced transmitter and 31dBm PA output power for HPUE in 0.153μm CMOS","authors":"Chen-Yen Ho, Shih-Mei Lin, Che-Hao Meng, Hao-Ping Hong, Sheng-Hong Yan, Ting-Hsun Kuo, Chia-Sheng Peng, Chieh-Hsun Hsiao, Hsin-Hung Chen, D. Sung, Chien-Wei Kuan","doi":"10.1109/ISSCC.2018.8310369","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310369","url":null,"abstract":"Modulation schemes employed in long-term-evolution advanced (LTE-A) services for higher data-rate with high peak-to-average power ratios (PAPR) are becoming more complicated, which degrades the efficiency of RF power amplifiers (PA). Envelope-tracking modulators (ETM) have been proposed to improve the PA efficiency and linearity by dynamically adjusting the supply voltage of the RF PA according to the envelope of the transmitted signal.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"65 1","pages":"432-434"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79566419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310272
Shoubhik Karmakar, B. Gonen, F. Sebastiano, R. V. Veldhoven, K. Makinwa
Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.
{"title":"A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW","authors":"Shoubhik Karmakar, B. Gonen, F. Sebastiano, R. V. Veldhoven, K. Makinwa","doi":"10.1109/ISSCC.2018.8310272","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310272","url":null,"abstract":"Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"49 1","pages":"238-240"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77289716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310290
Marc Erett, D. Carey, James Hudner, R. Casey, Kevin Geary, Pedro Neto, M. Raj, S. McLeod, Hongtao Zhang, A. Roldan, Hongyuan Zhao, P. Chiang, Haibing Zhao, Kee Hian Tan, Y. Frans, Ken Chang
The industry has recently proposed standards for synchronous high-speed interfaces targeting chip-to-chip communication across a very short PCB trace [1]. Figure 16.7.1 shows an example of such an interface. Eight 56Gb/s NRZ lanes provide a total of 448Gb/s aggregate bandwidth in each direction. The channel insertion loss and propagation delay varies from lane to lane, with a maximum insertion loss of 8dB at 28GHz from BGA to BGA. The routing inside the two packages adds an additional 3dB insertion loss at 28GHz. Taking advantage of the relatively low channel loss, the interface is expected to adopt simple transmitter/receiver circuits with low power consumption. However, a per-lane deskewing scheme is still required due to the propagation delay variations between lanes.
{"title":"A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET","authors":"Marc Erett, D. Carey, James Hudner, R. Casey, Kevin Geary, Pedro Neto, M. Raj, S. McLeod, Hongtao Zhang, A. Roldan, Hongyuan Zhao, P. Chiang, Haibing Zhao, Kee Hian Tan, Y. Frans, Ken Chang","doi":"10.1109/ISSCC.2018.8310290","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310290","url":null,"abstract":"The industry has recently proposed standards for synchronous high-speed interfaces targeting chip-to-chip communication across a very short PCB trace [1]. Figure 16.7.1 shows an example of such an interface. Eight 56Gb/s NRZ lanes provide a total of 448Gb/s aggregate bandwidth in each direction. The channel insertion loss and propagation delay varies from lane to lane, with a maximum insertion loss of 8dB at 28GHz from BGA to BGA. The routing inside the two packages adds an additional 3dB insertion loss at 28GHz. Taking advantage of the relatively low channel loss, the interface is expected to adopt simple transmitter/receiver circuits with low power consumption. However, a per-lane deskewing scheme is still required due to the propagation delay variations between lanes.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"38 1","pages":"274-276"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86956105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310309
Loai G. Salem, P. Mercier
Modern DVFS-enabled SoCs require nimble supply regulators that rapidly respond to abrupt load changes and offer fine resolution (e.g., 12.5mV in [1], 10mV in [2]) over large voltage and current dynamic ranges. Switch-array digital LDOs (SA-DLDOs) are a potentially attractive regulation option due to their ability to operate with low input voltages and in part to their modular digital nature and scalability. SA-DLDOs employ 2” unary-[3] or binary-weighted [4] PMOS arrays that are modulated through a 1b or multi-bit ADCs to maintain the output voltage (Vout) at the desired level (Vref), as shown in Fig. 18.7.1 (top left). Unfortunately, while array conductance in SA-DLDOs linearly increases with equal step size (gLSB) as the code is increased, the output voltage step, vLSB, does not; in fact, vLsB is nonlinear: ∼GLVout × GLSB. Thus, SA-DLDOs achieve a nonlinear steady-state error, ess = Veef − Vout ≈ ±gLSB/Gl χ Vú!op, as shown in Fig. 18.7.1 (bottom left), that deteriorates at large dropout voltages, Vdrop = Vin − Voitt, and at small loads, Gl. As a result, the required supply step of 10mV (with ±15% typical accuracy) to perform per-core DVFS over a typical 100χ IL dynamic range requires an impractical 16b PMOS array resolution. Even with limit-cycle oscillations, the load range that can achieve ±1.5mV accuracy is provably limited to 2N-6, 7 at Veef=VJ2 (Fig. 18.7.2, top left), which would still require a 14b array resolution that, even if it were feasible to build, would come with linearly (for binary search) or exponentially (for linear search) increased response time (TR), quiescent power (IQ), and area.
{"title":"A sub-1.55mV-accuracy 36.9ps-FOM digital-low-dropout regulator employing switched-capacitor resistance","authors":"Loai G. Salem, P. Mercier","doi":"10.1109/ISSCC.2018.8310309","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310309","url":null,"abstract":"Modern DVFS-enabled SoCs require nimble supply regulators that rapidly respond to abrupt load changes and offer fine resolution (e.g., 12.5mV in [1], 10mV in [2]) over large voltage and current dynamic ranges. Switch-array digital LDOs (SA-DLDOs) are a potentially attractive regulation option due to their ability to operate with low input voltages and in part to their modular digital nature and scalability. SA-DLDOs employ 2” unary-[3] or binary-weighted [4] PMOS arrays that are modulated through a 1b or multi-bit ADCs to maintain the output voltage (V<inf>out</inf>) at the desired level (V<inf>ref</inf>), as shown in Fig. 18.7.1 (top left). Unfortunately, while array conductance in SA-DLDOs linearly increases with equal step size (<inf>g</inf>LSB) as the code is increased, the output voltage step, <inf>v</inf>LSB, does not; in fact, <inf>v</inf>LsB is nonlinear: ∼G<inf>L</inf>V<inf>out</inf> × <inf>G</inf>LSB. Thus, SA-DLDOs achieve a nonlinear steady-state error, e<inf>ss</inf> = V<inf>eef</inf> − V<inf>out</inf> ≈ ±<inf>g</inf>LSB/G<inf>l</inf> χ V<inf>ú!op</inf>, as shown in Fig. 18.7.1 (bottom left), that deteriorates at large dropout voltages, V<inf>drop</inf> = V<inf>in</inf> − V<inf>oitt</inf>, and at small loads, G<inf>l</inf>. As a result, the required supply step of 10mV (with ±15% typical accuracy) to perform per-core DVFS over a typical 100χ I<inf>L</inf> dynamic range requires an impractical 16b PMOS array resolution. Even with limit-cycle oscillations, the load range that can achieve ±1.5mV accuracy is provably limited to 2<sup>N-6, 7</sup> at V<inf>eef</inf>=VJ2 (Fig. 18.7.2, top left), which would still require a 14b array resolution that, even if it were feasible to build, would come with linearly (for binary search) or exponentially (for linear search) increased response time (T<inf>R</inf>), quiescent power (IQ), and area.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"22 1","pages":"312-314"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73105627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310184
Shinwoong Park, Dongseok Shin, Kwang-Jin Koh, S. Raman
Discrete-time (DT) circuits provide a means to overcome the analog-circuit design challenges in deeply scaled digital CMOS technologies while benefitting from the reduced switch on-resistance and parasitic capacitance, resulting in lower dynamic power dissipation. In addition, such DT analog circuits can reduce the requirements on analog-to-digital converters that precede digital processing [1]. Recent DT domain filters achieve high-order narrowband programmable filtering with low power and high linearity even under low supply voltage [2,3]. However, DT switched capacitor circuits have not been considered for wideband analog signal processing (ASP) applications such as on-chip implementation of FIR-based beamforming [4,5]. While the AFIR filter proposed in [6] is a suitable approach for programmable wideband ASP applications, in that design only symmetric and positive coefficient sets were possible and measured performance was not shown.
{"title":"A low-power 3.25GS/s 4th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processing","authors":"Shinwoong Park, Dongseok Shin, Kwang-Jin Koh, S. Raman","doi":"10.1109/ISSCC.2018.8310184","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310184","url":null,"abstract":"Discrete-time (DT) circuits provide a means to overcome the analog-circuit design challenges in deeply scaled digital CMOS technologies while benefitting from the reduced switch on-resistance and parasitic capacitance, resulting in lower dynamic power dissipation. In addition, such DT analog circuits can reduce the requirements on analog-to-digital converters that precede digital processing [1]. Recent DT domain filters achieve high-order narrowband programmable filtering with low power and high linearity even under low supply voltage [2,3]. However, DT switched capacitor circuits have not been considered for wideband analog signal processing (ASP) applications such as on-chip implementation of FIR-based beamforming [4,5]. While the AFIR filter proposed in [6] is a suitable approach for programmable wideband ASP applications, in that design only symmetric and positive coefficient sets were possible and measured performance was not shown.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"60 1","pages":"62-64"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73900937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310379
J. Moody, Pouyan Bassirian, Abhishek Roy, Ningxi Liu, Stephen Pancrazio, N. Scott Barker, B. Calhoun, S. Bowers
Event-driven sensor nodes have applications in agriculture, infrastructure, and perimeter monitoring and are characterized by spending the vast majority of their time in an asleep-yet-alert state. In this state, the node must wake to incoming RF wakeup commands from an antenna with minimal dc power, as the total percentage of power in sleep mode dominates if wakeup events are sufficiently infrequent. The RF wakeup receiver (WuRX) is one critical block of the node's asleep-yet-alert state. It must maximize sensitivity with power consumptions of 10nW or less to maximize battery lifetime or even enable battery-less systems that persist on energy harvesting [1-3]. These WuRXs must reliably detect wakeup signals as well as reject false wakeups caused by external interferer signals or noise. Otherwise, booting the full node into its active state when it is not needed can quickly relinquish power savings created by the wakeup radio in its asleep-yet-alert state.
{"title":"A −76dBm 7.4nW wakeup radio with automatic offset compensation","authors":"J. Moody, Pouyan Bassirian, Abhishek Roy, Ningxi Liu, Stephen Pancrazio, N. Scott Barker, B. Calhoun, S. Bowers","doi":"10.1109/ISSCC.2018.8310379","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310379","url":null,"abstract":"Event-driven sensor nodes have applications in agriculture, infrastructure, and perimeter monitoring and are characterized by spending the vast majority of their time in an asleep-yet-alert state. In this state, the node must wake to incoming RF wakeup commands from an antenna with minimal dc power, as the total percentage of power in sleep mode dominates if wakeup events are sufficiently infrequent. The RF wakeup receiver (WuRX) is one critical block of the node's asleep-yet-alert state. It must maximize sensitivity with power consumptions of 10nW or less to maximize battery lifetime or even enable battery-less systems that persist on energy harvesting [1-3]. These WuRXs must reliably detect wakeup signals as well as reject false wakeups caused by external interferer signals or noise. Otherwise, booting the full node into its active state when it is not needed can quickly relinquish power savings created by the wakeup radio in its asleep-yet-alert state.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"22 1","pages":"452-454"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73355804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310217
N. E. C. Akkaya, B. Erbagci, K. Mai
With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production, counterfeiting, IP theft, and hardware Trojan Horses. A parallel and related threat is posed by advanced reverse engineering capabilities, such that even chips manufactured at the most advanced technology nodes can be de-layered, imaged, and analyzed [1]. While various manufacturing methodologies and camouflaged gates have been proposed, none fully address these threats, especially in combination. To address these concerns, we use post-manufacturing programmable camouflaged logic topology to simultaneously obscure the design IP from the manufacturer as well as combat reverse engineering. The basis of the design is a threshold-voltage-defined (TVD) logic gate topology that solely uses different threshold voltage implants to determine the logic gate function [2]. Every gate has an identical physical layout and is post-manufacturing programmed with different threshold voltages for different Boolean functions using intentional directed hot-carrier injection (HCI). Similar intentional HCI techniques have previously been used to enhance SRAM margins, boost PUF reliability, and build TRNGs [3][4]. The design is fully compatible with standard CMOS logic processes, requiring no special layers, structures, or process steps.
{"title":"A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD","authors":"N. E. C. Akkaya, B. Erbagci, K. Mai","doi":"10.1109/ISSCC.2018.8310217","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310217","url":null,"abstract":"With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production, counterfeiting, IP theft, and hardware Trojan Horses. A parallel and related threat is posed by advanced reverse engineering capabilities, such that even chips manufactured at the most advanced technology nodes can be de-layered, imaged, and analyzed [1]. While various manufacturing methodologies and camouflaged gates have been proposed, none fully address these threats, especially in combination. To address these concerns, we use post-manufacturing programmable camouflaged logic topology to simultaneously obscure the design IP from the manufacturer as well as combat reverse engineering. The basis of the design is a threshold-voltage-defined (TVD) logic gate topology that solely uses different threshold voltage implants to determine the logic gate function [2]. Every gate has an identical physical layout and is post-manufacturing programmed with different threshold voltages for different Boolean functions using intentional directed hot-carrier injection (HCI). Similar intentional HCI techniques have previously been used to enhance SRAM margins, boost PUF reliability, and build TRNGs [3][4]. The design is fully compatible with standard CMOS logic processes, requiring no special layers, structures, or process steps.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"20 1","pages":"128-130"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72794673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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