Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310187
Min-Yu Huang, T. Chi, Fei Wang, Tso-Wei Li, Hua Wang
Millimeter-wave massive MIMOs leverage large array size to enhance the link budget and spatial selectivity, but their resulting narrow beamwidth substantially complicates the transmitter-receiver (TX-RX) alignment. Unlike most existing “static” applications (e.g., mm-wave HDTV transmission), many future mm-wave links will operate in highly “dynamic” environments, such as wireless AR/VR and vehicle-/drone-/machine-based links, necessitating rapid and precise beam-forming/-tracking for high link reliability and low latency. Densely deployed mm-wave nodes will also result in future congested/contested environments, requiring spatially tracking/rejecting unknown blockers (unknown frequency, angle-of-arrival AoA, or modulation).
{"title":"A 23-to-30GHz hybrid beamforming MIMO receiver array with closed-loop multistage front-end beamformers for full-FoV dynamic and autonomous unknown signal tracking and blocker rejection","authors":"Min-Yu Huang, T. Chi, Fei Wang, Tso-Wei Li, Hua Wang","doi":"10.1109/ISSCC.2018.8310187","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310187","url":null,"abstract":"Millimeter-wave massive MIMOs leverage large array size to enhance the link budget and spatial selectivity, but their resulting narrow beamwidth substantially complicates the transmitter-receiver (TX-RX) alignment. Unlike most existing “static” applications (e.g., mm-wave HDTV transmission), many future mm-wave links will operate in highly “dynamic” environments, such as wireless AR/VR and vehicle-/drone-/machine-based links, necessitating rapid and precise beam-forming/-tracking for high link reliability and low latency. Densely deployed mm-wave nodes will also result in future congested/contested environments, requiring spatially tracking/rejecting unknown blockers (unknown frequency, angle-of-arrival AoA, or modulation).","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"99 1","pages":"68-70"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85856578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310315
Long Xu, J. Huijsing, K. Makinwa
This paper presents a fully integrated ±4A current sensor that supports a 25V input common-mode voltage range (CMVR) while operating from a single 1.5V supply. It consists of an on-chip metal shunt, a beyond-the-rails ADC [1] and a temperature-dependent voltage reference. The beyond-the-rails ADC facilitates high-side current sensing without the need for external resistive dividers or level shifters, thus reducing power consumption and system complexity. To compensate for the shunt's temperature dependence, the ADC employs a proportional-to-absolute-temperature (PTAT) reference voltage. Compared to digital temperature compensation schemes [2,3], this analog scheme eliminates the need for a temperature sensor, a band-gap voltage reference and calibration logic. As a result, the current sensor draws only 10.9μA and is 10x more energy efficient than [2]. Over a ±4A range, and after a one-point trim, the sensor exhibits a 0.9% (max) gain error from −40°C to 85°C and a 0.05% gain error at room temperature. The former is comparable with that of other fully-integrated current sensors [2-4], while the latter represents the state-of-the-art.
{"title":"A ±4A high-side current sensor with 25V input CM range and 0.9% gain error from −40°C to 85°C using an analog temperature compensation technique","authors":"Long Xu, J. Huijsing, K. Makinwa","doi":"10.1109/ISSCC.2018.8310315","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310315","url":null,"abstract":"This paper presents a fully integrated ±4A current sensor that supports a 25V input common-mode voltage range (CMVR) while operating from a single 1.5V supply. It consists of an on-chip metal shunt, a beyond-the-rails ADC [1] and a temperature-dependent voltage reference. The beyond-the-rails ADC facilitates high-side current sensing without the need for external resistive dividers or level shifters, thus reducing power consumption and system complexity. To compensate for the shunt's temperature dependence, the ADC employs a proportional-to-absolute-temperature (PTAT) reference voltage. Compared to digital temperature compensation schemes [2,3], this analog scheme eliminates the need for a temperature sensor, a band-gap voltage reference and calibration logic. As a result, the current sensor draws only 10.9μA and is 10x more energy efficient than [2]. Over a ±4A range, and after a one-point trim, the sensor exhibits a 0.9% (max) gain error from −40°C to 85°C and a 0.05% gain error at room temperature. The former is comparable with that of other fully-integrated current sensors [2-4], while the latter represents the state-of-the-art.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"29 1","pages":"324-326"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86852172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310345
A. Seidel, B. Wicht
Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ∼1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.
{"title":"A fully integrated three-level 11.6nC gate driver supporting GaN gate injection transistors","authors":"A. Seidel, B. Wicht","doi":"10.1109/ISSCC.2018.8310345","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310345","url":null,"abstract":"Due to their superior fast-switching performance, GaN transistors show enormous potential to enable compact power electronics in applications like renewable energy, electrical cars and home appliances by shrinking down the size of passives. However, fast switching poses challenges for the gate driver. Since GaN transistors have a low threshold voltage Vt of ∼1V, an unintended driver turn-on can occur in case of a unipolar gate control as shown for a typical half-bridge in Fig. 24.2.1 (top left). This is due to coupling via the gate-drain capacitance (Miller coupling), when the low-side driver turns on, causing a peak current into the gate. This is usually tackled by applying a negative gate voltage to enhance the safety margin towards Vt, resulting in a bipolar gate-driving scheme. In many power-electronics applications GaN transistors operate in reverse conduction, carrying the inductor current during the dead time t, when the high-side and low-side switch are off (as illustrated at a high-side switch in Fig. 24.2.1, bottom left). As there is no real body diode as in silicon devices, the GaN transistor turns on in reverse operation with a voltage drop VF across the drain-source terminals (quasi-body diode behavior). As a negative gate voltage adds to VF, 63% higher reverse-conduction losses were measured for a typical GaN switch in bipolar gate-drive operation. This drawback is addressed by a three-level gate voltage (positive, 0V, negative), which at the same time provides robustness against unintended turn-on similar to the bipolar gate driver, proven in [1] for a discrete driver.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"26 1","pages":"384-386"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76013657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modulation schemes employed in long-term-evolution advanced (LTE-A) services for higher data-rate with high peak-to-average power ratios (PAPR) are becoming more complicated, which degrades the efficiency of RF power amplifiers (PA). Envelope-tracking modulators (ETM) have been proposed to improve the PA efficiency and linearity by dynamically adjusting the supply voltage of the RF PA according to the envelope of the transmitted signal.
{"title":"An 87.1% efficiency RF-PA envelope-tracking modulator for 80MHz LTE-Advanced transmitter and 31dBm PA output power for HPUE in 0.153μm CMOS","authors":"Chen-Yen Ho, Shih-Mei Lin, Che-Hao Meng, Hao-Ping Hong, Sheng-Hong Yan, Ting-Hsun Kuo, Chia-Sheng Peng, Chieh-Hsun Hsiao, Hsin-Hung Chen, D. Sung, Chien-Wei Kuan","doi":"10.1109/ISSCC.2018.8310369","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310369","url":null,"abstract":"Modulation schemes employed in long-term-evolution advanced (LTE-A) services for higher data-rate with high peak-to-average power ratios (PAPR) are becoming more complicated, which degrades the efficiency of RF power amplifiers (PA). Envelope-tracking modulators (ETM) have been proposed to improve the PA efficiency and linearity by dynamically adjusting the supply voltage of the RF PA according to the envelope of the transmitted signal.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"65 1","pages":"432-434"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79566419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310272
Shoubhik Karmakar, B. Gonen, F. Sebastiano, R. V. Veldhoven, K. Makinwa
Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.
{"title":"A 280μW dynamic-zoom ADC with 120dB DR and 118dB SNDR in 1kHz BW","authors":"Shoubhik Karmakar, B. Gonen, F. Sebastiano, R. V. Veldhoven, K. Makinwa","doi":"10.1109/ISSCC.2018.8310272","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310272","url":null,"abstract":"Micro-power ADCs with high linearity and dynamic range (DR) are required in several applications, such as smart sensors, biomedical imaging, and portable instrumentation. Since the signals of interest are then often small (tens of μν) and slow (<1kHz BW), such ADCs should also exhibit low offset and flicker noise. Noise-shaping SAR [1] and incremental ADCs [2] have been proposed for such applications, but their DR is limited to about 100dB. Although the ΔΣ modulator (ΔΣM) proposed in [3] achieves 136dB DR, it is at the expense of high power consumption (12.7mW). The incremental zoom ADC proposed in [4] combines a coarse SAR ADC and a fine ΔΣ ADC to efficiently achieve 119.8dB DR, but is limited to DC signals. The dynamic zoom ADC in [5] solves this problem, but requires external filtering to cope with out-of-band interference. This paper describes an interferer-robust dynamic zoom ADC that consumes 280μW while achieving 120.3dB DR and 118.1dB SNDR in 1kHz BW, resulting in a Schreier FoM of 185.8dB. It also achieves a maximum offset of 30μν and a 1/f corner of 7Hz. These advances are achieved by the combination of dynamic error-correction techniques, an asynchronous SAR ADC and a fully differential inverter-based ΔΣ ADC.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"49 1","pages":"238-240"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77289716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310290
Marc Erett, D. Carey, James Hudner, R. Casey, Kevin Geary, Pedro Neto, M. Raj, S. McLeod, Hongtao Zhang, A. Roldan, Hongyuan Zhao, P. Chiang, Haibing Zhao, Kee Hian Tan, Y. Frans, Ken Chang
The industry has recently proposed standards for synchronous high-speed interfaces targeting chip-to-chip communication across a very short PCB trace [1]. Figure 16.7.1 shows an example of such an interface. Eight 56Gb/s NRZ lanes provide a total of 448Gb/s aggregate bandwidth in each direction. The channel insertion loss and propagation delay varies from lane to lane, with a maximum insertion loss of 8dB at 28GHz from BGA to BGA. The routing inside the two packages adds an additional 3dB insertion loss at 28GHz. Taking advantage of the relatively low channel loss, the interface is expected to adopt simple transmitter/receiver circuits with low power consumption. However, a per-lane deskewing scheme is still required due to the propagation delay variations between lanes.
{"title":"A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET","authors":"Marc Erett, D. Carey, James Hudner, R. Casey, Kevin Geary, Pedro Neto, M. Raj, S. McLeod, Hongtao Zhang, A. Roldan, Hongyuan Zhao, P. Chiang, Haibing Zhao, Kee Hian Tan, Y. Frans, Ken Chang","doi":"10.1109/ISSCC.2018.8310290","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310290","url":null,"abstract":"The industry has recently proposed standards for synchronous high-speed interfaces targeting chip-to-chip communication across a very short PCB trace [1]. Figure 16.7.1 shows an example of such an interface. Eight 56Gb/s NRZ lanes provide a total of 448Gb/s aggregate bandwidth in each direction. The channel insertion loss and propagation delay varies from lane to lane, with a maximum insertion loss of 8dB at 28GHz from BGA to BGA. The routing inside the two packages adds an additional 3dB insertion loss at 28GHz. Taking advantage of the relatively low channel loss, the interface is expected to adopt simple transmitter/receiver circuits with low power consumption. However, a per-lane deskewing scheme is still required due to the propagation delay variations between lanes.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"38 1","pages":"274-276"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86956105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310263
Sungpill Choi, Jinsu Lee, K. Lee, H. Yoo
Recently, 3D hand-gesture recognition (HGR) has become an important feature in smart mobile devices, such as head-mounted displays (HMDs) or smartphones for AR/VR applications. A 3D HGR system in Fig. 13.4.1 enables users to interact with virtual 3D objects using depth sensing and hand tracking. However, a previous 3D HGR system, such as Hololens [1], utilized a power consuming time-of-flight (ToF) depth sensor (>2W) limiting 3D HGR operation to less than 3 hours. Even though stereo matching was used instead of ToF for depth sensing with low power consumption [2], it could not provide interaction with virtual 3D objects because depth information was used only for hand segmentation. The HGR-based UI system in smart mobile devices, such as HMDs, must be low power consumption (<10mW), while maintaining real-time operation (<33.3ms). A convolutional neural network (CNN) can be adopted to enhance the accuracy of the low-power stereo matching. The CNN-based HGR system comprises two 6-layer CNNs (stereo) without any pooling layers to preserve geometrical information and an iterative-closest-point/particle-swarm optimization-based (ICP-PSO) hand tracking to acquire 3D coordinates of a user's fingertips and palm from the hand depth. The CNN learns the skin color and texture to detect the hand accurately, comparable to ToF, in the low-power stereo matching system irrespective of variations in external conditions [3]. However, it requires >1000 more MAC operations than previous feature-based stereo depth sensing, which is difficult in real-time with a mobile CPU, and therefore, a dedicated low-power CNN-based stereo matching SoC is required.
{"title":"A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices","authors":"Sungpill Choi, Jinsu Lee, K. Lee, H. Yoo","doi":"10.1109/ISSCC.2018.8310263","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310263","url":null,"abstract":"Recently, 3D hand-gesture recognition (HGR) has become an important feature in smart mobile devices, such as head-mounted displays (HMDs) or smartphones for AR/VR applications. A 3D HGR system in Fig. 13.4.1 enables users to interact with virtual 3D objects using depth sensing and hand tracking. However, a previous 3D HGR system, such as Hololens [1], utilized a power consuming time-of-flight (ToF) depth sensor (>2W) limiting 3D HGR operation to less than 3 hours. Even though stereo matching was used instead of ToF for depth sensing with low power consumption [2], it could not provide interaction with virtual 3D objects because depth information was used only for hand segmentation. The HGR-based UI system in smart mobile devices, such as HMDs, must be low power consumption (<10mW), while maintaining real-time operation (<33.3ms). A convolutional neural network (CNN) can be adopted to enhance the accuracy of the low-power stereo matching. The CNN-based HGR system comprises two 6-layer CNNs (stereo) without any pooling layers to preserve geometrical information and an iterative-closest-point/particle-swarm optimization-based (ICP-PSO) hand tracking to acquire 3D coordinates of a user's fingertips and palm from the hand depth. The CNN learns the skin color and texture to detect the hand accurately, comparable to ToF, in the low-power stereo matching system irrespective of variations in external conditions [3]. However, it requires >1000 more MAC operations than previous feature-based stereo depth sensing, which is difficult in real-time with a mobile CPU, and therefore, a dedicated low-power CNN-based stereo matching SoC is required.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"141 1","pages":"220-222"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89027945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310360
Lorenzo Lotti, G. LaCaille, A. Niknejad
Multi-user multiple-input multiple-output (MIMO) systems are promising enablers for high-capacity wireless access in next-generation mobile networks. Leveraging antenna arrays at the access point, narrow beams can be steered to different users simultaneously, enhancing spectral efficiency through spatial multiplexing. By employing a number of array elements, M, much larger than the number of users, K, (i.e. massive MIMO), simple linear beamforming algorithms can achieve nearly optimal operation [1]. Operating massive MIMO systems at mm-waves results in compact antenna arrays and wide channel bandwidths. Within the available spectrum, the E-Band communication bandwidth (71 to 76GHz, 81 to 86GHz, and 92 to 95GHz) has recently gained attention for both access and wireless backhaul, due to low oxygen attenuation.
{"title":"A 12mW 70-to-100GHz mixer-first receiver front-end for mm-wave massive-MIMO arrays in 28nm CMOS","authors":"Lorenzo Lotti, G. LaCaille, A. Niknejad","doi":"10.1109/ISSCC.2018.8310360","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310360","url":null,"abstract":"Multi-user multiple-input multiple-output (MIMO) systems are promising enablers for high-capacity wireless access in next-generation mobile networks. Leveraging antenna arrays at the access point, narrow beams can be steered to different users simultaneously, enhancing spectral efficiency through spatial multiplexing. By employing a number of array elements, M, much larger than the number of users, K, (i.e. massive MIMO), simple linear beamforming algorithms can achieve nearly optimal operation [1]. Operating massive MIMO systems at mm-waves results in compact antenna arrays and wide channel bandwidths. Within the available spectrum, the E-Band communication bandwidth (71 to 76GHz, 81 to 86GHz, and 92 to 95GHz) has recently gained attention for both access and wireless backhaul, due to low oxygen attenuation.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"49 1","pages":"414-416"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90632215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310336
Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi
To address the increasing demand for high-bandwidth mobile communications, 5G technology is targeted to support data-rates up to 10Gb/s. To reach this goal, one of challenging tasks for wireless transceivers is to generate millimeter-wave (mmW) band Lo signals that have an ultra-low integrated phase noise (IPN). The IPN of an LO signal should be reduced to less than −30dBc to satisfy the EVM requirements of high-order modulations, such as 64-QAM. Figure 23.1.1 shows the frequency spectrum for cellular systems, including existing bands below 6GHz and new mmW bands for 5G. A key goal of the evolution of mobile communications is to ensure interoperability with past-generation standards, and this is expected to continue for 5G. Thus, LO generators eventually will be designed to cover existing bands as well as mmW bands. There are many PLLs that can generate mmW signals directly [1,2], but their ability to achieve low IPN is limited. This is because they are susceptible to increases in in-band phase noise due to their large division numbers and out-of-band phase noise due to the low Q-factors of mmW VCOs. They also require a significant amount of power to operate high-frequency circuits, such as frequency dividers. In addition, they must divide frequencies again to support bands below 6GHz, resulting in the consumption of additional power.
{"title":"A −31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers","authors":"Heein Yoon, Juyeop Kim, Suneui Park, Younghyun Lim, Yongsun Lee, Jooeun Bang, Kyoohyun Lim, Jaehyouk Choi","doi":"10.1109/ISSCC.2018.8310336","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310336","url":null,"abstract":"To address the increasing demand for high-bandwidth mobile communications, 5G technology is targeted to support data-rates up to 10Gb/s. To reach this goal, one of challenging tasks for wireless transceivers is to generate millimeter-wave (mmW) band Lo signals that have an ultra-low integrated phase noise (IPN). The IPN of an LO signal should be reduced to less than −30dBc to satisfy the EVM requirements of high-order modulations, such as 64-QAM. Figure 23.1.1 shows the frequency spectrum for cellular systems, including existing bands below 6GHz and new mmW bands for 5G. A key goal of the evolution of mobile communications is to ensure interoperability with past-generation standards, and this is expected to continue for 5G. Thus, LO generators eventually will be designed to cover existing bands as well as mmW bands. There are many PLLs that can generate mmW signals directly [1,2], but their ability to achieve low IPN is limited. This is because they are susceptible to increases in in-band phase noise due to their large division numbers and out-of-band phase noise due to the low Q-factors of mmW VCOs. They also require a significant amount of power to operate high-frequency circuits, such as frequency dividers. In addition, they must divide frequencies again to support bands below 6GHz, resulting in the consumption of additional power.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"50 1","pages":"366-368"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90727024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310269
H. Chandrakumar, D. Markovic
Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to advance deep brain stimulation (DBS) therapies. However, stimulation generates large artifacts (∼100mV) at the recording sites that saturate traditional front-ends. We present a 15.2b-ENOB CT ΔΣΜ with 187dB FOM, which along with an 8x-gain capacitively coupled chopper instrumentation amplifier (CCIA), realizes a front-end that can digitize neural signals (<2mVpp) from 1Hz to 5kHz in the presence of 200mVpp artifacts. Neural recording front-ends need to function within a power budget of 10μW/ch, input-referred noise of 4–8μVrms in 1Hz-5kHz, DC input impedance Zin, DC>1GΩ and high-pass (HP) cutoff <1Hz [1]. Prior work has addressed power and noise [1]-[2], but has limited dynamic-range and bandwidth (BW), making them incapable of performing true closed-loop operation.
{"title":"A 15.2-ENOB continuous-time ΔΣ ADC for a 200mVpp-linear-input-range neural recording front-end","authors":"H. Chandrakumar, D. Markovic","doi":"10.1109/ISSCC.2018.8310269","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310269","url":null,"abstract":"Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to advance deep brain stimulation (DBS) therapies. However, stimulation generates large artifacts (∼100mV) at the recording sites that saturate traditional front-ends. We present a 15.2b-ENOB CT ΔΣΜ with 187dB FOM, which along with an 8x-gain capacitively coupled chopper instrumentation amplifier (CCIA), realizes a front-end that can digitize neural signals (<2mV<inf>pp</inf>) from 1Hz to 5kHz in the presence of 200mV<inf>pp</inf> artifacts. Neural recording front-ends need to function within a power budget of 10μW/ch, input-referred noise of 4–8μV<inf>rms</inf> in 1Hz-5kHz, DC input impedance Z<inf>in, DC</inf>>1GΩ and high-pass (HP) cutoff <1Hz [1]. Prior work has addressed power and noise [1]-[2], but has limited dynamic-range and bandwidth (BW), making them incapable of performing true closed-loop operation.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"34 1","pages":"232-234"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87994104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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