Pub Date : 2018-02-14DOI: 10.1109/ISSCC.2018.8310390
D. Jang, Seonghwan Cho
Photoplethysmogram (PPG) sensors have gained great popularity in recent years as they can easily obtain heart rate (HR) in wearable devices such as smart watches and smart rings. However, one of the biggest problems for PPG sensors is their large power consumption, as wearable devices are highly limited in its battery capacity. The power consumption of a PPG sensor is typically dominated by the LED driver, which requires several to a few tens of mA of current. Thus, many previous works are aimed at reducing the LED driver power [1-5]. The most widely used method is duty-cycling the LED by using a train of discrete pulses instead of always turning on the LED [1-4]. As a PPG signal has low bandwidth, the duty-cycle ratio of the LED can be as low as 1%. Another low-power method is compressive sampling, which exploits the sparse nature of PPG signals [5]. Although it can reduce the effective duty-cycle ratio down to 0.0125%, a critical problem is that a large power consumption is required in reconstructing the compressive-sampled signal. In this work, we present an ultra-low-power PPG sensor with a heartbeat-locked loop (HBLL) that turns on the LED only during the PPG peaks and thus achieves an effective duty cycle of 0.0175%. We also reduce the power consumption of the analog front-end (AFE) by using the HBLL, which is in contrast to previous works where AFE power is not duty-cycled. A prototype implemented in 0.18μm CMOS demonstrates 43.4μW of total power consumption with less than 2.1bpm error in heart rate.
{"title":"A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop","authors":"D. Jang, Seonghwan Cho","doi":"10.1109/ISSCC.2018.8310390","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310390","url":null,"abstract":"Photoplethysmogram (PPG) sensors have gained great popularity in recent years as they can easily obtain heart rate (HR) in wearable devices such as smart watches and smart rings. However, one of the biggest problems for PPG sensors is their large power consumption, as wearable devices are highly limited in its battery capacity. The power consumption of a PPG sensor is typically dominated by the LED driver, which requires several to a few tens of mA of current. Thus, many previous works are aimed at reducing the LED driver power [1-5]. The most widely used method is duty-cycling the LED by using a train of discrete pulses instead of always turning on the LED [1-4]. As a PPG signal has low bandwidth, the duty-cycle ratio of the LED can be as low as 1%. Another low-power method is compressive sampling, which exploits the sparse nature of PPG signals [5]. Although it can reduce the effective duty-cycle ratio down to 0.0125%, a critical problem is that a large power consumption is required in reconstructing the compressive-sampled signal. In this work, we present an ultra-low-power PPG sensor with a heartbeat-locked loop (HBLL) that turns on the LED only during the PPG peaks and thus achieves an effective duty cycle of 0.0175%. We also reduce the power consumption of the analog front-end (AFE) by using the HBLL, which is in contrast to previous works where AFE power is not duty-cycled. A prototype implemented in 0.18μm CMOS demonstrates 43.4μW of total power consumption with less than 2.1bpm error in heart rate.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"5 1","pages":"474-476"},"PeriodicalIF":0.0,"publicationDate":"2018-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84282235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-14DOI: 10.1109/ISSCC.2018.8310368
Se-un Shin, Yeunhee Huh, Yong-Min Ju, Sung-Won Choi, Changsik Shin, Young-Jin Woo, Minseong Choi, Se-Hong Park, Young-Hoon Sohn, Min-Woo Ko, Youngsin Jo, Hyunki Han, Hyung-Min Lee, Sung-Wan Hong, W. Qu, G. Cho
DC-DC boost converters are widely used to increase the supply voltage in various applications, including LED drivers, energy harvesting, etc. [1-5]. The conventional boost converter (CBC) is shown in Fig. 27.5.1, where the switches S1 and S2 are turned on and off alternately at φ1 and φ2, respectively, and the inductor current (IL) is built up and delivered to the output. There are some critical issues in CBC because the output delivery current (IS) is not continuous. As a result, the IL can be much larger than the load current (ILOAD) as φ1 becomes longer. Since a bulky-size inductor having a low parasitic DC resistance (Rdcr) is not usable for mobile applications with a strictly limited space, this large IL results in significant conduction loss in the large RDCR of a small-size inductor. Another issue is that the discontinuous IS in φ2 causes large voltage ripple (AVOUT) at the output. Moreover, switching spike voltages can cause over-voltage stress on the loading block due to large di/dt of IS combined with parasitic inductances of the GND path.
{"title":"A 95.2% efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple","authors":"Se-un Shin, Yeunhee Huh, Yong-Min Ju, Sung-Won Choi, Changsik Shin, Young-Jin Woo, Minseong Choi, Se-Hong Park, Young-Hoon Sohn, Min-Woo Ko, Youngsin Jo, Hyunki Han, Hyung-Min Lee, Sung-Wan Hong, W. Qu, G. Cho","doi":"10.1109/ISSCC.2018.8310368","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310368","url":null,"abstract":"DC-DC boost converters are widely used to increase the supply voltage in various applications, including LED drivers, energy harvesting, etc. [1-5]. The conventional boost converter (CBC) is shown in Fig. 27.5.1, where the switches S<inf>1</inf> and S<inf>2</inf> are turned on and off alternately at φ<inf>1</inf> and φ<inf>2</inf>, respectively, and the inductor current (I<inf>L</inf>) is built up and delivered to the output. There are some critical issues in CBC because the output delivery current (I<inf>S</inf>) is not continuous. As a result, the I<inf>L</inf> can be much larger than the load current (I<inf>LOAD</inf>) as φ<inf>1</inf> becomes longer. Since a bulky-size inductor having a low parasitic DC resistance (R<inf>dcr</inf>) is not usable for mobile applications with a strictly limited space, this large I<inf>L</inf> results in significant conduction loss in the large R<inf>DCR</inf> of a small-size inductor. Another issue is that the discontinuous I<inf>S</inf> in φ<inf>2</inf> causes large voltage ripple (AV<inf>OUT</inf>) at the output. Moreover, switching spike voltages can cause over-voltage stress on the loading block due to large di/dt of I<inf>S</inf> combined with parasitic inductances of the GND path.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"46 1","pages":"430-432"},"PeriodicalIF":0.0,"publicationDate":"2018-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80968679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-14DOI: 10.1109/ISSCC.2018.8310230
Se-un Shin, Minseong Choi, Seok-Tae Koh, Yu-Jin Yang, Seungchul Jung, Young-Hoon Sohn, Se-Hong Park, Yong-Min Ju, Youngsin Jo, Yeunhee Huh, Sung-Won Choi, Sang Joon Kim, G. Cho
Wireless power transfer (WPT) has been widely adopted in various applications, such as biomedical implants and wireless sensors. A conventional voltage-mode receiver (VM-RX) uses a rectifier or a doubler for AC-DC conversion [1,2]. This requires a sufficiently large input power (P,N) inducing a large voltage (VAC) in the LC tank of the receiver (RX) due to the limited voltage conversion efficiency. A subordinate DC-DC converter is also required for voltage regulation or battery charging, which reduces the overall power-conversion efficiency (PCE) due to the 2-stage structure. To overcome these limitations, the resonant current-mode receiver (RCM-RX) has been proposed for direct battery charging [3] and voltage regulation [4,5]. The RCM-RX has two operation phases: a resonance phase (PHre) that accumulates energy in the LC tank during optimal resonant cycles (NOPT) to track the maximum efficiency [3], and a charging phase (PHch) that delivers the energy of the LC tank to the output, when the resonant current (IAC) is at its peak. However, the RCM-RX typically operates at low resonant frequency fRESO (50kHz to 1MHz) because it is challenging to accurately detect the peak timing of IAC due to the intrinsic delay and offset of the comparator used in the peak timing detector. Operating at low fRESO causes the coil size to increase, making a burden on a size-constrained implant. In addition, the RCM-RX has a LC-tank resonance-loss interval PHch, which hinders optimal power transfer from the transmitter (TX) to the RX because the reactive impedance is not cancelled out but appears on the TX side. Because the LC tank and the output are not isolated during PHch, the power-transfer efficiency (PTE) can also be affected by load variation, such as the battery-voltage (VBAT) variation. These problems become worse as NOPT is reduced to lower number.
{"title":"A 13.56MHz time-interleaved resonant-voltage-mode wireless-power receiver with isolated resonator and quasi-resonant boost converter for implantable systems","authors":"Se-un Shin, Minseong Choi, Seok-Tae Koh, Yu-Jin Yang, Seungchul Jung, Young-Hoon Sohn, Se-Hong Park, Yong-Min Ju, Youngsin Jo, Yeunhee Huh, Sung-Won Choi, Sang Joon Kim, G. Cho","doi":"10.1109/ISSCC.2018.8310230","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310230","url":null,"abstract":"Wireless power transfer (WPT) has been widely adopted in various applications, such as biomedical implants and wireless sensors. A conventional voltage-mode receiver (VM-RX) uses a rectifier or a doubler for AC-DC conversion [1,2]. This requires a sufficiently large input power (P,N) inducing a large voltage (VAC) in the LC tank of the receiver (RX) due to the limited voltage conversion efficiency. A subordinate DC-DC converter is also required for voltage regulation or battery charging, which reduces the overall power-conversion efficiency (PCE) due to the 2-stage structure. To overcome these limitations, the resonant current-mode receiver (RCM-RX) has been proposed for direct battery charging [3] and voltage regulation [4,5]. The RCM-RX has two operation phases: a resonance phase (PHre) that accumulates energy in the LC tank during optimal resonant cycles (NOPT) to track the maximum efficiency [3], and a charging phase (PHch) that delivers the energy of the LC tank to the output, when the resonant current (IAC) is at its peak. However, the RCM-RX typically operates at low resonant frequency fRESO (50kHz to 1MHz) because it is challenging to accurately detect the peak timing of IAC due to the intrinsic delay and offset of the comparator used in the peak timing detector. Operating at low fRESO causes the coil size to increase, making a burden on a size-constrained implant. In addition, the RCM-RX has a LC-tank resonance-loss interval PHch, which hinders optimal power transfer from the transmitter (TX) to the RX because the reactive impedance is not cancelled out but appears on the TX side. Because the LC tank and the output are not isolated during PHch, the power-transfer efficiency (PTE) can also be affected by load variation, such as the battery-voltage (VBAT) variation. These problems become worse as NOPT is reduced to lower number.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"19 1","pages":"154-156"},"PeriodicalIF":0.0,"publicationDate":"2018-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81503738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-14DOI: 10.1109/ISSCC.2018.8310367
Min-Woo Ko, Kiduk Kim, Young-Jin Woo, Se-un Shin, Hyunki Han, Yeunhee Huh, Gyeong-Gu Kang, Jeong-Hyun Cho, Sangjin Lim, Se-Hong Park, Hyung-Min Lee, G. Cho
Lithium-ion batteries are generally used in mobile devices, but the voltage range of the battery varies from 2.7 to 4.2V. To provide a mid-3V-range output from the battery, a converter capable of step-up/down-conversion is necessary. For this purpose, non-inverting buck-boost topologies with multimode control [1-3] have been widely used. However, they have limited efficiency slightly higher than 90%, which comes from the fact that a main current path always encompasses two switches. To increase the efficiency in the buck mode where the converter operates for most of the usage time, a flying capacitor buck-boost (FCBB) was proposed in [4]. Despite its high power efficiency, it requires large-size LDMOS to endure a large voltage range up to 8V at switching node, resulting in cost inefficiency. Since all these topologies have a common controller that covers both buck and boost modes of operation, compensator design is challenging. Moreover, a non-minimum-phase system of boost operation makes it hard to achieve a fast loop response. In this paper, we propose a step-up/down DC-DC converter based on buck operation only over the whole input voltage range, which greatly simplifies the controller design and consequently gives fast response. Furthermore, it achieves high efficiency because of the reduced effective resistance on the main current path.
{"title":"A 97% high-efficiency 6μs fast-recovery-time buck-based step-up/down converter with embedded 1/2 and 3/2 charge-pumps for li-lon battery management","authors":"Min-Woo Ko, Kiduk Kim, Young-Jin Woo, Se-un Shin, Hyunki Han, Yeunhee Huh, Gyeong-Gu Kang, Jeong-Hyun Cho, Sangjin Lim, Se-Hong Park, Hyung-Min Lee, G. Cho","doi":"10.1109/ISSCC.2018.8310367","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310367","url":null,"abstract":"Lithium-ion batteries are generally used in mobile devices, but the voltage range of the battery varies from 2.7 to 4.2V. To provide a mid-3V-range output from the battery, a converter capable of step-up/down-conversion is necessary. For this purpose, non-inverting buck-boost topologies with multimode control [1-3] have been widely used. However, they have limited efficiency slightly higher than 90%, which comes from the fact that a main current path always encompasses two switches. To increase the efficiency in the buck mode where the converter operates for most of the usage time, a flying capacitor buck-boost (FCBB) was proposed in [4]. Despite its high power efficiency, it requires large-size LDMOS to endure a large voltage range up to 8V at switching node, resulting in cost inefficiency. Since all these topologies have a common controller that covers both buck and boost modes of operation, compensator design is challenging. Moreover, a non-minimum-phase system of boost operation makes it hard to achieve a fast loop response. In this paper, we propose a step-up/down DC-DC converter based on buck operation only over the whole input voltage range, which greatly simplifies the controller design and consequently gives fast response. Furthermore, it achieves high efficiency because of the reduced effective resistance on the main current path.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"49 1","pages":"428-430"},"PeriodicalIF":0.0,"publicationDate":"2018-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82746268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-14DOI: 10.1109/ISSCC.2018.8310389
Sehwan Lee, Arup K. George, Taeju Lee, Jun-Uk Chu, Sungmin Han, Ji-Hoon Kim, M. Je, Junghyup Lee
Multi-channel neural-recording amplifier systems have evolved into the method of choice for analyzing neurophysiological behavior, and are leading to a deeper understanding of the human brain [1-4]. Such systems operate from a noisy supply and ground, especially when they are powered wirelessly. As shown in Fig. 29.7.1, the amplifiers ought to be low-noise, low-power, and resilient against environmental noise and interferences that are capacitively coupled from the power lines (220V/60Hz). Specifications-wise, these requirements translate into high CMRR, TCMRR, and PSRR. TCMRR (total CMRR) is a more realistic specification than CMRR as it includes the effect of the impedances of both electrodes (Ze) and the amplifier input (ZCin) as well. In fact, the TCMRR should be >70dB for reliable detection of a 5μVrms neural signal [1].
{"title":"A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS","authors":"Sehwan Lee, Arup K. George, Taeju Lee, Jun-Uk Chu, Sungmin Han, Ji-Hoon Kim, M. Je, Junghyup Lee","doi":"10.1109/ISSCC.2018.8310389","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310389","url":null,"abstract":"Multi-channel neural-recording amplifier systems have evolved into the method of choice for analyzing neurophysiological behavior, and are leading to a deeper understanding of the human brain [1-4]. Such systems operate from a noisy supply and ground, especially when they are powered wirelessly. As shown in Fig. 29.7.1, the amplifiers ought to be low-noise, low-power, and resilient against environmental noise and interferences that are capacitively coupled from the power lines (220V/60Hz). Specifications-wise, these requirements translate into high CMRR, TCMRR, and PSRR. TCMRR (total CMRR) is a more realistic specification than CMRR as it includes the effect of the impedances of both electrodes (Ze) and the amplifier input (ZCin) as well. In fact, the TCMRR should be >70dB for reliable detection of a 5μVrms neural signal [1].","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"7 1","pages":"472-474"},"PeriodicalIF":0.0,"publicationDate":"2018-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78414067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-13DOI: 10.1109/ISSCC.2018.8310249
Kiduk Kim, Seunghyun Park, K. Yoon, Gyeong-Gu Kang, Hyunki Han, Jieun Choi, Min-Woo Ko, Jeong-Hyun Cho, Sangjin Lim, Hyung-Min Lee, Hyunsik Kim, Kwyro Lee, G. Cho
A micro-bolometer focal plane array (MBFPA) detector is one of the best candidates for thermal imaging cameras due to its excellent uncooled imaging performance with low manufacturing cost [1-4]. In Fig. 10.8.1, remote infra-red signals from thermal objects are maximized and absorbed at the MEMS micro-bolometer pixels having a λ/4 cavity structure, and they are then converted into resistance of a thermistor layer in each cell. Then, a CMOS analog front-end (AFE) reads out the cell resistance value in current-mode by applying a voltage bias to the micro-bolometer pixel. In the readout process, the skimming cell that does not respond to the infra-red signal is used to remove the offset components by generating an opposite-phase current, which in turn alleviates the system required resolution. Nevertheless, there is still very significant fixed-pattern noise (FPN) resulting from process, voltage, and temperature (PVT) variations, and this severely limits the responsivity/dynamic range trade-off. Addressing the problem, both bias voltages (VFID & VGSK) applied to sensing and skimming cells, respectively, should be precisely adjusted so as to avoid any saturation while maintaining sufficient responsivity, and their noise levels must be low enough considering the noise amplification in the signal chain.
{"title":"A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm2 1.89μVrms noise 12b biasing DAC","authors":"Kiduk Kim, Seunghyun Park, K. Yoon, Gyeong-Gu Kang, Hyunki Han, Jieun Choi, Min-Woo Ko, Jeong-Hyun Cho, Sangjin Lim, Hyung-Min Lee, Hyunsik Kim, Kwyro Lee, G. Cho","doi":"10.1109/ISSCC.2018.8310249","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310249","url":null,"abstract":"A micro-bolometer focal plane array (MBFPA) detector is one of the best candidates for thermal imaging cameras due to its excellent uncooled imaging performance with low manufacturing cost [1-4]. In Fig. 10.8.1, remote infra-red signals from thermal objects are maximized and absorbed at the MEMS micro-bolometer pixels having a λ/4 cavity structure, and they are then converted into resistance of a thermistor layer in each cell. Then, a CMOS analog front-end (AFE) reads out the cell resistance value in current-mode by applying a voltage bias to the micro-bolometer pixel. In the readout process, the skimming cell that does not respond to the infra-red signal is used to remove the offset components by generating an opposite-phase current, which in turn alleviates the system required resolution. Nevertheless, there is still very significant fixed-pattern noise (FPN) resulting from process, voltage, and temperature (PVT) variations, and this severely limits the responsivity/dynamic range trade-off. Addressing the problem, both bias voltages (VFID & VGSK) applied to sensing and skimming cells, respectively, should be precisely adjusted so as to avoid any saturation while maintaining sufficient responsivity, and their noise levels must be low enough considering the noise amplification in the signal chain.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"11 1","pages":"192-194"},"PeriodicalIF":0.0,"publicationDate":"2018-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86128407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Directly modulated lasers (DMLs) are widely employed in medium-reach optical links owing to their simplicity and cost effectiveness. However, the chirp phenomenon under direct modulation limits the reach (2–10km) in a standard single-mode fiber (SMF). Although diverse optical-domain chirp-management techniques have been studied [1], excessive cost and installation difficulties have limited their widespread use. Therefore, external modulation schemes are predominant in applications requiring extended-reach, despite their high cost and power dissipation. Recently, an electronic dispersion compensation (EDC) IC has been reported to compensate for the chirp-induced dispersion (adiabatic chirp) of a 6Gb/s DML [2,3]. However, such a technique cannot be applied to high-speed (>10Gb/s) DML applications since spectral broadening caused by transient chirp dominates in high-speed links. In this paper, an adaptive EDC-based CDR IC compensating for both adiabatic and transient chirp in DMLs is proposed to help extend the reach of both 10Gb/s and 28Gb/s optical links.
{"title":"A 28Gb/s transceiver with chirp-managed EDC for DML systems","authors":"Kyeongha Kwon, Jong-Hyeok Yoon, Hanho Choi, Younho Jeon, Jaehyeok Yang, Bongjin Kim, Soon-Won Kwon, Minsik Kim, Sejun Jeon, Hyosup Won, Hyeon-Min Bae","doi":"10.1109/ISSCC.2018.8310285","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310285","url":null,"abstract":"Directly modulated lasers (DMLs) are widely employed in medium-reach optical links owing to their simplicity and cost effectiveness. However, the chirp phenomenon under direct modulation limits the reach (2–10km) in a standard single-mode fiber (SMF). Although diverse optical-domain chirp-management techniques have been studied [1], excessive cost and installation difficulties have limited their widespread use. Therefore, external modulation schemes are predominant in applications requiring extended-reach, despite their high cost and power dissipation. Recently, an electronic dispersion compensation (EDC) IC has been reported to compensate for the chirp-induced dispersion (adiabatic chirp) of a 6Gb/s DML [2,3]. However, such a technique cannot be applied to high-speed (>10Gb/s) DML applications since spectral broadening caused by transient chirp dominates in high-speed links. In this paper, an adaptive EDC-based CDR IC compensating for both adiabatic and transient chirp in DMLs is proposed to help extend the reach of both 10Gb/s and 28Gb/s optical links.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"2017 1","pages":"264-266"},"PeriodicalIF":0.0,"publicationDate":"2018-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74035632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-13DOI: 10.1109/ISSCC.2018.8310289
Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, J. Sim, Hong-June Park, Byungsub Kim
Compact transceivers (TRXs) for highly reflective (HR) interconnects are strongly demanded by the memory industry. Although discontinuous reflective channels like multi-drop DRAM interfaces are less suitable for high data rates than continuous point-to-point channels, their great advantages in high capacity, high throughput, and low latency attract the market [1-3]. However, compact TRXs for low-loss HR channels are more challenging than for high-loss low-reflection (LR) channels. Although the long-tail ISI of a high-loss LR channel can be cost-efficiently canceled by an FFE with a few taps or a DFE with IIR feedback (DFE-IIR) [4], the irregular ISI of a low-loss HR channel requires many DFE taps [2], demanding unacceptably large hardware cost and power dissipation. As an alternative solution, a multi-tone (MT) TRX was proposed to avoid a notch of the frequency response [3], but it is also very costly for HR channels with many notches. This paper proposes a 7.8Gb/s/pin compact single-ended (SE) TRX with simple clock data recovery (CDR) using phase-difference modulation (PDM) for HR memory interfaces. For reliable operation of the TRX/CDR, a phase-difference amplifier (PDA) is also proposed to satisfy its stringent timing requirement.
{"title":"A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces","authors":"Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, J. Sim, Hong-June Park, Byungsub Kim","doi":"10.1109/ISSCC.2018.8310289","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310289","url":null,"abstract":"Compact transceivers (TRXs) for highly reflective (HR) interconnects are strongly demanded by the memory industry. Although discontinuous reflective channels like multi-drop DRAM interfaces are less suitable for high data rates than continuous point-to-point channels, their great advantages in high capacity, high throughput, and low latency attract the market [1-3]. However, compact TRXs for low-loss HR channels are more challenging than for high-loss low-reflection (LR) channels. Although the long-tail ISI of a high-loss LR channel can be cost-efficiently canceled by an FFE with a few taps or a DFE with IIR feedback (DFE-IIR) [4], the irregular ISI of a low-loss HR channel requires many DFE taps [2], demanding unacceptably large hardware cost and power dissipation. As an alternative solution, a multi-tone (MT) TRX was proposed to avoid a notch of the frequency response [3], but it is also very costly for HR channels with many notches. This paper proposes a 7.8Gb/s/pin compact single-ended (SE) TRX with simple clock data recovery (CDR) using phase-difference modulation (PDM) for HR memory interfaces. For reliable operation of the TRX/CDR, a phase-difference amplifier (PDA) is also proposed to satisfy its stringent timing requirement.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"105 1","pages":"272-274"},"PeriodicalIF":0.0,"publicationDate":"2018-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91224116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-12DOI: 10.1109/ISSCC.2018.8310265
Wei Tang, H. Prabhu, Liang Liu, V. Öwall, Zhengya Zhang
This work presents a 2.0mm2 128×16 massive MIMO detector IC that provides 21dB array gain and 16x multiplexing gain at the system level. The detector implements iterative expectation-propagation detection (EPD) for up to 256-QAM modulation. Tested with measured channel data [1], the detector achieves 4.3dB processing gain over state-of-the-art massive MlMo detectors [2, 3], enabling 2.7x reduction in transmit power for battery-powered mobile terminals. The iC uses link-adaptive processing to meet a variety of practical channel conditions with scalable energy consumption. The design is realized in a condensed systolic array architecture and an approximate moment-matching circuitry to reach 1.8Gb/s at 70.6pJ/b. The performance and energy efficiency can be tuned over a wide range by UTBB-FDSOI body bias.
{"title":"A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI","authors":"Wei Tang, H. Prabhu, Liang Liu, V. Öwall, Zhengya Zhang","doi":"10.1109/ISSCC.2018.8310265","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310265","url":null,"abstract":"This work presents a 2.0mm2 128×16 massive MIMO detector IC that provides 21dB array gain and 16x multiplexing gain at the system level. The detector implements iterative expectation-propagation detection (EPD) for up to 256-QAM modulation. Tested with measured channel data [1], the detector achieves 4.3dB processing gain over state-of-the-art massive MlMo detectors [2, 3], enabling 2.7x reduction in transmit power for battery-powered mobile terminals. The iC uses link-adaptive processing to meet a variety of practical channel conditions with scalable energy consumption. The design is realized in a condensed systolic array architecture and an approximate moment-matching circuitry to reach 1.8Gb/s at 70.6pJ/b. The performance and energy efficiency can be tuned over a wide range by UTBB-FDSOI body bias.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"62 1","pages":"224-226"},"PeriodicalIF":0.0,"publicationDate":"2018-02-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80997482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-11DOI: 10.1109/ISSCC.2018.8310362
P. Hillger, R. Jain, J. Grzyb, L. Mavarani, B. Heinemann, G. MacGrogan, P. Mounaix, T. Zimmer, U. Pfeiffer
Real-time terahertz video cameras are regarded as key enabler systems for numerous applications. Unfortunately, their spatial resolution is fundamentally restricted by the diffraction limit. Near-field-scanning optical microscopy (NSOM) is used in the THz domain to break through this limit [1]. Recently reported THz near-field sensors based on silicon technology promise significant improvements compared to NSOM with respect to sensor sensitivity, system cost, and scanning time [2,3]. However, only single-pixel implementations have been presented with unmodulated CW sources so far, which limits the sensors dynamic range (DR) due to detector 1/f noise. This paper scales-up the research of near-field sensing into larger surfaces made of a plurality of super-resolution pixels with video-rate imaging capabilities. The 128-pixel 0.56THz imaging array includes all functions such as illumination, sensing, detection, and digital readout on a single silicon chip.
{"title":"A 128-pixel 0.56THz sensing array for real-time near-field imaging in 0.13μm SiGe BiCMOS","authors":"P. Hillger, R. Jain, J. Grzyb, L. Mavarani, B. Heinemann, G. MacGrogan, P. Mounaix, T. Zimmer, U. Pfeiffer","doi":"10.1109/ISSCC.2018.8310362","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310362","url":null,"abstract":"Real-time terahertz video cameras are regarded as key enabler systems for numerous applications. Unfortunately, their spatial resolution is fundamentally restricted by the diffraction limit. Near-field-scanning optical microscopy (NSOM) is used in the THz domain to break through this limit [1]. Recently reported THz near-field sensors based on silicon technology promise significant improvements compared to NSOM with respect to sensor sensitivity, system cost, and scanning time [2,3]. However, only single-pixel implementations have been presented with unmodulated CW sources so far, which limits the sensors dynamic range (DR) due to detector 1/f noise. This paper scales-up the research of near-field sensing into larger surfaces made of a plurality of super-resolution pixels with video-rate imaging capabilities. The 128-pixel 0.56THz imaging array includes all functions such as illumination, sensing, detection, and digital readout on a single silicon chip.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"31 1","pages":"418-420"},"PeriodicalIF":0.0,"publicationDate":"2018-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76427690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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