Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310197
Po-Sheng Chou, Chin-Hao Chang, M. Mhala, C. Liu, C. Chao, Chiao-Yi Huang, H. Tu, T. Wu, Shang-Fu Yeh, Seiji Takahashi, Yi-Min Huang
Slow-motion video is a desirable feature for state-of-art smartphones. The effect is achieved by capturing a video at a higher frame rate and playing it back at a lower frame rate. While the still-image resolution of smartphone cameras ranges from 8MP to 25MP, standard videos are limited to 3 formats: 3840×2160 (4K2K, 2160p), 1920×1080 (Full High Definition, FHD, 1080p), and 1280×720 (High Definition, HD, 720p). CMOS image sensors using various column-parallel aDc architectures have been reported to reach high frame rates [1-5]. The single-slope (SS) ADC is an attractive choice for a balanced performance among high speed, low noise, small area, and low power consumption. However, in conventional SS ADC design, each ADC is hardwired to a column signal line. ADCs for skipped columns are left idle during the subsampling operation, and the potential to reach higher frame rate is not optimized. In this paper, we develop an approach in which all the column ADCs are fully utilized in both of the 2-to-1 and 3-to-1 subsampling modes, such that the maximum of 4x faster FHD and 9x faster HD videos are demonstrated with reference to the 1-to-1 non-subsampled 4K2K video.
{"title":"A 1.1μm-Pitch 13.5Mpixel 3D-stacked CMOS image sensor featuring 230fps full-high-definition and 514fps high-definition videos by reading 2 or 3 rows simultaneously using a column-switching matrix","authors":"Po-Sheng Chou, Chin-Hao Chang, M. Mhala, C. Liu, C. Chao, Chiao-Yi Huang, H. Tu, T. Wu, Shang-Fu Yeh, Seiji Takahashi, Yi-Min Huang","doi":"10.1109/ISSCC.2018.8310197","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310197","url":null,"abstract":"Slow-motion video is a desirable feature for state-of-art smartphones. The effect is achieved by capturing a video at a higher frame rate and playing it back at a lower frame rate. While the still-image resolution of smartphone cameras ranges from 8MP to 25MP, standard videos are limited to 3 formats: 3840×2160 (4K2K, 2160p), 1920×1080 (Full High Definition, FHD, 1080p), and 1280×720 (High Definition, HD, 720p). CMOS image sensors using various column-parallel aDc architectures have been reported to reach high frame rates [1-5]. The single-slope (SS) ADC is an attractive choice for a balanced performance among high speed, low noise, small area, and low power consumption. However, in conventional SS ADC design, each ADC is hardwired to a column signal line. ADCs for skipped columns are left idle during the subsampling operation, and the potential to reach higher frame rate is not optimized. In this paper, we develop an approach in which all the column ADCs are fully utilized in both of the 2-to-1 and 3-to-1 subsampling modes, such that the maximum of 4x faster FHD and 9x faster HD videos are demonstrated with reference to the 1-to-1 non-subsampled 4K2K video.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"25 1","pages":"88-90"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86967254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310300
Jiawei Xu, M. Konijnenburg, Budi Lukita, Shuang Song, Hyunsoo Ha, Roland Van Wegberg, E. Sheikhi, M. Mazzillo, G. Fallica, W. Raedt, C. Hoof, N. V. Helleputte
Functional brain imaging is considered a powerful and practical solution for understanding the brain and neurological diseases. While EEG is an established method for non-invasive electrical activity, electrical-impedance tomography (EIT) and near-infrared spectroscopy (NIRS) can additionally measure impedance changes and hemodynamic processes. To facilitate long-term multi-channel brain imaging in a wearable form factor without cabling overhead, there is a need for low-power local amplifiers [1] to support all these modalities. The main principle of optical hemodynamic measurements is to send light pulses into the tissue and measure the reflected light, which is modulated by the oxygen levels in the blood (Fig. 17.8.1). State-of-the-art NIRS ICs typically consume a few mW, primarily for the LEDs to meet the required light sensitivity at the photodiodes (PDs). Silicon photomultipliers (SiPMs) are promising alternatives because they have excellent low-light detection capabilities, speed of response and higher detection efficiency in both visible and near infrared range [2]. Hence, SiPMs allow deeper brain sensing depth and the possibility to sample consistent cerebral regions with larger inter-optode distance. This benefit would significantly reduce the number of NIRS channels and the associated power for a wearable NIRS device. Although SiPMs require a higher bias voltage (∼30V) than PDs, they achieve similar NIRS responses with a few hundred times less LED current. This results in a low-power NIRS ASIC and an overall power-efficient system. Existing optical sensing ICs are not suitable for a SiPM because of its large and variable output current. Trimming-based calibration methods [3] suffer from drift over time. Auto-zeroing by swapping an integrator capacitor [4][5] compensates ambient light at the cost of the integrator's headroom. Apart from ambient light, the dynamic range (DR) of the amplifier is also limited by a large NIRS signal, leading to a power-hungry readout.
{"title":"A 665μW silicon photomultiplier-based NIRS/EEG/EIT monitoring asic for wearable functional brain imaging","authors":"Jiawei Xu, M. Konijnenburg, Budi Lukita, Shuang Song, Hyunsoo Ha, Roland Van Wegberg, E. Sheikhi, M. Mazzillo, G. Fallica, W. Raedt, C. Hoof, N. V. Helleputte","doi":"10.1109/ISSCC.2018.8310300","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310300","url":null,"abstract":"Functional brain imaging is considered a powerful and practical solution for understanding the brain and neurological diseases. While EEG is an established method for non-invasive electrical activity, electrical-impedance tomography (EIT) and near-infrared spectroscopy (NIRS) can additionally measure impedance changes and hemodynamic processes. To facilitate long-term multi-channel brain imaging in a wearable form factor without cabling overhead, there is a need for low-power local amplifiers [1] to support all these modalities. The main principle of optical hemodynamic measurements is to send light pulses into the tissue and measure the reflected light, which is modulated by the oxygen levels in the blood (Fig. 17.8.1). State-of-the-art NIRS ICs typically consume a few mW, primarily for the LEDs to meet the required light sensitivity at the photodiodes (PDs). Silicon photomultipliers (SiPMs) are promising alternatives because they have excellent low-light detection capabilities, speed of response and higher detection efficiency in both visible and near infrared range [2]. Hence, SiPMs allow deeper brain sensing depth and the possibility to sample consistent cerebral regions with larger inter-optode distance. This benefit would significantly reduce the number of NIRS channels and the associated power for a wearable NIRS device. Although SiPMs require a higher bias voltage (∼30V) than PDs, they achieve similar NIRS responses with a few hundred times less LED current. This results in a low-power NIRS ASIC and an overall power-efficient system. Existing optical sensing ICs are not suitable for a SiPM because of its large and variable output current. Trimming-based calibration methods [3] suffer from drift over time. Auto-zeroing by swapping an integrator capacitor [4][5] compensates ambient light at the cost of the integrator's headroom. Apart from ambient light, the dynamic range (DR) of the amplifier is also limited by a large NIRS signal, leading to a power-hungry readout.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"24 1","pages":"294-296"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73455936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310205
C. Menolfi, M. Braendli, P. Francese, T. Morf, A. Cevrero, M. Kossel, L. Kull, D. Luu, Ilter Özkaya, T. Toifl
The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In the foreseeable future, a high-performance TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 SST Tx that is based on a quarter-rate 56GS/s 8b SST DAC along with a digital 8-tap FIR filter for channel equalization.
{"title":"A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS","authors":"C. Menolfi, M. Braendli, P. Francese, T. Morf, A. Cevrero, M. Kossel, L. Kull, D. Luu, Ilter Özkaya, T. Toifl","doi":"10.1109/ISSCC.2018.8310205","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310205","url":null,"abstract":"The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In the foreseeable future, a high-performance TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 SST Tx that is based on a quarter-rate 56GS/s 8b SST DAC along with a digital 8-tap FIR filter for channel equalization.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"82 1","pages":"104-106"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78083975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310282
J. Sharma, H. Krishnaswamy
In the recent past, there have been exciting advances in dividerless PLLs, such as sub-sampling PLLs (SSPLLs) [1,2] and injection-locked clock multipliers (ILCMs) [3] that substantially reduce loop noise to cross the −250dB jitter-power figure-of-merit (FOM,) barrier. However, there exists a fundamental trade-off between FOM, and reference spurs in PLLs, although the mechanisms vary across architectures. Narrow PLL bandwidths are necessary for reducing spurs through filtering, but this can conflict with the optimal bandwidth for jitter. In SSPLLs, buffers, isolating the VCO from the sub-sampled phase detector (SSPD) (Fig. 15.7.1), reduce spurs at the expense of noise and power consumption. Smaller sample capacitances in the SSPD reduce spurs generated by mismatch-induced charge sharing, charge injection, and tank frequency modulation at the expense of increased kT/C noise. Consequently, the SSPLL of [2] achieves spur <-80dBc by using isolation buffers, a small sample capacitance (and another DLL-based technique) but exhibits an FOM, of −244.6dB. In the SSPLL of [1], the elimination of this isolation buffer and the use of a larger capacitance results in a better FOM, of −252dB but a spur of −56dBc. The ILCM in [3] operates with large injection to enable locking to a high multiple of the reference, but this degrades spurs. The absence of noisy loop components yields a very low, but large injection leads to a spur of −43dBc. Also, ILCMs do not feature explicit phase detectors, limiting the optimization of loop dynamics.
{"title":"A dividerless reference-sampling RF PLL with −253.5dB jitter FOM and <-67dBc Reference Spurs","authors":"J. Sharma, H. Krishnaswamy","doi":"10.1109/ISSCC.2018.8310282","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310282","url":null,"abstract":"In the recent past, there have been exciting advances in dividerless PLLs, such as sub-sampling PLLs (SSPLLs) [1,2] and injection-locked clock multipliers (ILCMs) [3] that substantially reduce loop noise to cross the −250dB jitter-power figure-of-merit (FOM,) barrier. However, there exists a fundamental trade-off between FOM, and reference spurs in PLLs, although the mechanisms vary across architectures. Narrow PLL bandwidths are necessary for reducing spurs through filtering, but this can conflict with the optimal bandwidth for jitter. In SSPLLs, buffers, isolating the VCO from the sub-sampled phase detector (SSPD) (Fig. 15.7.1), reduce spurs at the expense of noise and power consumption. Smaller sample capacitances in the SSPD reduce spurs generated by mismatch-induced charge sharing, charge injection, and tank frequency modulation at the expense of increased kT/C noise. Consequently, the SSPLL of [2] achieves spur <-80dBc by using isolation buffers, a small sample capacitance (and another DLL-based technique) but exhibits an FOM, of −244.6dB. In the SSPLL of [1], the elimination of this isolation buffer and the use of a larger capacitance results in a better FOM, of −252dB but a spur of −56dBc. The ILCM in [3] operates with large injection to enable locking to a high multiple of the reference, but this degrades spurs. The absence of noisy loop components yields a very low, but large injection leads to a spur of −43dBc. Also, ILCMs do not feature explicit phase detectors, limiting the optimization of loop dynamics.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"97 1","pages":"258-260"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75412711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310392
Chung-Cheng Chou, Zheng-Jun Lin, P. Tseng, Chih-Feng Li, Chih-Yang Chang, Wei-Chih Chen, Y. Chih, T. Chang
RRAM is an attractive and low-cost memory structure for embedded applications due to the simplicity of the RRAM element (RE) and its compatibility with a logic process. A RRAM bit cell (Fig. 30.1.1) consists of an NMOS select transistor and a bipolar RE, which consists of a bottom electrode (BE), a transition metal-oxide file (Hi-K), a metal capping layer and a top electrode (TE). The memory cell operates as a 3-terminal device, including bit-line (BL), source-line (SL) and word-line (WL). BL is connecting to TE, SL is connecting to the source node of the select transistor and word-line (WL) is connecting to the gate of the select transistor. A common SL (CSL) architecture is adopted in this work. CSL allows two or more columns to share one source line. So that the column mux number for SL can be reduced, therefore macro area can be saved. In addition, SL can be implemented with a wider metal track due to the reduced SL count. Therefore, the SL resistance also can be reduced. However, a CSL architecture will result in a larger parasitic capacitance on SL. This paper presents an SL precharge scheme to deal this increased capacitance when reading from the CSL.
{"title":"An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance","authors":"Chung-Cheng Chou, Zheng-Jun Lin, P. Tseng, Chih-Feng Li, Chih-Yang Chang, Wei-Chih Chen, Y. Chih, T. Chang","doi":"10.1109/ISSCC.2018.8310392","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310392","url":null,"abstract":"RRAM is an attractive and low-cost memory structure for embedded applications due to the simplicity of the RRAM element (RE) and its compatibility with a logic process. A RRAM bit cell (Fig. 30.1.1) consists of an NMOS select transistor and a bipolar RE, which consists of a bottom electrode (BE), a transition metal-oxide file (Hi-K), a metal capping layer and a top electrode (TE). The memory cell operates as a 3-terminal device, including bit-line (BL), source-line (SL) and word-line (WL). BL is connecting to TE, SL is connecting to the source node of the select transistor and word-line (WL) is connecting to the gate of the select transistor. A common SL (CSL) architecture is adopted in this work. CSL allows two or more columns to share one source line. So that the column mux number for SL can be reduced, therefore macro area can be saved. In addition, SL can be implemented with a wider metal track due to the reduced SL count. Therefore, the SL resistance also can be reduced. However, a CSL architecture will result in a larger parasitic capacitance on SL. This paper presents an SL precharge scheme to deal this increased capacitance when reading from the CSL.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"38 1","pages":"478-480"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74903615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310375
Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, T. Kaneko, W. Deng, Rui Wu, K. Okada, A. Matsuzawa
This paper demonstrates a Bluetooth Low-Energy (BLE) transceiver (TRX) achieving ultra-low-power (ULP) operation for Internet-of-Things (IoT) applications. As more and more devices will be connected and access to the Internet, the wireless traffic will be extremely crowded in the 2.4GHz ISM band. To coexist with all the wireless devices without being interfered by co-channel and out-of-band (OB) signals, a BLE receiver (RX) should have very high adjacent-channel rejection and very high blocker tolerance. At the same time, the total power consumption should be minimized for longer battery life. In this work, the TRX utilizes a wide loop-bandwidth All-Digital PLL (ADPLL) as a central component for transmitter (TX) modulation, RX analog data digitization, and phase synchronization. The single-channel demodulation method is adopted for cutting half of the analog baseband circuit to further reduce the power consumption while maintaining a high interference rejection. This BLE TRX achieves the lowest energy consumption among the state-of-the-art works in the comparison table [1-5] while satisfying all the interference requirements with sufficient margins.
{"title":"An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS","authors":"Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, T. Kaneko, W. Deng, Rui Wu, K. Okada, A. Matsuzawa","doi":"10.1109/ISSCC.2018.8310375","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310375","url":null,"abstract":"This paper demonstrates a Bluetooth Low-Energy (BLE) transceiver (TRX) achieving ultra-low-power (ULP) operation for Internet-of-Things (IoT) applications. As more and more devices will be connected and access to the Internet, the wireless traffic will be extremely crowded in the 2.4GHz ISM band. To coexist with all the wireless devices without being interfered by co-channel and out-of-band (OB) signals, a BLE receiver (RX) should have very high adjacent-channel rejection and very high blocker tolerance. At the same time, the total power consumption should be minimized for longer battery life. In this work, the TRX utilizes a wide loop-bandwidth All-Digital PLL (ADPLL) as a central component for transmitter (TX) modulation, RX analog data digitization, and phase synchronization. The single-channel demodulation method is adopted for cutting half of the analog baseband circuit to further reduce the power consumption while maintaining a high interference rejection. This BLE TRX achieves the lowest energy consumption among the state-of-the-art works in the comparison table [1-5] while satisfying all the interference requirements with sufficient margins.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"72 1","pages":"444-446"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76118903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310181
Eric Cope, Julian Aschieri, Tony Lai, Franklin Zhao, Walter Grandfield, M. Clifford, Pete Rathfelder, Qiyuan Liu, Siddartha Kavilipati, Aaron Vandergriff, Gerald Miaille
Conventional Class-D amplifiers, although more power efficient than Class-AB amplifiers, typically do not deliver the same audio quality. The non-ideal switching behavior of the output power stages can degrade the linearity, noise and power-supply-rejection-ratio (PSRR) performance of Class-D amplifiers if employed in open-loop configurations [1]. Closed-loop Class-D amplifiers shape the non-idealities of the power amplifiers (PAs) and provide improved performance [2]. Conventional analog feedback amplifiers (AFAs) sense the PA output and feed it back to compare with the audio input signal in the analog domain. Compared with AFAs, digital feedback amplifiers (DFAs) have emerged with benefits of improved control of the loop filter and pulse-width modulation (PWM) in the digital domain. However, the DFA architecture usually demands a high-performance analog-to-digital converter (ADC) to digitize the PA output in the feedback path; This ADC's non-idealities may become the bottleneck of the system [3]. In this paper, a 2-channel Class-D digital error-feedback amplifier (DEFA) with a peak THD+N of 0.0013% is presented. A series of proposed techniques enable the DEFA to maintain its performance up to the maximum power level available.
{"title":"A 2×20W 0.0013% THD+N Class-D audio amplifier with consistent performance up to maximum power level","authors":"Eric Cope, Julian Aschieri, Tony Lai, Franklin Zhao, Walter Grandfield, M. Clifford, Pete Rathfelder, Qiyuan Liu, Siddartha Kavilipati, Aaron Vandergriff, Gerald Miaille","doi":"10.1109/ISSCC.2018.8310181","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310181","url":null,"abstract":"Conventional Class-D amplifiers, although more power efficient than Class-AB amplifiers, typically do not deliver the same audio quality. The non-ideal switching behavior of the output power stages can degrade the linearity, noise and power-supply-rejection-ratio (PSRR) performance of Class-D amplifiers if employed in open-loop configurations [1]. Closed-loop Class-D amplifiers shape the non-idealities of the power amplifiers (PAs) and provide improved performance [2]. Conventional analog feedback amplifiers (AFAs) sense the PA output and feed it back to compare with the audio input signal in the analog domain. Compared with AFAs, digital feedback amplifiers (DFAs) have emerged with benefits of improved control of the loop filter and pulse-width modulation (PWM) in the digital domain. However, the DFA architecture usually demands a high-performance analog-to-digital converter (ADC) to digitize the PA output in the feedback path; This ADC's non-idealities may become the bottleneck of the system [3]. In this paper, a 2-channel Class-D digital error-feedback amplifier (DEFA) with a peak THD+N of 0.0013% is presented. A series of proposed techniques enable the DEFA to maintain its performance up to the maximum power level available.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"20 1","pages":"56-58"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75691075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310199
K. Yoshioka, H. Kubota, Tomonori Fukushima, Satoshi Kondo, T. Ta, H. Okuni, Kaori Watanabe, Yoshinari Ojima, K. Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, N. Kawabe, Yasuhiro Ishii, Y. Iwagami, S. Yagi, I. Fujisawa, N. Kano, Tomohiro Sugimoto, Daisuke Kurose, N. Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, A. Sai, Nobu Matsumoto
Long-range and high-pixel-resolution LiDAR systems, using Time-of-Flight (ToF) information of the reflected photon from the target, are essential upon launching safe and reliable self-driving programs of Level 4 and above. 200m long-range distance measurement (DM) is required to sense proceeding vehicles and obstacles as fast as possible in a highway situation. To realize safe and reliable self-driving in city areas, LiDAR systems uniting wide angle-of-view and high pixel resolution are required to fully perceive surrounding events. Moreover, these performances must be achieved under strong background light (e.g., sunlight), which is the most significant noise source for LiDAR systems. To accomplish a 100m-range DM, an accumulation of the DM results through several pixels is utilized to improve the S/N ratio with 70klux background light [1]. Here, S is the number of photons reflected from the target and N as the number of background light photons. However, if the range is extended to 200m under similar condition of the laser power and frame rate (FPS), 16x more pixel accumulation is required. Such pixel accumulation leads to blurring the range image, and hence, a serious oversight in the surrounding events, such as a flying-out pedestrian, may occur, not suiting self-driving applications. Furthermore, the Time-to-Digital Converter (tDC) based ToF measurement is activated only when 2 or more photons are detected simultaneously [1], and thus, is not suitable for the 200m long-range DM where few photons are reflected from the target. On the other hand, ToF measurements using ADCs, which can continuously quantize the silicon photomultiplier (SiPM) output and can sense single-photon events, suits long-range measuring purposes well [2]. However, a number of accumulations should still be required to accomplish 200m-range DM, and hence, low resolution is inevitable. In addition, the SoC cost is critical. To enhance the short-range DM resolution by using ADCs, the required sampling rate is over 10GS/s; upon realizing a 20ch AFE, such an ADC array alone may occupy an area of over 10mm2 and consume huge power [3].
{"title":"A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique","authors":"K. Yoshioka, H. Kubota, Tomonori Fukushima, Satoshi Kondo, T. Ta, H. Okuni, Kaori Watanabe, Yoshinari Ojima, K. Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, N. Kawabe, Yasuhiro Ishii, Y. Iwagami, S. Yagi, I. Fujisawa, N. Kano, Tomohiro Sugimoto, Daisuke Kurose, N. Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, A. Sai, Nobu Matsumoto","doi":"10.1109/ISSCC.2018.8310199","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310199","url":null,"abstract":"Long-range and high-pixel-resolution LiDAR systems, using Time-of-Flight (ToF) information of the reflected photon from the target, are essential upon launching safe and reliable self-driving programs of Level 4 and above. 200m long-range distance measurement (DM) is required to sense proceeding vehicles and obstacles as fast as possible in a highway situation. To realize safe and reliable self-driving in city areas, LiDAR systems uniting wide angle-of-view and high pixel resolution are required to fully perceive surrounding events. Moreover, these performances must be achieved under strong background light (e.g., sunlight), which is the most significant noise source for LiDAR systems. To accomplish a 100m-range DM, an accumulation of the DM results through several pixels is utilized to improve the S/N ratio with 70klux background light [1]. Here, S is the number of photons reflected from the target and N as the number of background light photons. However, if the range is extended to 200m under similar condition of the laser power and frame rate (FPS), 16x more pixel accumulation is required. Such pixel accumulation leads to blurring the range image, and hence, a serious oversight in the surrounding events, such as a flying-out pedestrian, may occur, not suiting self-driving applications. Furthermore, the Time-to-Digital Converter (tDC) based ToF measurement is activated only when 2 or more photons are detected simultaneously [1], and thus, is not suitable for the 200m long-range DM where few photons are reflected from the target. On the other hand, ToF measurements using ADCs, which can continuously quantize the silicon photomultiplier (SiPM) output and can sense single-photon events, suits long-range measuring purposes well [2]. However, a number of accumulations should still be required to accomplish 200m-range DM, and hence, low resolution is inevitable. In addition, the SoC cost is critical. To enhance the short-range DM resolution by using ADCs, the required sampling rate is over 10GS/s; upon realizing a 20ch AFE, such an ADC array alone may occupy an area of over 10mm2 and consume huge power [3].","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"30 1","pages":"92-94"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74350705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310200
C. Bamji, S. Mehta, Barry Thompson, T. Elkhatib, S. Wurster, O. Akkaya, A. Payne, J. Godbaz, M. Fenton, V. Rajasekaran, Larry Prather, S. Nagaraja, Vishali Mogallapu, Dane Snow, Rich McCauley, Mustansir Mukadam, I. Agi, S. McCarthy, Zhanping Xu, Travis Perry, William Qian, V. Chan, P. Adepu, G. Ali, Muneeb Ahmed, Aditya Mukherjee, Sheethal Nayak, Dave Gampell, S. Acharya, Lou Kordus, Patrick O'Connor
The quest for accurate, high-resolution, low-power-consumption, and small-footprint 3D depth cameras has driven a rapid improvement in Continuous-Wave (CW) Time-of-Flight (ToF) technology. Commercially available 3D image acquisition techniques include Stereo Vision, Structured Light, and ToF. CW ToF imaging systems offer excellent mechanical robustness, no baseline requirement, high effective depth image resolution, low computational cost, and simultaneous IR ambient light invariant intensity capture (Active Brightness). In a CW ToF camera, light from an amplitude modulated light source is backscattered by objects in the camera's field of view, and the phase delay of the amplitude envelope is measured between the emitted and reflected light. This phase difference is translated into a distance value for each pixel in the imaging array.
{"title":"IMpixel 65nm BSI 320MHz demodulated TOF Image sensor with 3μm global shutter pixels and analog binning","authors":"C. Bamji, S. Mehta, Barry Thompson, T. Elkhatib, S. Wurster, O. Akkaya, A. Payne, J. Godbaz, M. Fenton, V. Rajasekaran, Larry Prather, S. Nagaraja, Vishali Mogallapu, Dane Snow, Rich McCauley, Mustansir Mukadam, I. Agi, S. McCarthy, Zhanping Xu, Travis Perry, William Qian, V. Chan, P. Adepu, G. Ali, Muneeb Ahmed, Aditya Mukherjee, Sheethal Nayak, Dave Gampell, S. Acharya, Lou Kordus, Patrick O'Connor","doi":"10.1109/ISSCC.2018.8310200","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310200","url":null,"abstract":"The quest for accurate, high-resolution, low-power-consumption, and small-footprint 3D depth cameras has driven a rapid improvement in Continuous-Wave (CW) Time-of-Flight (ToF) technology. Commercially available 3D image acquisition techniques include Stereo Vision, Structured Light, and ToF. CW ToF imaging systems offer excellent mechanical robustness, no baseline requirement, high effective depth image resolution, low computational cost, and simultaneous IR ambient light invariant intensity capture (Active Brightness). In a CW ToF camera, light from an amplitude modulated light source is backscattered by objects in the camera's field of view, and the phase delay of the amplitude envelope is measured between the emitted and reflected light. This phase difference is translated into a distance value for each pixel in the imaging array.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"124 1","pages":"94-96"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73724026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310407
Bo Zhang, F. Gianesello, S. Erba, M. Meghelli, A. Emami-Neyestanak, T. Shibasaki
Since the invention of optical fiber in the 1970's, optical communication has been changing the landscape of telecommunication and data communication worldwide with its ultra-broad bandwidth and long haul transmission capabilities. It connects people around the world through submarine inter-continent optical cables, is the backbone of metro area networks, and is essential for data center network connectivity. Today, cost effective 100Gb/s optical links on a single fiber, using either III-V based optical devices or silicon photonics, are readily available for few meters to few kilometers connectivity solutions inside the data center and between data centers, while next generation links are poised to reach 400Gb/s. In this forum, the current state-of-the-art of optical communications will be reviewed, including advances in long-haul transport, progress in silicon photonics covering transceivers, packaging, assembly and test, progress in high order modulation schemes and signal processing, description of 56Gb/s and beyond electrical serial interfaces, and closing with a presentation on optical backplane technology.
{"title":"F5: Advanced optical communication: From devices, circuits, and architectures to algorithms","authors":"Bo Zhang, F. Gianesello, S. Erba, M. Meghelli, A. Emami-Neyestanak, T. Shibasaki","doi":"10.1109/ISSCC.2018.8310407","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310407","url":null,"abstract":"Since the invention of optical fiber in the 1970's, optical communication has been changing the landscape of telecommunication and data communication worldwide with its ultra-broad bandwidth and long haul transmission capabilities. It connects people around the world through submarine inter-continent optical cables, is the backbone of metro area networks, and is essential for data center network connectivity. Today, cost effective 100Gb/s optical links on a single fiber, using either III-V based optical devices or silicon photonics, are readily available for few meters to few kilometers connectivity solutions inside the data center and between data centers, while next generation links are poised to reach 400Gb/s. In this forum, the current state-of-the-art of optical communications will be reviewed, including advances in long-haul transport, progress in silicon photonics covering transceivers, packaging, assembly and test, progress in high order modulation schemes and signal processing, description of 56Gb/s and beyond electrical serial interfaces, and closing with a presentation on optical backplane technology.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"20 1","pages":"514-516"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73773272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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