Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310184
Shinwoong Park, Dongseok Shin, Kwang-Jin Koh, S. Raman
Discrete-time (DT) circuits provide a means to overcome the analog-circuit design challenges in deeply scaled digital CMOS technologies while benefitting from the reduced switch on-resistance and parasitic capacitance, resulting in lower dynamic power dissipation. In addition, such DT analog circuits can reduce the requirements on analog-to-digital converters that precede digital processing [1]. Recent DT domain filters achieve high-order narrowband programmable filtering with low power and high linearity even under low supply voltage [2,3]. However, DT switched capacitor circuits have not been considered for wideband analog signal processing (ASP) applications such as on-chip implementation of FIR-based beamforming [4,5]. While the AFIR filter proposed in [6] is a suitable approach for programmable wideband ASP applications, in that design only symmetric and positive coefficient sets were possible and measured performance was not shown.
{"title":"A low-power 3.25GS/s 4th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processing","authors":"Shinwoong Park, Dongseok Shin, Kwang-Jin Koh, S. Raman","doi":"10.1109/ISSCC.2018.8310184","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310184","url":null,"abstract":"Discrete-time (DT) circuits provide a means to overcome the analog-circuit design challenges in deeply scaled digital CMOS technologies while benefitting from the reduced switch on-resistance and parasitic capacitance, resulting in lower dynamic power dissipation. In addition, such DT analog circuits can reduce the requirements on analog-to-digital converters that precede digital processing [1]. Recent DT domain filters achieve high-order narrowband programmable filtering with low power and high linearity even under low supply voltage [2,3]. However, DT switched capacitor circuits have not been considered for wideband analog signal processing (ASP) applications such as on-chip implementation of FIR-based beamforming [4,5]. While the AFIR filter proposed in [6] is a suitable approach for programmable wideband ASP applications, in that design only symmetric and positive coefficient sets were possible and measured performance was not shown.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"60 1","pages":"62-64"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73900937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310309
Loai G. Salem, P. Mercier
Modern DVFS-enabled SoCs require nimble supply regulators that rapidly respond to abrupt load changes and offer fine resolution (e.g., 12.5mV in [1], 10mV in [2]) over large voltage and current dynamic ranges. Switch-array digital LDOs (SA-DLDOs) are a potentially attractive regulation option due to their ability to operate with low input voltages and in part to their modular digital nature and scalability. SA-DLDOs employ 2” unary-[3] or binary-weighted [4] PMOS arrays that are modulated through a 1b or multi-bit ADCs to maintain the output voltage (Vout) at the desired level (Vref), as shown in Fig. 18.7.1 (top left). Unfortunately, while array conductance in SA-DLDOs linearly increases with equal step size (gLSB) as the code is increased, the output voltage step, vLSB, does not; in fact, vLsB is nonlinear: ∼GLVout × GLSB. Thus, SA-DLDOs achieve a nonlinear steady-state error, ess = Veef − Vout ≈ ±gLSB/Gl χ Vú!op, as shown in Fig. 18.7.1 (bottom left), that deteriorates at large dropout voltages, Vdrop = Vin − Voitt, and at small loads, Gl. As a result, the required supply step of 10mV (with ±15% typical accuracy) to perform per-core DVFS over a typical 100χ IL dynamic range requires an impractical 16b PMOS array resolution. Even with limit-cycle oscillations, the load range that can achieve ±1.5mV accuracy is provably limited to 2N-6, 7 at Veef=VJ2 (Fig. 18.7.2, top left), which would still require a 14b array resolution that, even if it were feasible to build, would come with linearly (for binary search) or exponentially (for linear search) increased response time (TR), quiescent power (IQ), and area.
{"title":"A sub-1.55mV-accuracy 36.9ps-FOM digital-low-dropout regulator employing switched-capacitor resistance","authors":"Loai G. Salem, P. Mercier","doi":"10.1109/ISSCC.2018.8310309","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310309","url":null,"abstract":"Modern DVFS-enabled SoCs require nimble supply regulators that rapidly respond to abrupt load changes and offer fine resolution (e.g., 12.5mV in [1], 10mV in [2]) over large voltage and current dynamic ranges. Switch-array digital LDOs (SA-DLDOs) are a potentially attractive regulation option due to their ability to operate with low input voltages and in part to their modular digital nature and scalability. SA-DLDOs employ 2” unary-[3] or binary-weighted [4] PMOS arrays that are modulated through a 1b or multi-bit ADCs to maintain the output voltage (V<inf>out</inf>) at the desired level (V<inf>ref</inf>), as shown in Fig. 18.7.1 (top left). Unfortunately, while array conductance in SA-DLDOs linearly increases with equal step size (<inf>g</inf>LSB) as the code is increased, the output voltage step, <inf>v</inf>LSB, does not; in fact, <inf>v</inf>LsB is nonlinear: ∼G<inf>L</inf>V<inf>out</inf> × <inf>G</inf>LSB. Thus, SA-DLDOs achieve a nonlinear steady-state error, e<inf>ss</inf> = V<inf>eef</inf> − V<inf>out</inf> ≈ ±<inf>g</inf>LSB/G<inf>l</inf> χ V<inf>ú!op</inf>, as shown in Fig. 18.7.1 (bottom left), that deteriorates at large dropout voltages, V<inf>drop</inf> = V<inf>in</inf> − V<inf>oitt</inf>, and at small loads, G<inf>l</inf>. As a result, the required supply step of 10mV (with ±15% typical accuracy) to perform per-core DVFS over a typical 100χ I<inf>L</inf> dynamic range requires an impractical 16b PMOS array resolution. Even with limit-cycle oscillations, the load range that can achieve ±1.5mV accuracy is provably limited to 2<sup>N-6, 7</sup> at V<inf>eef</inf>=VJ2 (Fig. 18.7.2, top left), which would still require a 14b array resolution that, even if it were feasible to build, would come with linearly (for binary search) or exponentially (for linear search) increased response time (T<inf>R</inf>), quiescent power (IQ), and area.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"22 1","pages":"312-314"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73105627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310193
M. Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, K. Honda, H. Kikuchi, T. Wada, Y. Kamikubo, T. Miura, M. Nakamizo, Naoki Jyo, Ryo Hayashibara, Y. Furukawa, Shinya Miyata, Satoshi Yamamoto, Y. Ota, H. Takahashi, T. Taura, Y. Oike, K. Tatani, T. Nagano, T. Ezaki, T. Hirayama
Rolling-shutter CMOS image sensors (CISs) are widely used [1,2]. However, the distortion of moving subjects remains an unresolved problem, regardless of the speed at which these sensors are operated. It has been reported that by adopting in-pixel analog memory (MEM) in pixels, a global shutter (GS) can be achieved by saving all pixels simultaneously as stored charges [3,4]. However, as signals from a storage unit are read in a column-wise sequence, a light-shielding structure is required for the MEM to suppress the influence of parasitic light during the reading period. Pixel-parallel ADCs have been reported as methods of implementing GS on a circuit [5,6]. However, these techniques have not been successful in operations on megapixels because they do not address issues such as the timing constraint for reading and writing a digital signal to and from an ADC in a pixel owing to increase in the number of pixels and the increase in the total power consumption of massively parallel comparators (CMs).
{"title":"A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC","authors":"M. Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, K. Honda, H. Kikuchi, T. Wada, Y. Kamikubo, T. Miura, M. Nakamizo, Naoki Jyo, Ryo Hayashibara, Y. Furukawa, Shinya Miyata, Satoshi Yamamoto, Y. Ota, H. Takahashi, T. Taura, Y. Oike, K. Tatani, T. Nagano, T. Ezaki, T. Hirayama","doi":"10.1109/ISSCC.2018.8310193","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310193","url":null,"abstract":"Rolling-shutter CMOS image sensors (CISs) are widely used [1,2]. However, the distortion of moving subjects remains an unresolved problem, regardless of the speed at which these sensors are operated. It has been reported that by adopting in-pixel analog memory (MEM) in pixels, a global shutter (GS) can be achieved by saving all pixels simultaneously as stored charges [3,4]. However, as signals from a storage unit are read in a column-wise sequence, a light-shielding structure is required for the MEM to suppress the influence of parasitic light during the reading period. Pixel-parallel ADCs have been reported as methods of implementing GS on a circuit [5,6]. However, these techniques have not been successful in operations on megapixels because they do not address issues such as the timing constraint for reading and writing a digital signal to and from an ADC in a pixel owing to increase in the number of pixels and the increase in the total power consumption of massively parallel comparators (CMs).","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"1 1","pages":"80-82"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79767206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310195
Yitae Kim, Wonchul Choi, D. Park, H. Jeoung, Bumsuk Kim, Youngsun Oh, Sung-Hun Oh, Byungjun Park, Euiyeol Kim, Yunki Lee, T. Jung, Yongwoong Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang
CMOS image sensors (CIS) have attracted much attention for the emerging mobile market, and the demand of high-resolution image sensors in mobile applications continues to increase [1-3]. For this reason, pixel pitch has been reduced down to 1.0μσι for mass production. Nevertheless, CISs are continuously scaling down to meet the strong demand for higher-resolution images. However, when the pixel size is reduced down to the sub-micron regime (possibly smaller than the diffraction limit), it is very important to consider photo sensitivity and crosstalk, which determine signal-to-noise ratio (SNR). To minimize degradation of photo sensitivity, back-side illumination (BSI), which collects light at the back side, is widely used instead of front-side illumination. In addition to BSI technology, deep-trench isolation (DTI) has emerged as a leading candidate to suppress crosstalk since it physically isolates the pixel. Previous work shows that partial-depth DTI can be applied in a 1.12μm-pitch pixel [4]. Furthermore, full-depth DTI has been demonstrated in a 1.12μm pixel with 24% larger full-well capacity (FWC), 30% smaller YSNR10, 2.0dB higher SNR, and especially for lower crosstalk (12.5%) compared with a conventional one [5]. In this work, a 24-Mpixel CIS with 0.9μσι unit pixels that takes advantage of full-depth DTI is demonstrated.
{"title":"A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation","authors":"Yitae Kim, Wonchul Choi, D. Park, H. Jeoung, Bumsuk Kim, Youngsun Oh, Sung-Hun Oh, Byungjun Park, Euiyeol Kim, Yunki Lee, T. Jung, Yongwoong Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang","doi":"10.1109/ISSCC.2018.8310195","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310195","url":null,"abstract":"CMOS image sensors (CIS) have attracted much attention for the emerging mobile market, and the demand of high-resolution image sensors in mobile applications continues to increase [1-3]. For this reason, pixel pitch has been reduced down to 1.0μσι for mass production. Nevertheless, CISs are continuously scaling down to meet the strong demand for higher-resolution images. However, when the pixel size is reduced down to the sub-micron regime (possibly smaller than the diffraction limit), it is very important to consider photo sensitivity and crosstalk, which determine signal-to-noise ratio (SNR). To minimize degradation of photo sensitivity, back-side illumination (BSI), which collects light at the back side, is widely used instead of front-side illumination. In addition to BSI technology, deep-trench isolation (DTI) has emerged as a leading candidate to suppress crosstalk since it physically isolates the pixel. Previous work shows that partial-depth DTI can be applied in a 1.12μm-pitch pixel [4]. Furthermore, full-depth DTI has been demonstrated in a 1.12μm pixel with 24% larger full-well capacity (FWC), 30% smaller YSNR10, 2.0dB higher SNR, and especially for lower crosstalk (12.5%) compared with a conventional one [5]. In this work, a 24-Mpixel CIS with 0.9μσι unit pixels that takes advantage of full-depth DTI is demonstrated.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"7 1","pages":"84-86"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76987117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310240
Bagher Rabet, J. Buckwalter
Gigabit-per-second millimeter-wave (mm-wave) access and backhaul networks at 28GHz demand high-order QAM, OFDM, and/or carrier-aggregated waveforms that force the PA to operate under high peak-to-average power ratio (PAPR) [1]. High PAPR requirements aggravate the design of mm-wave Si CMOS and SiGe BiCMOS PAs since a linear response and high efficiency are simultaneously desired. Recent work has demonstrated mm-wave PAs with peak efficiency exceeding 30% at 28GHz for output powers above 20dBm [1-5]. However, high average efficiency associated with high-PAPR waveforms remains elusive. To improve average efficiency, circuit techniques based on Doherty [3] and outphasing [6] have been demonstrated in mm-wave bands. Earlier work using these techniques showed average efficiency with QAM waveforms that is well under 20%.
{"title":"A high-efficiency 28GHz outphasing PA with 23dBm output power using a triaxial balun combiner","authors":"Bagher Rabet, J. Buckwalter","doi":"10.1109/ISSCC.2018.8310240","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310240","url":null,"abstract":"Gigabit-per-second millimeter-wave (mm-wave) access and backhaul networks at 28GHz demand high-order QAM, OFDM, and/or carrier-aggregated waveforms that force the PA to operate under high peak-to-average power ratio (PAPR) [1]. High PAPR requirements aggravate the design of mm-wave Si CMOS and SiGe BiCMOS PAs since a linear response and high efficiency are simultaneously desired. Recent work has demonstrated mm-wave PAs with peak efficiency exceeding 30% at 28GHz for output powers above 20dBm [1-5]. However, high average efficiency associated with high-PAPR waveforms remains elusive. To improve average efficiency, circuit techniques based on Doherty [3] and outphasing [6] have been demonstrated in mm-wave bands. Earlier work using these techniques showed average efficiency with QAM waveforms that is well under 20%.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"29 1","pages":"174-176"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85241711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310208
Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, A. C. Carusone
ADC-based transceivers having up to 8 bits of resolution have been reported for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantization has been explored [3,4] using performance metrics for the complete link, such as bit-error rate (BER), to optimize the quantizer thresholds. Both [3,4] are PAM-2 (NRZ) receivers, demonstrating non-uniform quantization specifically for a decision feedback equalizer (DFE) at 10Gb/s and a feedforward equalizer (FFE) at 4Gb/s respectively. An LMS algorithm in [4] adjusts the threshold levels requiring fine-tuning (8b resolution). This paper presents a 64Gb/s PAM-4 transceiver utilizing an ADC-based receiver (RX), with an analog front-end (AFE) based on a 6b, 1b folding, flash ADC with adaptive threshold levels. A fast greedy-search algorithm is used to choose the optimal quantizer thresholds for minimum BER over a given channel. This provides a near-optimal way of power-scaling the ADC when the channel loss doesn't require the ADC's full resolution. The optimization can work in the background for any equalizer structure, does not place additional requirements on the ADC design, and never diverges, unlike LMS-based approaches [4].
{"title":"A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET","authors":"Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, A. C. Carusone","doi":"10.1109/ISSCC.2018.8310208","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310208","url":null,"abstract":"ADC-based transceivers having up to 8 bits of resolution have been reported for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantization has been explored [3,4] using performance metrics for the complete link, such as bit-error rate (BER), to optimize the quantizer thresholds. Both [3,4] are PAM-2 (NRZ) receivers, demonstrating non-uniform quantization specifically for a decision feedback equalizer (DFE) at 10Gb/s and a feedforward equalizer (FFE) at 4Gb/s respectively. An LMS algorithm in [4] adjusts the threshold levels requiring fine-tuning (8b resolution). This paper presents a 64Gb/s PAM-4 transceiver utilizing an ADC-based receiver (RX), with an analog front-end (AFE) based on a 6b, 1b folding, flash ADC with adaptive threshold levels. A fast greedy-search algorithm is used to choose the optimal quantizer thresholds for minimum BER over a given channel. This provides a near-optimal way of power-scaling the ADC when the channel loss doesn't require the ADC's full resolution. The optimization can work in the background for any equalizer structure, does not place additional requirements on the ADC design, and never diverges, unlike LMS-based approaches [4].","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"45 1","pages":"110-112"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84822146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310236
S. Daneshgar, K. Dasgupta, C. Thakkar, A. Chakrabarti, Shuhei Yamada, D. Choudhury, J. Jaussi, B. Casper
The industry-wide impetus on user experience and immersive content for handheld/wearable consumer devices is accelerating the demand for high-speed millimeter-wave (mm-wave) PAN wireless connectivity. Next-generation 60GHz PAN standards [1] have made it mandatory to achieve >20Gb/s rates using wide (4.32GHz or higher) bandwidth. However, in order to support multiple concurrent high-speed links, it is imperative to achieve high spectral efficiency. MIMO techniques allow for such spectrum reuse by employing simultaneous spatial streams. However, unlike at low-GHz frequencies, which exhibit rich multipath scattering and therefore a high-rank TX-RX MIMO channel matrix, mm-wave propagation is fundamentally less diverse due to higher reflection/absorption.
{"title":"A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO","authors":"S. Daneshgar, K. Dasgupta, C. Thakkar, A. Chakrabarti, Shuhei Yamada, D. Choudhury, J. Jaussi, B. Casper","doi":"10.1109/ISSCC.2018.8310236","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310236","url":null,"abstract":"The industry-wide impetus on user experience and immersive content for handheld/wearable consumer devices is accelerating the demand for high-speed millimeter-wave (mm-wave) PAN wireless connectivity. Next-generation 60GHz PAN standards [1] have made it mandatory to achieve >20Gb/s rates using wide (4.32GHz or higher) bandwidth. However, in order to support multiple concurrent high-speed links, it is imperative to achieve high spectral efficiency. MIMO techniques allow for such spectrum reuse by employing simultaneous spatial streams. However, unlike at low-GHz frequencies, which exhibit rich multipath scattering and therefore a high-rank TX-RX MIMO channel matrix, mm-wave propagation is fundamentally less diverse due to higher reflection/absorption.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"33 1","pages":"166-168"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82436799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310406
P. Busson, H. Luong, C. Hung, H. Krishnaswamy, T. Georgantas, P. Mercier
The 5th generation wireless system (5G) is proposed as the next major revolution of mobile wireless technologies. Carrier frequencies in the mm-wave bands and MIMO/multi-antenna systems are expected to be extensively employed to achieve significantly enhanced data rate, spectral/spatial diversity/efficiency and minimized system latency. The design of commercial high-performance radio transceivers at mm-wave represents a major technical challenge. This forum is focused on current state-of-the-art and future directions of multi-antenna systems in the mm-wave bands, from both system architecture and circuit design perspectives. Key system integration aspects such as antenna design, packaging and built-in self-test will also be covered.
{"title":"F4: Circuit and system techniques for mm-wave multi-antenna systems","authors":"P. Busson, H. Luong, C. Hung, H. Krishnaswamy, T. Georgantas, P. Mercier","doi":"10.1109/ISSCC.2018.8310406","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310406","url":null,"abstract":"The 5th generation wireless system (5G) is proposed as the next major revolution of mobile wireless technologies. Carrier frequencies in the mm-wave bands and MIMO/multi-antenna systems are expected to be extensively employed to achieve significantly enhanced data rate, spectral/spatial diversity/efficiency and minimized system latency. The design of commercial high-performance radio transceivers at mm-wave represents a major technical challenge. This forum is focused on current state-of-the-art and future directions of multi-antenna systems in the mm-wave bands, from both system architecture and circuit design perspectives. Key system integration aspects such as antenna design, packaging and built-in self-test will also be covered.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"10 1","pages":"511-513"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81863238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310330
Anh Chu, Benedikt Schlecker, K. Lips, M. Ortmanns, J. Anders
Thanks to their unmatched specificity, methods based on magnetic resonance effects are amongst the most powerful spectroscopic techniques available today. Out of these methods, due to the availability of improved electronics at the required frequencies in the tens of GHz region, electron spin resonance (ESR) spectroscopy is gaining significant attention in the research community as a tool in life science and materials science research.
{"title":"An 8-channel 13GHz ESR-on-a-Chip injection-locked vco-array achieving 200μM-concentration sensitivity","authors":"Anh Chu, Benedikt Schlecker, K. Lips, M. Ortmanns, J. Anders","doi":"10.1109/ISSCC.2018.8310330","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310330","url":null,"abstract":"Thanks to their unmatched specificity, methods based on magnetic resonance effects are amongst the most powerful spectroscopic techniques available today. Out of these methods, due to the availability of improved electronics at the required frequencies in the tens of GHz region, electron spin resonance (ESR) spectroscopy is gaining significant attention in the research community as a tool in life science and materials science research.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"5 1","pages":"354-356"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84378380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310358
Tso-Wei Li, Min-Yu Huang, Hua Wang
The 5th generation (5G) mm-wave systems are expected to support wideband spectrum-efficient modulations (e.g., 64-QAM or 256-QAM) to achieve Gb/s-link-throughput revolution. These complex modulation schemes, however, often come with high-density constellations that demand stringent linearity, i.e. AM-AM and AM-PM, on the mm-wave front-end circuits, in particular, the power amplifiers (PAs). In addition, to support future massive MIMOs, the mm-wave front-ends should be ultra-efficient in both their energy efficiency and area usage, posing even more constraints on the PA designs [1-5].
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