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2018 IEEE International Solid - State Circuits Conference - (ISSCC)最新文献

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A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation 一种可重构的28/37GHz混合波束形成MIMO接收机,带间载波聚合和rf域LMS权重自适应
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310189
Susnata Mondal, Rahul Singh, J. Paramesh
This paper presents a hybrid beamforming mm-wave MIMO receiver with two key innovations. First, it can be configured into three modes: two single-band multistream modes at 28 or 37 GHz that can support single-or multi-user MIMO, and a concurrent 28 and 37GHz dual-band single-stream phased-array inter-band carrier-aggregation mode. In all modes, the receiver features full connectivity from each antenna element input to each output stream, thereby maximizing usage of the available aperture. Second, the digitally programmable RF beamforming weights can be controlled by an external serial interface, or by an on-chip “one-port” mixed-signal adaptation loop that implements a technique that we call double-sampling time-multiplexed LMS (DS-TM-LMS). Unlike conventional LMS-type adaptation algorithms that require access to the individual array inputs and the combined output, and are therefore not easily amenable to a hybrid beamformer, DS-TM-LMS updates the RF-domain weights by accessing only the combined downconverted array outputs. Such adaptation is valuable for adaptive main-lobe, side-lobe or null steering, but more importantly, it can assist/augment codebook-based beam acquisition/tracking algorithms, which may fail in the presence of multipath, on- or off-channel interferers.
本文提出了一种混合波束形成毫米波MIMO接收机,其中有两个关键的创新。首先,它可以配置为三种模式:支持单用户或多用户MIMO的28或37GHz的两个单频段多流模式,以及并发的28和37GHz双频单流相控阵带间载波聚合模式。在所有模式下,接收器具有从每个天线单元输入到每个输出流的完整连接,从而最大限度地利用可用孔径。其次,数字可编程射频波束形成权重可以通过外部串行接口或片上“单端口”混合信号自适应环路控制,该环路实现了我们称为双采样时间复用LMS (DS-TM-LMS)的技术。传统的lms型自适应算法需要访问单个阵列输入和组合输出,因此不容易适用于混合波束形成器,DS-TM-LMS通过仅访问组合下转换阵列输出来更新rf域权重。这种自适应对于自适应主瓣、副瓣或零导向是有价值的,但更重要的是,它可以辅助/增强基于码本的波束捕获/跟踪算法,这些算法可能在存在多径、通道内或通道外干扰时失败。
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引用次数: 21
A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks 用于1Tb/s/mm2模对模光网络的150μW、120μs锁时间数字监督模拟微环波长稳定的10Gb/s硅光子收发器
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310328
Y. Thonnart, M. Zid, J. L. Jiménez, G. Waltener, R. Polster, O. Dubray, F. Lepin, S. Bernabé, S. Menezo, G. Pares, O. Castany, L. Boutafa, P. Grosse, B. Charbonnier, C. Baudot
Silicon photonics has allowed cost reduction and performance improvement for optical interconnects for the past few years, and short-reach wavelength-division-multiplexed (WDM) links have recently emerged thanks to the introduction of microring modulators and filters [1-5]. Nevertheless, the promise of optical networks-on-chip foreseen in [1] has to face the integration challenges of scalable low-footprint elementary drivers and robust operation under heavy thermal stress due to self-heating of the cores with varying loads. This work presents a 3D-stacked CMOS-on-Si-photonic transceiver chip, which includes base building-blocks targeting die-to-die WDM optical communication for multicore processors: 10Gbps 2.5Vpp OOK modulator driver, associated receiver, and digitally-supervised analog wavelength stabilization using microring heaters and remapping for 0-to-90°C operating range, for a total footprint of 0.01mm2 per microring.
硅光子学在过去几年中降低了光学互连的成本并提高了性能,由于微环调制器和滤波器的引入,短距离波分复用(WDM)链路最近出现了[1-5]。然而,在[1]中预见到的片上光网络的前景必须面临可扩展的低占用空间基本驱动程序的集成挑战,以及由于核心在不同负载下自加热而导致的重热应力下的稳健运行。这项工作提出了一种3d堆叠的cmos -on- si光子收发器芯片,其中包括针对多核处理器的模对模WDM光通信的基本构建模块:10Gbps 2.5Vpp OOK调制器驱动程序,相关接收器,以及使用微环加热器的数字监督模拟波长稳定,并在0至90°C的工作范围内重新映射,每个微环的总占地面积为0.01mm2。
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引用次数: 20
A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors 一种由60nm晶体氧化物半导体晶体管组成的20ns写入45ns读取1014周期持久存储器模块
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310395
Shuhei Maeda, S. Ohshita, K. Furutani, Y. Yakubo, T. Ishizu, T. Atsumi, Y. Ando, D. Matsubayashi, K. Kato, T. Okuda, M. Fujita, S. Yamazaki
Development of LSI targeting artificial intelligence (AI) has accelerated, some chips have been used and are commercially available in a number of applications. LSI capable of performing arithmetic operation for deep learning, etc., at low power and high speed is crucial for achieving more sophisticated AI. Power consumption is increasing significantly owing particularly to the practical use of AI, and power reduction techniques are urgently necessary.
针对人工智能(AI)的大规模集成电路的发展已经加速,一些芯片已经在许多应用中使用并商业化。能够以低功耗和高速度进行深度学习等算术运算的LSI对于实现更复杂的人工智能至关重要。由于人工智能的实际应用,功耗正在显著增加,因此迫切需要降低功耗的技术。
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引用次数: 5
A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation 1/2.8英寸24Mpixel CMOS图像传感器,采用全深度深沟隔离技术分离0.9μm单位像素
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310195
Yitae Kim, Wonchul Choi, D. Park, H. Jeoung, Bumsuk Kim, Youngsun Oh, Sung-Hun Oh, Byungjun Park, Euiyeol Kim, Yunki Lee, T. Jung, Yongwoong Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang
CMOS image sensors (CIS) have attracted much attention for the emerging mobile market, and the demand of high-resolution image sensors in mobile applications continues to increase [1-3]. For this reason, pixel pitch has been reduced down to 1.0μσι for mass production. Nevertheless, CISs are continuously scaling down to meet the strong demand for higher-resolution images. However, when the pixel size is reduced down to the sub-micron regime (possibly smaller than the diffraction limit), it is very important to consider photo sensitivity and crosstalk, which determine signal-to-noise ratio (SNR). To minimize degradation of photo sensitivity, back-side illumination (BSI), which collects light at the back side, is widely used instead of front-side illumination. In addition to BSI technology, deep-trench isolation (DTI) has emerged as a leading candidate to suppress crosstalk since it physically isolates the pixel. Previous work shows that partial-depth DTI can be applied in a 1.12μm-pitch pixel [4]. Furthermore, full-depth DTI has been demonstrated in a 1.12μm pixel with 24% larger full-well capacity (FWC), 30% smaller YSNR10, 2.0dB higher SNR, and especially for lower crosstalk (12.5%) compared with a conventional one [5]. In this work, a 24-Mpixel CIS with 0.9μσι unit pixels that takes advantage of full-depth DTI is demonstrated.
CMOS图像传感器(CIS)在新兴的移动市场备受关注,移动应用对高分辨率图像传感器的需求不断增加[1-3]。因此,为了量产,像素间距已经降低到1.0μσι。尽管如此,CISs仍在不断缩小规模,以满足对高分辨率图像的强烈需求。然而,当像素尺寸减小到亚微米级(可能小于衍射极限)时,考虑光敏度和串扰是非常重要的,它们决定了信噪比(SNR)。为了最大限度地减少光敏度的下降,在背面收集光线的背面照明(BSI)被广泛使用,而不是正面照明。除了BSI技术,深沟隔离(DTI)已经成为抑制串扰的主要候选技术,因为它在物理上隔离了像素。先前的研究表明,部分深度DTI可以应用于1.12μm-pitch像素[4]。此外,在1.12μm像素的全深度DTI中,与传统DTI相比,全井容量(FWC)提高24%,YSNR10降低30%,信噪比提高2.0dB,特别是串扰(12.5%)更低[5]。在这项工作中,展示了一个利用全深度DTI的2.4百万像素、0.9μσι单位像素的CIS。
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引用次数: 19
A high-efficiency 28GHz outphasing PA with 23dBm output power using a triaxial balun combiner 采用三轴平衡合成器,输出功率为23dBm的高效28GHz分相PA
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310240
Bagher Rabet, J. Buckwalter
Gigabit-per-second millimeter-wave (mm-wave) access and backhaul networks at 28GHz demand high-order QAM, OFDM, and/or carrier-aggregated waveforms that force the PA to operate under high peak-to-average power ratio (PAPR) [1]. High PAPR requirements aggravate the design of mm-wave Si CMOS and SiGe BiCMOS PAs since a linear response and high efficiency are simultaneously desired. Recent work has demonstrated mm-wave PAs with peak efficiency exceeding 30% at 28GHz for output powers above 20dBm [1-5]. However, high average efficiency associated with high-PAPR waveforms remains elusive. To improve average efficiency, circuit techniques based on Doherty [3] and outphasing [6] have been demonstrated in mm-wave bands. Earlier work using these techniques showed average efficiency with QAM waveforms that is well under 20%.
每秒千兆毫米波(mm-wave)接入和28GHz回程网络需要高阶QAM、OFDM和/或载波聚合波形,这些波形迫使PA在高峰值平均功率比(PAPR)下工作[1]。高PAPR要求加剧了毫米波Si CMOS和SiGe BiCMOS PAs的设计,因为同时需要线性响应和高效率。最近的研究表明,当输出功率大于20dBm时,毫米波PAs在28GHz时的峰值效率超过30%[1-5]。然而,与高papr波形相关的高平均效率仍然是难以捉摸的。为了提高平均效率,基于Doherty[3]和out - phasing[6]的电路技术已经在毫米波波段进行了演示。使用这些技术的早期工作表明,QAM波形的平均效率远低于20%。
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引用次数: 32
A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET 采用16nm FinFET自适应阈值ADC的64Gb/s PAM-4收发器
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310208
Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, A. C. Carusone
ADC-based transceivers having up to 8 bits of resolution have been reported for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantization has been explored [3,4] using performance metrics for the complete link, such as bit-error rate (BER), to optimize the quantizer thresholds. Both [3,4] are PAM-2 (NRZ) receivers, demonstrating non-uniform quantization specifically for a decision feedback equalizer (DFE) at 10Gb/s and a feedforward equalizer (FFE) at 4Gb/s respectively. An LMS algorithm in [4] adjusts the threshold levels requiring fine-tuning (8b resolution). This paper presents a 64Gb/s PAM-4 transceiver utilizing an ADC-based receiver (RX), with an analog front-end (AFE) based on a 6b, 1b folding, flash ADC with adaptive threshold levels. A fast greedy-search algorithm is used to choose the optimal quantizer thresholds for minimum BER over a given channel. This provides a near-optimal way of power-scaling the ADC when the channel loss doesn't require the ADC's full resolution. The optimization can work in the background for any equalizer structure, does not place additional requirements on the ADC design, and never diverges, unlike LMS-based approaches [4].
据报道,基于adc的收发器具有高达8位的分辨率,用于50Gb/s以上的PAM-4链路[1,2],尽管更少的位就足够了,并且为短距离(SR)通道提供更低的功率。为了进一步降低基于adc的有线收发器的功耗,研究人员利用完整链路的性能指标(如误码率(BER))探索了非均匀量化[3,4],以优化量化器阈值。两者[3,4]都是PAM-2 (NRZ)接收器,分别为10Gb/s的决策反馈均衡器(DFE)和4Gb/s的前馈均衡器(FFE)展示了非均匀量化。[4]中的LMS算法调整需要微调的阈值水平(8b分辨率)。本文提出了一个64Gb/s PAM-4收发器,利用基于ADC的接收器(RX),模拟前端(AFE)基于6b, 1b折叠,具有自适应阈值水平的闪存ADC。在给定信道上,采用快速贪婪搜索算法选择最小误码率的最优量化器阈值。当通道损耗不需要ADC的全分辨率时,这提供了一种近乎最佳的ADC功率缩放方式。与基于lms的方法不同,这种优化可以在任何均衡器结构的后台工作,不会对ADC设计提出额外的要求,并且不会发散[4]。
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引用次数: 21
A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO 一个27.8Gb/s 11.5pJ/b 60GHz的28nm CMOS偏振MIMO收发器
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310236
S. Daneshgar, K. Dasgupta, C. Thakkar, A. Chakrabarti, Shuhei Yamada, D. Choudhury, J. Jaussi, B. Casper
The industry-wide impetus on user experience and immersive content for handheld/wearable consumer devices is accelerating the demand for high-speed millimeter-wave (mm-wave) PAN wireless connectivity. Next-generation 60GHz PAN standards [1] have made it mandatory to achieve >20Gb/s rates using wide (4.32GHz or higher) bandwidth. However, in order to support multiple concurrent high-speed links, it is imperative to achieve high spectral efficiency. MIMO techniques allow for such spectrum reuse by employing simultaneous spatial streams. However, unlike at low-GHz frequencies, which exhibit rich multipath scattering and therefore a high-rank TX-RX MIMO channel matrix, mm-wave propagation is fundamentally less diverse due to higher reflection/absorption.
整个行业对手持/可穿戴消费设备的用户体验和沉浸式内容的推动正在加速对高速毫米波(mm-wave) PAN无线连接的需求。下一代60GHz PAN标准[1]已经强制要求使用宽(4.32GHz或更高)带宽实现>20Gb/s的速率。然而,为了支持多个并发高速链路,必须实现高频谱效率。MIMO技术允许这样的频谱重用通过采用同步的空间流。然而,与低ghz频率不同,低ghz频率表现出丰富的多径散射,因此具有高阶TX-RX MIMO信道矩阵,由于更高的反射/吸收,毫米波传播的多样性基本上较低。
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引用次数: 29
F4: Circuit and system techniques for mm-wave multi-antenna systems F4:毫米波多天线系统的电路和系统技术
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310406
P. Busson, H. Luong, C. Hung, H. Krishnaswamy, T. Georgantas, P. Mercier
The 5th generation wireless system (5G) is proposed as the next major revolution of mobile wireless technologies. Carrier frequencies in the mm-wave bands and MIMO/multi-antenna systems are expected to be extensively employed to achieve significantly enhanced data rate, spectral/spatial diversity/efficiency and minimized system latency. The design of commercial high-performance radio transceivers at mm-wave represents a major technical challenge. This forum is focused on current state-of-the-art and future directions of multi-antenna systems in the mm-wave bands, from both system architecture and circuit design perspectives. Key system integration aspects such as antenna design, packaging and built-in self-test will also be covered.
第五代无线系统(5G)被认为是移动无线技术的下一个重大革命。毫米波频段的载波频率和MIMO/多天线系统有望得到广泛应用,以实现显著提高的数据速率、频谱/空间分集/效率和最小化系统延迟。商用高性能毫米波无线电收发器的设计是一个重大的技术挑战。本次论坛将从系统架构和电路设计两方面探讨毫米波波段多天线系统的现状和未来发展方向。关键的系统集成方面,如天线设计,封装和内置自检也将涵盖。
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引用次数: 1
An 8-channel 13GHz ESR-on-a-Chip injection-locked vco-array achieving 200μM-concentration sensitivity 8通道13GHz esr片上注入锁定vco阵列,浓度灵敏度达到200μ m
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310330
Anh Chu, Benedikt Schlecker, K. Lips, M. Ortmanns, J. Anders
Thanks to their unmatched specificity, methods based on magnetic resonance effects are amongst the most powerful spectroscopic techniques available today. Out of these methods, due to the availability of improved electronics at the required frequencies in the tens of GHz region, electron spin resonance (ESR) spectroscopy is gaining significant attention in the research community as a tool in life science and materials science research.
由于其无与伦比的特异性,基于磁共振效应的方法是当今最强大的光谱技术之一。在这些方法中,由于在数十GHz区域所需频率下改进电子器件的可用性,电子自旋共振(ESR)光谱作为生命科学和材料科学研究的工具在研究界受到了极大的关注。
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引用次数: 20
A continuous-mode harmonically tuned 19-to-29.5GHz ultra-linear PA supporting 18Gb/s at 18.4% modulation PAE and 43.5% peak PAE 一种连续模式谐波调谐19- 29.5 ghz超线性放大器,在18.4%调制PAE和43.5%峰值PAE下支持18Gb/s
Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310358
Tso-Wei Li, Min-Yu Huang, Hua Wang
The 5th generation (5G) mm-wave systems are expected to support wideband spectrum-efficient modulations (e.g., 64-QAM or 256-QAM) to achieve Gb/s-link-throughput revolution. These complex modulation schemes, however, often come with high-density constellations that demand stringent linearity, i.e. AM-AM and AM-PM, on the mm-wave front-end circuits, in particular, the power amplifiers (PAs). In addition, to support future massive MIMOs, the mm-wave front-ends should be ultra-efficient in both their energy efficiency and area usage, posing even more constraints on the PA designs [1-5].
第五代(5G)毫米波系统预计将支持宽带频谱高效调制(例如64-QAM或256-QAM),以实现Gb/s链路吞吐量革命。然而,这些复杂的调制方案通常伴随着高密度的星座,要求严格的线性,即AM-AM和AM-PM,在毫米波前端电路上,特别是功率放大器(pa)。此外,为了支持未来的大规模mimo,毫米波前端在能源效率和面积使用方面都应该是超高效的,这对PA设计提出了更多的限制[1-5]。
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引用次数: 48
期刊
2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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