Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310219
Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee
With the advent of the IoT era, billions of devices are connected to networks, and assuring sufficient security at low cost is a critical concern. Physically Unclonable Functions (PUFs) have drawn increasing attention as key security building blocks for authentication since each PUF circuit has unique challenge response pairs (CRPs). Such uniqueness is achieved by maximizing the effects of process variation using process-sensitive circuits, i.e. PUF cells. Recently reported PUF cell types include cells based on a two-transistor amplifier [1], NAND gate [2], ring oscillator [3], current mirror [4], back-to-back connected inverters [5], and inverter [6]. Regardless of the variation source, PUFs inevitably include CRPs that respond inconsistently when the process variation of the compared element in the CRP is small compared to noise. For example, if the output of a two-transistor amplifier in [1] is near the switching threshold, the output can be inconsistent, resulting in bit error and an unstable CRP. Thus, efforts have focused on stabilizing unstable CRPs. The most straightforward stabilization scheme is temporal majority voting (TMV) [1,5], but the improvement in bit error rate (BER) and stability is limited since it does not directly address the instability of a given CRP. Trimming [2,3,5,6], another widely used approach, improves BER/stability by discarding unstable CRPs. However, stability evaluation is not very accurate, so the number of discarded CRPs can be significant (up to 30% in [3]), increasing the required silicon area for additional CRP generation and making it prohibitive for cost-sensitive IoT applications. This is especially true for weak PUFs. In this paper, a leakage-based PUF that allows lossless stabilization through remapping of unstable PUF cell pairs is presented. BER and stability comparable to, or better than, trimming stabilization method are achieved without discarding CRPs.
{"title":"A 445F2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT Security","authors":"Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee","doi":"10.1109/ISSCC.2018.8310219","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310219","url":null,"abstract":"With the advent of the IoT era, billions of devices are connected to networks, and assuring sufficient security at low cost is a critical concern. Physically Unclonable Functions (PUFs) have drawn increasing attention as key security building blocks for authentication since each PUF circuit has unique challenge response pairs (CRPs). Such uniqueness is achieved by maximizing the effects of process variation using process-sensitive circuits, i.e. PUF cells. Recently reported PUF cell types include cells based on a two-transistor amplifier [1], NAND gate [2], ring oscillator [3], current mirror [4], back-to-back connected inverters [5], and inverter [6]. Regardless of the variation source, PUFs inevitably include CRPs that respond inconsistently when the process variation of the compared element in the CRP is small compared to noise. For example, if the output of a two-transistor amplifier in [1] is near the switching threshold, the output can be inconsistent, resulting in bit error and an unstable CRP. Thus, efforts have focused on stabilizing unstable CRPs. The most straightforward stabilization scheme is temporal majority voting (TMV) [1,5], but the improvement in bit error rate (BER) and stability is limited since it does not directly address the instability of a given CRP. Trimming [2,3,5,6], another widely used approach, improves BER/stability by discarding unstable CRPs. However, stability evaluation is not very accurate, so the number of discarded CRPs can be significant (up to 30% in [3]), increasing the required silicon area for additional CRP generation and making it prohibitive for cost-sensitive IoT applications. This is especially true for weak PUFs. In this paper, a leakage-based PUF that allows lossless stabilization through remapping of unstable PUF cell pairs is presented. BER and stability comparable to, or better than, trimming stabilization method are achieved without discarding CRPs.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"31 1","pages":"132-134"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87480774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310338
Jingzhi Zhang, Huihua Liu, Chenxi Zhao, K. Kang
Future cross-network and international roaming are attractive in mm-wave fifth-generation (5G) wireless networks with multiband operations. The generation of an ultra-wide-bandwidth ultra-low-phase-noise (PN) local oscillator (LO) signal in massive multiple-input multiple-output (MIMO) transceivers, which support spectra around 28GHz, 37GHz, and 39GHz, becomes a significant challenge. Injection-locked frequency tripler (ILFT) is a good candidate for LO generation due to its low PN property while suffering from a narrow locking range. Varactors are often used to tune the free-running frequency to increase the bandwidth [1]. However, the PN performance degrades when the target frequency is far away from the free-running frequency, which means a complex calibration mechanism must be applied [2,3]. Meanwhile, an ILFT with such a self-calibration circuit still suffers from a narrow locking range, which cannot support multiband operations. To simplify the system design and meet the multiband requirement, a tuning-less ILFT with an ultra-wide locking range is seen as an appropriate solution for mm-wave multiband 5G applications.
{"title":"A 22.8-to-43.2GHz tuning-less injection-locked frequency tripler using injection-current boosting with 76.4% locking range for multiband 5G applications","authors":"Jingzhi Zhang, Huihua Liu, Chenxi Zhao, K. Kang","doi":"10.1109/ISSCC.2018.8310338","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310338","url":null,"abstract":"Future cross-network and international roaming are attractive in mm-wave fifth-generation (5G) wireless networks with multiband operations. The generation of an ultra-wide-bandwidth ultra-low-phase-noise (PN) local oscillator (LO) signal in massive multiple-input multiple-output (MIMO) transceivers, which support spectra around 28GHz, 37GHz, and 39GHz, becomes a significant challenge. Injection-locked frequency tripler (ILFT) is a good candidate for LO generation due to its low PN property while suffering from a narrow locking range. Varactors are often used to tune the free-running frequency to increase the bandwidth [1]. However, the PN performance degrades when the target frequency is far away from the free-running frequency, which means a complex calibration mechanism must be applied [2,3]. Meanwhile, an ILFT with such a self-calibration circuit still suffers from a narrow locking range, which cannot support multiband operations. To simplify the system design and meet the multiband requirement, a tuning-less ILFT with an ultra-wide locking range is seen as an appropriate solution for mm-wave multiband 5G applications.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"1 1","pages":"370-372"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89852432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310395
Shuhei Maeda, S. Ohshita, K. Furutani, Y. Yakubo, T. Ishizu, T. Atsumi, Y. Ando, D. Matsubayashi, K. Kato, T. Okuda, M. Fujita, S. Yamazaki
Development of LSI targeting artificial intelligence (AI) has accelerated, some chips have been used and are commercially available in a number of applications. LSI capable of performing arithmetic operation for deep learning, etc., at low power and high speed is crucial for achieving more sophisticated AI. Power consumption is increasing significantly owing particularly to the practical use of AI, and power reduction techniques are urgently necessary.
{"title":"A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors","authors":"Shuhei Maeda, S. Ohshita, K. Furutani, Y. Yakubo, T. Ishizu, T. Atsumi, Y. Ando, D. Matsubayashi, K. Kato, T. Okuda, M. Fujita, S. Yamazaki","doi":"10.1109/ISSCC.2018.8310395","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310395","url":null,"abstract":"Development of LSI targeting artificial intelligence (AI) has accelerated, some chips have been used and are commercially available in a number of applications. LSI capable of performing arithmetic operation for deep learning, etc., at low power and high speed is crucial for achieving more sophisticated AI. Power consumption is increasing significantly owing particularly to the practical use of AI, and power reduction techniques are urgently necessary.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"9 1","pages":"484-486"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91542907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310217
N. E. C. Akkaya, B. Erbagci, K. Mai
With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production, counterfeiting, IP theft, and hardware Trojan Horses. A parallel and related threat is posed by advanced reverse engineering capabilities, such that even chips manufactured at the most advanced technology nodes can be de-layered, imaged, and analyzed [1]. While various manufacturing methodologies and camouflaged gates have been proposed, none fully address these threats, especially in combination. To address these concerns, we use post-manufacturing programmable camouflaged logic topology to simultaneously obscure the design IP from the manufacturer as well as combat reverse engineering. The basis of the design is a threshold-voltage-defined (TVD) logic gate topology that solely uses different threshold voltage implants to determine the logic gate function [2]. Every gate has an identical physical layout and is post-manufacturing programmed with different threshold voltages for different Boolean functions using intentional directed hot-carrier injection (HCI). Similar intentional HCI techniques have previously been used to enhance SRAM margins, boost PUF reliability, and build TRNGs [3][4]. The design is fully compatible with standard CMOS logic processes, requiring no special layers, structures, or process steps.
{"title":"A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD","authors":"N. E. C. Akkaya, B. Erbagci, K. Mai","doi":"10.1109/ISSCC.2018.8310217","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310217","url":null,"abstract":"With the continued globalization of the IC manufacturing supply chain, securing that supply chain is becoming increasingly difficult and this opens the door to a myriad of security threats such as unauthorized production, counterfeiting, IP theft, and hardware Trojan Horses. A parallel and related threat is posed by advanced reverse engineering capabilities, such that even chips manufactured at the most advanced technology nodes can be de-layered, imaged, and analyzed [1]. While various manufacturing methodologies and camouflaged gates have been proposed, none fully address these threats, especially in combination. To address these concerns, we use post-manufacturing programmable camouflaged logic topology to simultaneously obscure the design IP from the manufacturer as well as combat reverse engineering. The basis of the design is a threshold-voltage-defined (TVD) logic gate topology that solely uses different threshold voltage implants to determine the logic gate function [2]. Every gate has an identical physical layout and is post-manufacturing programmed with different threshold voltages for different Boolean functions using intentional directed hot-carrier injection (HCI). Similar intentional HCI techniques have previously been used to enhance SRAM margins, boost PUF reliability, and build TRNGs [3][4]. The design is fully compatible with standard CMOS logic processes, requiring no special layers, structures, or process steps.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"20 1","pages":"128-130"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72794673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310189
Susnata Mondal, Rahul Singh, J. Paramesh
This paper presents a hybrid beamforming mm-wave MIMO receiver with two key innovations. First, it can be configured into three modes: two single-band multistream modes at 28 or 37 GHz that can support single-or multi-user MIMO, and a concurrent 28 and 37GHz dual-band single-stream phased-array inter-band carrier-aggregation mode. In all modes, the receiver features full connectivity from each antenna element input to each output stream, thereby maximizing usage of the available aperture. Second, the digitally programmable RF beamforming weights can be controlled by an external serial interface, or by an on-chip “one-port” mixed-signal adaptation loop that implements a technique that we call double-sampling time-multiplexed LMS (DS-TM-LMS). Unlike conventional LMS-type adaptation algorithms that require access to the individual array inputs and the combined output, and are therefore not easily amenable to a hybrid beamformer, DS-TM-LMS updates the RF-domain weights by accessing only the combined downconverted array outputs. Such adaptation is valuable for adaptive main-lobe, side-lobe or null steering, but more importantly, it can assist/augment codebook-based beam acquisition/tracking algorithms, which may fail in the presence of multipath, on- or off-channel interferers.
{"title":"A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation","authors":"Susnata Mondal, Rahul Singh, J. Paramesh","doi":"10.1109/ISSCC.2018.8310189","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310189","url":null,"abstract":"This paper presents a hybrid beamforming mm-wave MIMO receiver with two key innovations. First, it can be configured into three modes: two single-band multistream modes at 28 or 37 GHz that can support single-or multi-user MIMO, and a concurrent 28 and 37GHz dual-band single-stream phased-array inter-band carrier-aggregation mode. In all modes, the receiver features full connectivity from each antenna element input to each output stream, thereby maximizing usage of the available aperture. Second, the digitally programmable RF beamforming weights can be controlled by an external serial interface, or by an on-chip “one-port” mixed-signal adaptation loop that implements a technique that we call double-sampling time-multiplexed LMS (DS-TM-LMS). Unlike conventional LMS-type adaptation algorithms that require access to the individual array inputs and the combined output, and are therefore not easily amenable to a hybrid beamformer, DS-TM-LMS updates the RF-domain weights by accessing only the combined downconverted array outputs. Such adaptation is valuable for adaptive main-lobe, side-lobe or null steering, but more importantly, it can assist/augment codebook-based beam acquisition/tracking algorithms, which may fail in the presence of multipath, on- or off-channel interferers.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"46 1","pages":"72-74"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80348719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310276
Hanli Liu, Dexian Tang, Zheng Sun, W. Deng, H. Ngo, K. Okada, A. Matsuzawa
In a world that has become increasingly connected by the Internet, ultra-low-power (ULP) transceivers (TRX) will be key elements in a variety of short-range network applications. The RF pLl in a TRX needs a significant amount of power due to the phase noise and spurious requirement. Compared with the analog PLLs, an ADPLL is more advantageous in nm-CMOS technologies [1-6]. This paper presents a 2.0-to-2.8GHz 653μW fractional-N ADPLL that achieves −242dB FOM in 65nm CMOS for 2.4GHz ISM band applications. The best power-jitter trade-off is achieved at 981μW using a reference doubler with 535fs jitter and a −56dBc in-band fractional spur, which corresponds to a FOM of −246dB. Thanks to the proposed 10b isolated constant-slope DTC, this ADPLL breaks the −240dB FOM barrier of sub-mW fractional-N ADPLLs.
{"title":"A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of −246dB for IoT applications in 65nm CMOS","authors":"Hanli Liu, Dexian Tang, Zheng Sun, W. Deng, H. Ngo, K. Okada, A. Matsuzawa","doi":"10.1109/ISSCC.2018.8310276","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310276","url":null,"abstract":"In a world that has become increasingly connected by the Internet, ultra-low-power (ULP) transceivers (TRX) will be key elements in a variety of short-range network applications. The RF pLl in a TRX needs a significant amount of power due to the phase noise and spurious requirement. Compared with the analog PLLs, an ADPLL is more advantageous in nm-CMOS technologies [1-6]. This paper presents a 2.0-to-2.8GHz 653μW fractional-N ADPLL that achieves −242dB FOM in 65nm CMOS for 2.4GHz ISM band applications. The best power-jitter trade-off is achieved at 981μW using a reference doubler with 535fs jitter and a −56dBc in-band fractional spur, which corresponds to a FOM of −246dB. Thanks to the proposed 10b isolated constant-slope DTC, this ADPLL breaks the −240dB FOM barrier of sub-mW fractional-N ADPLLs.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"1 1","pages":"246-248"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76042435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310221
Kamala Raghavan Sadagopan, Jian Kang, Y. Ramadass, A. Natarajan
Leveraging the ubiquitous WiFi infrastructure to wirelessly power sensors can enable perpetually powered sensors for several monitoring and asset-tracking IoT applications. Small form factor is often desirable to ensure unobtrusive sensors. However, typical 2.4GHz WiFi output power of <+20dBm implies ∼−30dBm (μW) incident power (assuming free space path loss) at a ∼3m range. This presents a fundamental trade-off since small antenna area can further restrict the wireless power available to the rectifier/harvester. In addition, the time-varying nature of RF wireless powering implies that the energy-harvesting approach must accommodate cold start. In this work, we address the challenge of simultaneously achieving small form factor, μW-scale wireless input sensitivity, and operation at relatively high frequency (2.4GHz) by co-designing the antenna, rectifier, and DC-DC converter, achieving −36dBm input sensitivity for a 0.8V output in primary operating mode and −33dBm sensitivity from cold start with overall 1.97cm2 area (including antenna). In contrast to prior work, the proposed wireless harvesting approach optimally extracts energy from the wireless beacon even with < −30dBm (μW) incident power levels. The harvester consumes 960pW quiescent power while supporting cold start. The feasibility of the proposed approach is demonstrated by harvesting energy from a commercial WiFi node.
{"title":"A 960pW Co-Integrated-Antenna Wireless Energy Harvester for WiFi Backchannel Wireless Powering","authors":"Kamala Raghavan Sadagopan, Jian Kang, Y. Ramadass, A. Natarajan","doi":"10.1109/ISSCC.2018.8310221","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310221","url":null,"abstract":"Leveraging the ubiquitous WiFi infrastructure to wirelessly power sensors can enable perpetually powered sensors for several monitoring and asset-tracking IoT applications. Small form factor is often desirable to ensure unobtrusive sensors. However, typical 2.4GHz WiFi output power of <+20dBm implies ∼−30dBm (μW) incident power (assuming free space path loss) at a ∼3m range. This presents a fundamental trade-off since small antenna area can further restrict the wireless power available to the rectifier/harvester. In addition, the time-varying nature of RF wireless powering implies that the energy-harvesting approach must accommodate cold start. In this work, we address the challenge of simultaneously achieving small form factor, μW-scale wireless input sensitivity, and operation at relatively high frequency (2.4GHz) by co-designing the antenna, rectifier, and DC-DC converter, achieving −36dBm input sensitivity for a 0.8V output in primary operating mode and −33dBm sensitivity from cold start with overall 1.97cm2 area (including antenna). In contrast to prior work, the proposed wireless harvesting approach optimally extracts energy from the wireless beacon even with < −30dBm (μW) incident power levels. The harvester consumes 960pW quiescent power while supporting cold start. The feasibility of the proposed approach is demonstrated by harvesting energy from a commercial WiFi node.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"44 1","pages":"136-138"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76979278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310379
J. Moody, Pouyan Bassirian, Abhishek Roy, Ningxi Liu, Stephen Pancrazio, N. Scott Barker, B. Calhoun, S. Bowers
Event-driven sensor nodes have applications in agriculture, infrastructure, and perimeter monitoring and are characterized by spending the vast majority of their time in an asleep-yet-alert state. In this state, the node must wake to incoming RF wakeup commands from an antenna with minimal dc power, as the total percentage of power in sleep mode dominates if wakeup events are sufficiently infrequent. The RF wakeup receiver (WuRX) is one critical block of the node's asleep-yet-alert state. It must maximize sensitivity with power consumptions of 10nW or less to maximize battery lifetime or even enable battery-less systems that persist on energy harvesting [1-3]. These WuRXs must reliably detect wakeup signals as well as reject false wakeups caused by external interferer signals or noise. Otherwise, booting the full node into its active state when it is not needed can quickly relinquish power savings created by the wakeup radio in its asleep-yet-alert state.
{"title":"A −76dBm 7.4nW wakeup radio with automatic offset compensation","authors":"J. Moody, Pouyan Bassirian, Abhishek Roy, Ningxi Liu, Stephen Pancrazio, N. Scott Barker, B. Calhoun, S. Bowers","doi":"10.1109/ISSCC.2018.8310379","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310379","url":null,"abstract":"Event-driven sensor nodes have applications in agriculture, infrastructure, and perimeter monitoring and are characterized by spending the vast majority of their time in an asleep-yet-alert state. In this state, the node must wake to incoming RF wakeup commands from an antenna with minimal dc power, as the total percentage of power in sleep mode dominates if wakeup events are sufficiently infrequent. The RF wakeup receiver (WuRX) is one critical block of the node's asleep-yet-alert state. It must maximize sensitivity with power consumptions of 10nW or less to maximize battery lifetime or even enable battery-less systems that persist on energy harvesting [1-3]. These WuRXs must reliably detect wakeup signals as well as reject false wakeups caused by external interferer signals or noise. Otherwise, booting the full node into its active state when it is not needed can quickly relinquish power savings created by the wakeup radio in its asleep-yet-alert state.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"22 1","pages":"452-454"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73355804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310286
Ilter Özkaya, A. Cevrero, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, L. Kull, M. Kossel, D. Luu, M. Meghelli, Y. Leblebici, T. Toifl
The increasing bandwidth demand in data-centers requires wireline transceivers supporting >50Gb/s/lane data-rates with low power consumption. Because link utilization in data-centers is <10% for 99% of the links [1] a promising way to reduce power consumption is fine-grained power gating, where the link is powered off during idle time. For rapid on/off functionality to be efficient with short data bursts, the link needs to wake up within a few ns, which is challenging at high speeds. Burst mode operation was previously demonstrated at 25Gb/s with 18.5ns lock-time [2] without power cycling.
{"title":"A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS","authors":"Ilter Özkaya, A. Cevrero, P. Francese, C. Menolfi, M. Braendli, T. Morf, D. Kuchta, L. Kull, M. Kossel, D. Luu, M. Meghelli, Y. Leblebici, T. Toifl","doi":"10.1109/ISSCC.2018.8310286","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310286","url":null,"abstract":"The increasing bandwidth demand in data-centers requires wireline transceivers supporting >50Gb/s/lane data-rates with low power consumption. Because link utilization in data-centers is <10% for 99% of the links [1] a promising way to reduce power consumption is fine-grained power gating, where the link is powered off during idle time. For rapid on/off functionality to be efficient with short data bursts, the link needs to wake up within a few ns, which is challenging at high speeds. Burst mode operation was previously demonstrated at 25Gb/s with 18.5ns lock-time [2] without power cycling.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"36 1","pages":"266-268"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75073139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310328
Y. Thonnart, M. Zid, J. L. Jiménez, G. Waltener, R. Polster, O. Dubray, F. Lepin, S. Bernabé, S. Menezo, G. Pares, O. Castany, L. Boutafa, P. Grosse, B. Charbonnier, C. Baudot
Silicon photonics has allowed cost reduction and performance improvement for optical interconnects for the past few years, and short-reach wavelength-division-multiplexed (WDM) links have recently emerged thanks to the introduction of microring modulators and filters [1-5]. Nevertheless, the promise of optical networks-on-chip foreseen in [1] has to face the integration challenges of scalable low-footprint elementary drivers and robust operation under heavy thermal stress due to self-heating of the cores with varying loads. This work presents a 3D-stacked CMOS-on-Si-photonic transceiver chip, which includes base building-blocks targeting die-to-die WDM optical communication for multicore processors: 10Gbps 2.5Vpp OOK modulator driver, associated receiver, and digitally-supervised analog wavelength stabilization using microring heaters and remapping for 0-to-90°C operating range, for a total footprint of 0.01mm2 per microring.
{"title":"A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks","authors":"Y. Thonnart, M. Zid, J. L. Jiménez, G. Waltener, R. Polster, O. Dubray, F. Lepin, S. Bernabé, S. Menezo, G. Pares, O. Castany, L. Boutafa, P. Grosse, B. Charbonnier, C. Baudot","doi":"10.1109/ISSCC.2018.8310328","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310328","url":null,"abstract":"Silicon photonics has allowed cost reduction and performance improvement for optical interconnects for the past few years, and short-reach wavelength-division-multiplexed (WDM) links have recently emerged thanks to the introduction of microring modulators and filters [1-5]. Nevertheless, the promise of optical networks-on-chip foreseen in [1] has to face the integration challenges of scalable low-footprint elementary drivers and robust operation under heavy thermal stress due to self-heating of the cores with varying loads. This work presents a 3D-stacked CMOS-on-Si-photonic transceiver chip, which includes base building-blocks targeting die-to-die WDM optical communication for multicore processors: 10Gbps 2.5Vpp OOK modulator driver, associated receiver, and digitally-supervised analog wavelength stabilization using microring heaters and remapping for 0-to-90°C operating range, for a total footprint of 0.01mm2 per microring.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"130 1","pages":"350-352"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75588071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：