Aiming at the problems of high bit error rate and large channel high-frequency loss in high-speed transmission, an adaptive equalizer suitable for 56 Gb/s PAM4 SerDes is designed. In order to improve the signal transmission bandwidth, PAM4 signal is used instead of NRZ signal. In order to improve the equalization effect, 4-tap FFE is used for pre-emphasis at the transmitter, and a two-stage CTLE is used for coarse equalization at the receiver. Furthermore, digital based 16-tap adaptive FFE and 1-tap adaptive DFE are used at the receiver to further reduce the bit error rate. Simulation results show that the equalizer can work at the rate of 56 Gb/s, and the eye diagram of PAM4 signal is obviously open. Compared with the traditional adaptive equalizer, it can effectively reduce the convergence time and bit error rate.
{"title":"An Adaptive Equalizer for 56 Gb/s PAM4 SerDes","authors":"Miaomiao Wu, Ming-Shiang Lai, Fangxu Lv, Jianjun Shi, Heming Wang, Zheng Wang, Zixiang Tang, Chaolong Xu","doi":"10.1109/ICICM54364.2021.9660321","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660321","url":null,"abstract":"Aiming at the problems of high bit error rate and large channel high-frequency loss in high-speed transmission, an adaptive equalizer suitable for 56 Gb/s PAM4 SerDes is designed. In order to improve the signal transmission bandwidth, PAM4 signal is used instead of NRZ signal. In order to improve the equalization effect, 4-tap FFE is used for pre-emphasis at the transmitter, and a two-stage CTLE is used for coarse equalization at the receiver. Furthermore, digital based 16-tap adaptive FFE and 1-tap adaptive DFE are used at the receiver to further reduce the bit error rate. Simulation results show that the equalizer can work at the rate of 56 Gb/s, and the eye diagram of PAM4 signal is obviously open. Compared with the traditional adaptive equalizer, it can effectively reduce the convergence time and bit error rate.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77630336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660330
Zichen Ding, Zhiqun Li, Zhennan Li, Yan Yao
This paper presents an 8-16GHz low-noise voltage-controlled oscillator (VCO) for microwave broadband frequency sources in 130nm SiGe BiCMOS. Four narrowband Colpitts oscillators and a multiplexer (MUX) are used to implement a VCO array with wide band feature. Each Colpitts VCO core is equipped 2bit capacitors switches to extend its tuning range. A variable bias is used to reduce phase noise after state of switches change. The simulation results show that the actual tuning range covers 11.3-22.3GHz, and the phase noise is less than -87dBc/Hz at 100kHz offset and less than -107.2dBc/Hz at 1MHz offset.
{"title":"An 8-16GHz Wideband VCO in 130nm SiGe BiCMOS","authors":"Zichen Ding, Zhiqun Li, Zhennan Li, Yan Yao","doi":"10.1109/ICICM54364.2021.9660330","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660330","url":null,"abstract":"This paper presents an 8-16GHz low-noise voltage-controlled oscillator (VCO) for microwave broadband frequency sources in 130nm SiGe BiCMOS. Four narrowband Colpitts oscillators and a multiplexer (MUX) are used to implement a VCO array with wide band feature. Each Colpitts VCO core is equipped 2bit capacitors switches to extend its tuning range. A variable bias is used to reduce phase noise after state of switches change. The simulation results show that the actual tuning range covers 11.3-22.3GHz, and the phase noise is less than -87dBc/Hz at 100kHz offset and less than -107.2dBc/Hz at 1MHz offset.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74444744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660262
Yuan Ma, Xuecheng Wang, Milin Zhang
This paper presents a differential 62. 5kS/s, 300nW,8bit successive approximation register (SAR) analog-to-digital converters (ADC) in 40nm CMOS technology occupying a silicon area of $0.005mathrm{m}mathrm{m}^{2}$. An algorithm that calculates the impact of capacitor mismatch errors and parasitic effects on performance for multi-structure comparison and area optimization has been proposed. The measured FOM of the proposed ADC is 14.9fJ/c-s at 62. 5kS/s with Effective number of bits (ENoB) of 8. 3bits, spurious free dynamic range (SFDR) of 63.34 dB and total harmonic distortion (THD) of 60.9 dB are achieved.
{"title":"Design of a 0.005mm2 8.5ENoB 14.9 fJ/conv-step SAR ADC for Biomedical Application","authors":"Yuan Ma, Xuecheng Wang, Milin Zhang","doi":"10.1109/ICICM54364.2021.9660262","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660262","url":null,"abstract":"This paper presents a differential 62. 5kS/s, 300nW,8bit successive approximation register (SAR) analog-to-digital converters (ADC) in 40nm CMOS technology occupying a silicon area of $0.005mathrm{m}mathrm{m}^{2}$. An algorithm that calculates the impact of capacitor mismatch errors and parasitic effects on performance for multi-structure comparison and area optimization has been proposed. The measured FOM of the proposed ADC is 14.9fJ/c-s at 62. 5kS/s with Effective number of bits (ENoB) of 8. 3bits, spurious free dynamic range (SFDR) of 63.34 dB and total harmonic distortion (THD) of 60.9 dB are achieved.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74864536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660347
Jun’an Zhang, Min Jiang, Qingwei Zhang
This paper introduces an equivalent circuit modelfor Negative Bias Temperature Instability (NBTI) effect in 65nm PMOS. Comparing with other models based on physical effect mechanism, the method of equivalent circuit model is more practical. Based on PMOS model of an existing 65nm CMOS PDK, several common electrical components and arithmetic units are utilized to form an equivalent circuit. The components include resistor, voltage source, current source, voltage-controlled voltage source, voltage controlled current source, current controlled current source, adder, multiplier, etc. Four input parameters, such as width of gate (W), length of gate (L), ambient temperature (temp), operation period (t), are included in this equivalent circuit model. This model also considered the voltage stress of drain-source, drain-gate, and gate-source. The simulation results show that the electrical performance of PMOS transistor under NBTI is fitted the measured data of many published papers. The equivalent circuit model will be utilized for long period reliability integrated circuit design in the future.
{"title":"An Equivalent Circuit Model for Negative Bias Temperature Instability Effect in 65nm PMOS","authors":"Jun’an Zhang, Min Jiang, Qingwei Zhang","doi":"10.1109/ICICM54364.2021.9660347","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660347","url":null,"abstract":"This paper introduces an equivalent circuit modelfor Negative Bias Temperature Instability (NBTI) effect in 65nm PMOS. Comparing with other models based on physical effect mechanism, the method of equivalent circuit model is more practical. Based on PMOS model of an existing 65nm CMOS PDK, several common electrical components and arithmetic units are utilized to form an equivalent circuit. The components include resistor, voltage source, current source, voltage-controlled voltage source, voltage controlled current source, current controlled current source, adder, multiplier, etc. Four input parameters, such as width of gate (W), length of gate (L), ambient temperature (temp), operation period (t), are included in this equivalent circuit model. This model also considered the voltage stress of drain-source, drain-gate, and gate-source. The simulation results show that the electrical performance of PMOS transistor under NBTI is fitted the measured data of many published papers. The equivalent circuit model will be utilized for long period reliability integrated circuit design in the future.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85193300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The surface mount device (SMD) packaging is becoming one of the most widely used high-power semiconductor device packaging forms because of its small size and low thermal resistance. However, the SMD package will suffer greater thermal stress when mounted on the PCB, because it has no lead-out terminals and is soldered to the PCB directly. This paper introduces a failure analysis case of a SMD-0.5 packaged device with stress fracture in the ceramic of package. Through analysis, it is found that package cracks occurred during the temperature cycling of the circuit board assembly. Based on the analysis of ceramic characteristics, the cause of the failure is the thermal mismatch between ceramic and PCB. In addition, the paper analyzes the influence of the PCB’s thermal expansion coefficient and solder joint morphology on the cracks of the package ceramic through simulation and experiments. Finally, the paper gives application suggestions for SMD packaged devices.
{"title":"Analysis of Crack Failure in SMD Package Caused by Thermal Stress","authors":"Haiming Zhang, Zhaoxi Wu, Meng Meng, Xu Wang, Zhimin Ding, Chao Duan, Liwei Han, Fangyuan Li","doi":"10.1109/ICICM54364.2021.9660253","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660253","url":null,"abstract":"The surface mount device (SMD) packaging is becoming one of the most widely used high-power semiconductor device packaging forms because of its small size and low thermal resistance. However, the SMD package will suffer greater thermal stress when mounted on the PCB, because it has no lead-out terminals and is soldered to the PCB directly. This paper introduces a failure analysis case of a SMD-0.5 packaged device with stress fracture in the ceramic of package. Through analysis, it is found that package cracks occurred during the temperature cycling of the circuit board assembly. Based on the analysis of ceramic characteristics, the cause of the failure is the thermal mismatch between ceramic and PCB. In addition, the paper analyzes the influence of the PCB’s thermal expansion coefficient and solder joint morphology on the cracks of the package ceramic through simulation and experiments. Finally, the paper gives application suggestions for SMD packaged devices.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91340217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660345
B. Mao, N. Tan, Ting Chong, Lei Li
A fast interrupt response time is a very important feature for embedded processors. In this paper, we design a fast interrupt system for embedded RISC-V processors. It is further extended on the Core-Local Interrupt Controller (CLIC) based interrupt system. When an interrupt happens, the general-purpose registers and other interrupt related registers such as Control and Status Registers (CSRs) are pushed to the stack memory automatically. Thus, there is no additional software overhead in the Interrupt Service Routine (ISR), and the real handler code can be executed immediately. The interrupt response time of the interrupt system based on the CLIC extension is shorter than that of a RISC-V processor only employing the CLIC, and is comparable to that of an ARM}
{"title":"A CLIC Extension Based Fast Interrupt System for Embedded RISC-V Processors","authors":"B. Mao, N. Tan, Ting Chong, Lei Li","doi":"10.1109/ICICM54364.2021.9660345","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660345","url":null,"abstract":"A fast interrupt response time is a very important feature for embedded processors. In this paper, we design a fast interrupt system for embedded RISC-V processors. It is further extended on the Core-Local Interrupt Controller (CLIC) based interrupt system. When an interrupt happens, the general-purpose registers and other interrupt related registers such as Control and Status Registers (CSRs) are pushed to the stack memory automatically. Thus, there is no additional software overhead in the Interrupt Service Routine (ISR), and the real handler code can be executed immediately. The interrupt response time of the interrupt system based on the CLIC extension is shorter than that of a RISC-V processor only employing the CLIC, and is comparable to that of an ARM}","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83201165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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