Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660276
Hongguang Zhang, Zhiqiang Zhang, Yuanyuan Gong, Yanan Zhang, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao
An 8Gb3200Mbps DDR4 SDRAM with fast clock gating and ODT path self-align technique is presented. Fast clock gating is utilized in the DDR4 SDRAM to pursue cut down DLL, read, write and ODT Paths stage, thus data jitters and current consumption can be reduced. ODT path delay self-align method is proposed to the DDR4 SDRAM which is implemented in DRAM process. Measurement results show fast clock gating can reduce 12 stages in DLL, read, write and ODT path and reduce 600uA current, and 5.4% jitters in Read and ODT path. What’s more, the measurement results also show the tADC variation is reduced from 220ps to 30ps with delay self-align technique.
{"title":"A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align","authors":"Hongguang Zhang, Zhiqiang Zhang, Yuanyuan Gong, Yanan Zhang, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao","doi":"10.1109/ICICM54364.2021.9660276","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660276","url":null,"abstract":"An 8Gb3200Mbps DDR4 SDRAM with fast clock gating and ODT path self-align technique is presented. Fast clock gating is utilized in the DDR4 SDRAM to pursue cut down DLL, read, write and ODT Paths stage, thus data jitters and current consumption can be reduced. ODT path delay self-align method is proposed to the DDR4 SDRAM which is implemented in DRAM process. Measurement results show fast clock gating can reduce 12 stages in DLL, read, write and ODT path and reduce 600uA current, and 5.4% jitters in Read and ODT path. What’s more, the measurement results also show the tADC variation is reduced from 220ps to 30ps with delay self-align technique.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"50 1","pages":"171-174"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78277998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660218
Yue Bing, Zhou Luyao, Yang Zhi, Zhao Lin, Lin Haofan, Yang Yong
The oil chromatographic data of the high-voltage reactor in an UHV substation was abnormal, and subsequent live detection measures were taken for this defect, including high-frequency partial discharge test, UHF partial discharge test, ultrasonic partial discharge test, and vibration monitoring. This paper comprehensively analyzed the test data, judges that there was discharge inside, and basically judged the discharge position in the Y-pillar area of the high-voltage reactor, and put forward suggestions and opinions for subsequent disposal measures and operation and maintenance measures.
{"title":"Analysis of Abnormal Defects of High Resistance of 1000 kV UHV Transmission Line","authors":"Yue Bing, Zhou Luyao, Yang Zhi, Zhao Lin, Lin Haofan, Yang Yong","doi":"10.1109/ICICM54364.2021.9660218","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660218","url":null,"abstract":"The oil chromatographic data of the high-voltage reactor in an UHV substation was abnormal, and subsequent live detection measures were taken for this defect, including high-frequency partial discharge test, UHF partial discharge test, ultrasonic partial discharge test, and vibration monitoring. This paper comprehensively analyzed the test data, judges that there was discharge inside, and basically judged the discharge position in the Y-pillar area of the high-voltage reactor, and put forward suggestions and opinions for subsequent disposal measures and operation and maintenance measures.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"36 1","pages":"362-365"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78609071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660240
Linyu Xu, Xiushan Wu, Yuqi Zeng
With the rapid development of micromechanical technology and the maturity of integrated circuit technology, which have made it possible to make miniaturization of high-performance frequency control devices. The piezoelectric film bulk acoustic resonator (FBAR) has gradually become one of the research hotspots of RF filters. This paper mainly derives the electrical impedance model of FBAR based on the sound wave transmission characteristics of thin-film materials, a one-dimensional Mason model is established for the later RF filter design, and the influence of the thickness and resonant area of each film on the resonant frequency of the device is studied. And detailed simulation of the physical parameters of the model. The simulation results show that as the thickness of each layer increases, the acoustic wave transmission path increases, and the loss increases, which causes the resonant frequency decrease gradually; as the resonant area increases, the resonant frequency is not affected, but the impedance value of the device decreases gradually.
{"title":"Simulation and Research of Piezoelectric Film Bulk Acoustic Resonator Based on Mason Model","authors":"Linyu Xu, Xiushan Wu, Yuqi Zeng","doi":"10.1109/ICICM54364.2021.9660240","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660240","url":null,"abstract":"With the rapid development of micromechanical technology and the maturity of integrated circuit technology, which have made it possible to make miniaturization of high-performance frequency control devices. The piezoelectric film bulk acoustic resonator (FBAR) has gradually become one of the research hotspots of RF filters. This paper mainly derives the electrical impedance model of FBAR based on the sound wave transmission characteristics of thin-film materials, a one-dimensional Mason model is established for the later RF filter design, and the influence of the thickness and resonant area of each film on the resonant frequency of the device is studied. And detailed simulation of the physical parameters of the model. The simulation results show that as the thickness of each layer increases, the acoustic wave transmission path increases, and the loss increases, which causes the resonant frequency decrease gradually; as the resonant area increases, the resonant frequency is not affected, but the impedance value of the device decreases gradually.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"184-188"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79233341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660279
Feng Yang
In this paper a novel current-mode analog multiplier based on translinear principle is presented. The transistors in the translinear loop all operate in the strong inversion region. The circuit consists of a current-mode square root circuit and a current-mode square/divider circuit. The circuit has favorable precision, wide dynamic range and is insensitive to variations in temperature and processing. The simulated results show that the multiplier has a bandwidth of 1 MHz. The total harmonic distortion of the multiplier is less than 1%. It is suitable for a wide range of analog signal processing application. Due to the low power, scalability and modularity, it can be also easily integrated in massive parallel systems.
{"title":"A Novel High Precision Low Power Current-Mode Multiplier","authors":"Feng Yang","doi":"10.1109/ICICM54364.2021.9660279","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660279","url":null,"abstract":"In this paper a novel current-mode analog multiplier based on translinear principle is presented. The transistors in the translinear loop all operate in the strong inversion region. The circuit consists of a current-mode square root circuit and a current-mode square/divider circuit. The circuit has favorable precision, wide dynamic range and is insensitive to variations in temperature and processing. The simulated results show that the multiplier has a bandwidth of 1 MHz. The total harmonic distortion of the multiplier is less than 1%. It is suitable for a wide range of analog signal processing application. Due to the low power, scalability and modularity, it can be also easily integrated in massive parallel systems.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"24 1","pages":"69-72"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77993469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-dimensional(3D) stacked packaging devices use epoxy packaging materials to integrate multiple components or chips in the vertical direction, and adopt various new interconnection technologies to realize the vertical interconnection of components. This article introduces a case of cracking on the surface coating of a 3D stacked package component with a vertical electrical connection by the surface metal coating. Through the analysis of the stacked packaging material and discussion of the process, the failure mechanism is clearly obtained and the cause of the failure was found out. Finally, several quality assurance methods to ensure the epoxy curing quality of epoxy-encapsulated 3D devices are given.
{"title":"Thermodynamic Analysis in Failure Analysis of 3D Stacked Package Devices","authors":"Xu Wang, Zhimin Ding, Chao Duan, Meng Meng, Yudong Liu, Zhibin Wang, Xiangtian Yu","doi":"10.1109/ICICM54364.2021.9660285","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660285","url":null,"abstract":"Three-dimensional(3D) stacked packaging devices use epoxy packaging materials to integrate multiple components or chips in the vertical direction, and adopt various new interconnection technologies to realize the vertical interconnection of components. This article introduces a case of cracking on the surface coating of a 3D stacked package component with a vertical electrical connection by the surface metal coating. Through the analysis of the stacked packaging material and discussion of the process, the failure mechanism is clearly obtained and the cause of the failure was found out. Finally, several quality assurance methods to ensure the epoxy curing quality of epoxy-encapsulated 3D devices are given.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"92 1","pages":"137-141"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83205944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660246
Ziyu Zhang, Leijun Xu
This paper presents a X/Ku-band wideband low noise amplifier (LNA), which consists of a cascode stage and a common-source stage based on 0.18 μm CMOS process working at 9-15 GHz. The parasitic capacitance at the gate-source of the cascode and the parasitic capacitance at the drain of the common-source stage are involved in the input and output matching network. In this way, two independent passive devices are used to form a T-shaped matching structure achieving the broadband performance. Moreover, the number of passive devices is saved and the chip area is also saved. The measured results of the LNA show a low return loss (< -10 dB) in the range of 9-15 GHz and a greater gain (> 10 dB). In addition, the noise factor is 4.43 dB at the center frequency. It generates 21 mA bias current at a 1.8 V supply and the area of the layout is 607μm×460μm.
{"title":"A X/Ku-Band Broadband Low Noise Amplifier in 0.18 μm CMOS","authors":"Ziyu Zhang, Leijun Xu","doi":"10.1109/ICICM54364.2021.9660246","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660246","url":null,"abstract":"This paper presents a X/Ku-band wideband low noise amplifier (LNA), which consists of a cascode stage and a common-source stage based on 0.18 μm CMOS process working at 9-15 GHz. The parasitic capacitance at the gate-source of the cascode and the parasitic capacitance at the drain of the common-source stage are involved in the input and output matching network. In this way, two independent passive devices are used to form a T-shaped matching structure achieving the broadband performance. Moreover, the number of passive devices is saved and the chip area is also saved. The measured results of the LNA show a low return loss (< -10 dB) in the range of 9-15 GHz and a greater gain (> 10 dB). In addition, the noise factor is 4.43 dB at the center frequency. It generates 21 mA bias current at a 1.8 V supply and the area of the layout is 607μm×460μm.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"25 1","pages":"193-196"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89985281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660327
Guoxiao Cheng, Y. Sun, Wen Wu
This paper presents a 1.8 ~ 3.1 GHz high-gain three-stage low-noise amplifier (LNA) in 0.18- $mu m$ SiGe BiCMOS technology. Firstly, a 4th-order $pi$-type input matching network is adopted to achieve both wideband noise and power matching. Secondly, current-reused topology is used in the first two stages for high gain and low power consumption, and the resonance points of each stage are staggered to expand the frequency bandwidth. Thirdly, to improve linearity performance, an optimized multiple gated transistor method (MGTR) is employed in the third stage, which focuses on alleviating the degradation of the transconductance. The post-layout simulated results show that the proposed LNA achieves $26.8 sim 29.8$ dB power gain and 1.5 $sim$ 1.7 dB noise Figure (NF) within the 3-dB bandwidth. It also has 1.1 ~ 5.8 GHz S11 bandwidth and $16.2 dBm OIP_{3}$ (third-order output intercept point).
{"title":"A 1.8~3.1 GHz High-Gain LNA with 1.5~1.7 dB NF in 0.18-μm SiGe BiCMOS Technology","authors":"Guoxiao Cheng, Y. Sun, Wen Wu","doi":"10.1109/ICICM54364.2021.9660327","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660327","url":null,"abstract":"This paper presents a 1.8 ~ 3.1 GHz high-gain three-stage low-noise amplifier (LNA) in 0.18- $mu m$ SiGe BiCMOS technology. Firstly, a 4th-order $pi$-type input matching network is adopted to achieve both wideband noise and power matching. Secondly, current-reused topology is used in the first two stages for high gain and low power consumption, and the resonance points of each stage are staggered to expand the frequency bandwidth. Thirdly, to improve linearity performance, an optimized multiple gated transistor method (MGTR) is employed in the third stage, which focuses on alleviating the degradation of the transconductance. The post-layout simulated results show that the proposed LNA achieves $26.8 sim 29.8$ dB power gain and 1.5 $sim$ 1.7 dB noise Figure (NF) within the 3-dB bandwidth. It also has 1.1 ~ 5.8 GHz S11 bandwidth and $16.2 dBm OIP_{3}$ (third-order output intercept point).","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"214-217"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78981156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660304
W. Lai
This article introduces integrated RF front-end CMOS receiver for millimeter-wave and biosensing applications. The proposed integrated RF front-end receiver consists of singlein differential-out (SIDO) low-noise amplifier (LNA), high linearity double-gate mixer, 3th-order loop bandpass filter, phaselocked loop (PLL) with a LC-tank voltage-controlled oscillates (VCO) and array antenna. The proposed integrated RF frontend CMOS receiver has been implemented in tsmc 0.18um CMOS technique.
{"title":"RF Front-End CMOS Receiver with Antenna for Millimeter-Wave Applications","authors":"W. Lai","doi":"10.1109/ICICM54364.2021.9660304","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660304","url":null,"abstract":"This article introduces integrated RF front-end CMOS receiver for millimeter-wave and biosensing applications. The proposed integrated RF front-end receiver consists of singlein differential-out (SIDO) low-noise amplifier (LNA), high linearity double-gate mixer, 3th-order loop bandpass filter, phaselocked loop (PLL) with a LC-tank voltage-controlled oscillates (VCO) and array antenna. The proposed integrated RF frontend CMOS receiver has been implemented in tsmc 0.18um CMOS technique.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2020 1","pages":"332-336"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73483879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, based on TSMC 22nm CMOS process, a Charge Pump with a working frequency of 50MHz is designed. In order to further expand the output voltage range with current matching of CP when charging and discharging, a CP structure based on low voltage differential current mirror technology was proposed. Rail-to-rail operational amplifier is used to clamp the voltage and improve the matching accuracy of charge current and discharge current of CP.
{"title":"Design of Charge Pump with Low Voltage Differential Current Mirror in 22nm CMOS Technology","authors":"Qingbo Cai, Zhiqun Li, Zhennan Li, Yan Yao, Xiaowei Wang, Bofan Chen","doi":"10.1109/ICICM54364.2021.9660364","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660364","url":null,"abstract":"In this paper, based on TSMC 22nm CMOS process, a Charge Pump with a working frequency of 50MHz is designed. In order to further expand the output voltage range with current matching of CP when charging and discharging, a CP structure based on low voltage differential current mirror technology was proposed. Rail-to-rail operational amplifier is used to clamp the voltage and improve the matching accuracy of charge current and discharge current of CP.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"5 1","pages":"218-221"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76418580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A dynamic bias transient enhanced LDO (Low Dropout regulator) circuit for GaN gate driver is presented in this paper. With high-speed comparator, the bias current of LDO error amplifier can be switched dynamically when large load occurs. The reference voltage of high-speed comparator determines the response time of dynamic bias control circuit. The LDO has been designed in 0.18 μm BCD (Bipolar-CMOS-DMOS) process, simulation results show that the proposed LDO undershoot voltage is 16.6% of output voltage and the recovery time is less than 0.5us when load current is changed from 0mA to 20mA by frequency is 1MHZ.
{"title":"Design of Transient Enhanced LDO Circuit for GaN HEMT Gate Driver","authors":"Li Wang, De-Zhong Zhou, Ningye He, Yuan Xu, Xiaoxiong He, Zhenhai Chen","doi":"10.1109/ICICM54364.2021.9660317","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660317","url":null,"abstract":"A dynamic bias transient enhanced LDO (Low Dropout regulator) circuit for GaN gate driver is presented in this paper. With high-speed comparator, the bias current of LDO error amplifier can be switched dynamically when large load occurs. The reference voltage of high-speed comparator determines the response time of dynamic bias control circuit. The LDO has been designed in 0.18 μm BCD (Bipolar-CMOS-DMOS) process, simulation results show that the proposed LDO undershoot voltage is 16.6% of output voltage and the recovery time is less than 0.5us when load current is changed from 0mA to 20mA by frequency is 1MHZ.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"40-44"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77580408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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