Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660348
Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding
The real-time clock (RTC) integrated circuit is a special-purpose accurate clock generating circuit that is used in many microcontroller units (MCUs). In this paper, we design an ultra-low power and high-precision RTC subsystem used in general purpose MCUs. A temperature compensation scheme is designed to improve the accuracy of the RTC. The RTC uses a 1Hz clock for generating the accurate time and a 32768-Hz clock for the temperature compensation, which can reduce power consumption while maintaining high accuracy. To get the temperature from the analog-to-digital (ADC), we design an ADC controller. A power management unit (PMU) is designed to control the MCU to enter or exit the ultra-low power mode. We also build a subsystem-level verification environment for the RTC using the universal verification methodology (UVM) platform. The results show that the functions of the RTC under various conditions are correct and coverage reaches 98% in the regression test, the frequency error within the industrial temperature range is ± 1 ppm after calibration, and the accuracy meets the requirement of most MCUs.
{"title":"Design and UVM Verification of an RTC Subsystem with Temperature Compensation","authors":"Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding","doi":"10.1109/ICICM54364.2021.9660348","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660348","url":null,"abstract":"The real-time clock (RTC) integrated circuit is a special-purpose accurate clock generating circuit that is used in many microcontroller units (MCUs). In this paper, we design an ultra-low power and high-precision RTC subsystem used in general purpose MCUs. A temperature compensation scheme is designed to improve the accuracy of the RTC. The RTC uses a 1Hz clock for generating the accurate time and a 32768-Hz clock for the temperature compensation, which can reduce power consumption while maintaining high accuracy. To get the temperature from the analog-to-digital (ADC), we design an ADC controller. A power management unit (PMU) is designed to control the MCU to enter or exit the ultra-low power mode. We also build a subsystem-level verification environment for the RTC using the universal verification methodology (UVM) platform. The results show that the functions of the RTC under various conditions are correct and coverage reaches 98% in the regression test, the frequency error within the industrial temperature range is ± 1 ppm after calibration, and the accuracy meets the requirement of most MCUs.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"384-389"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90512566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Object detection is a popular direction in computer vision and digital image processing and convolutional neural network have been widely used in this field. In the forward reasoning stage, many practical applications based on embedded platforms have stringent requirements for low latency and low power consumption. FPGA are undoubtedly the optimal solution to deal with such problems. Yolo [1] is one of the high-quality frameworks for object detection. Among them, Yolov3-tiny is a lightweight network that balances accuracy and network complexity. It is also the most popular object detection network in the industry. This article introduces the complete process of mapping the network structure to the FPGA based on the Yolov3tiny algorithm and optimizes the accelerator architecture for Zedboard to make it under limited resources to achieve the best performance. The experimental results show that the detection speed of 325.036ms/img and the performance of 24.32GOPS is obtained on Zedboard and the mAP of COCO is 32.6%. Compared with Xeon E5-2673 v4 CPU, the energy efficiency is 241times and the performance is 8 times; compared with single-core ARM-A9 CPU, its energy efficiency is 180.75 times and its performance is 402.12 times.
{"title":"Yolov3-tiny Object Detection SoC Based on FPGA Platform","authors":"Hongbo Zhang, Jiaqi Jiang, Yunhao Fu, Yuchun Chang","doi":"10.1109/ICICM54364.2021.9660358","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660358","url":null,"abstract":"Object detection is a popular direction in computer vision and digital image processing and convolutional neural network have been widely used in this field. In the forward reasoning stage, many practical applications based on embedded platforms have stringent requirements for low latency and low power consumption. FPGA are undoubtedly the optimal solution to deal with such problems. Yolo [1] is one of the high-quality frameworks for object detection. Among them, Yolov3-tiny is a lightweight network that balances accuracy and network complexity. It is also the most popular object detection network in the industry. This article introduces the complete process of mapping the network structure to the FPGA based on the Yolov3tiny algorithm and optimizes the accelerator architecture for Zedboard to make it under limited resources to achieve the best performance. The experimental results show that the detection speed of 325.036ms/img and the performance of 24.32GOPS is obtained on Zedboard and the mAP of COCO is 32.6%. Compared with Xeon E5-2673 v4 CPU, the energy efficiency is 241times and the performance is 8 times; compared with single-core ARM-A9 CPU, its energy efficiency is 180.75 times and its performance is 402.12 times.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"4 1","pages":"291-294"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86376740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660242
Yidong Cao, Zhiping Wen
This paper presents a wide input voltage range, low quiescent current low-dropout voltage (LDO) regulator. Featuring the NPN transistors in the BGR circuit operate as the differential input pair of operational trans conductance amplifier (OTA). Current mirror with $beta$ helper structure and class AB output stage of OTA are introduced to improve the accuracy of entire circuit. The proposed LDO is simulated based on 400 nm BCD process. The simulation results shows that the proposed LDO regulator achieved 3.2$mu$A quiescent current with the fixed output voltage 3. 3V. The BGR output voltage has a 186ppm$/^{circ}$C temperature coefficient (TC) when temperature varies from - 55°C to 125°C. The proposed LDO has a line regulation of 11mV when input voltage varies from 4.3V to 24V and a load regulation of 12.8mV with load current range from 5$mu$A to 50mA. The STB(stability) analysis result shows that the circuit provides a gain over 55dB with a gain-bandwidth (GBW) above 5kHz, and a phase margin (PM) over 45 degree with a load capacitor equal to 1$mu$F for different load conditions.
{"title":"A Wide Input Voltage Range, Low Quiescent Current LDO Using Combination Structure of Bandgap and Error Amplifier","authors":"Yidong Cao, Zhiping Wen","doi":"10.1109/ICICM54364.2021.9660242","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660242","url":null,"abstract":"This paper presents a wide input voltage range, low quiescent current low-dropout voltage (LDO) regulator. Featuring the NPN transistors in the BGR circuit operate as the differential input pair of operational trans conductance amplifier (OTA). Current mirror with $beta$ helper structure and class AB output stage of OTA are introduced to improve the accuracy of entire circuit. The proposed LDO is simulated based on 400 nm BCD process. The simulation results shows that the proposed LDO regulator achieved 3.2$mu$A quiescent current with the fixed output voltage 3. 3V. The BGR output voltage has a 186ppm$/^{circ}$C temperature coefficient (TC) when temperature varies from - 55°C to 125°C. The proposed LDO has a line regulation of 11mV when input voltage varies from 4.3V to 24V and a load regulation of 12.8mV with load current range from 5$mu$A to 50mA. The STB(stability) analysis result shows that the circuit provides a gain over 55dB with a gain-bandwidth (GBW) above 5kHz, and a phase margin (PM) over 45 degree with a load capacitor equal to 1$mu$F for different load conditions.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"65 1","pages":"240-245"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79970427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/icicm54364.2021.9660296
{"title":"[ICICM 2021 Front cover]","authors":"","doi":"10.1109/icicm54364.2021.9660296","DOIUrl":"https://doi.org/10.1109/icicm54364.2021.9660296","url":null,"abstract":"","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"03 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72618285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660319
Xue Shi, Nan Chen, Ting-Yu Wei, Jiayu Wu, Peilei Xiao
A controller for DC-DC switching converters based on solely AI algorithm is proposed with a simpler structure than the traditional neural network-PID controllers. Reinforcement learning is used to train the AI controller online using deep deterministic policy gradient (DDPG) algorithm. The AI controller with an actor-critical architecture realizes model-free control with strong self-adaptive ability for different control objects, which can be used for different types of DC-DC switching converters. The performance of a buck DC-DC switching converter with the AI controller is compared with a neural network-PID controller through simulation. The simulation results show that the settling time is improved by at least 65% and overshoot/undershoot is decreased by at least 43%.
{"title":"A Reinforcement Learning-based Online-training AI Controller for DC-DC Switching Converters","authors":"Xue Shi, Nan Chen, Ting-Yu Wei, Jiayu Wu, Peilei Xiao","doi":"10.1109/ICICM54364.2021.9660319","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660319","url":null,"abstract":"A controller for DC-DC switching converters based on solely AI algorithm is proposed with a simpler structure than the traditional neural network-PID controllers. Reinforcement learning is used to train the AI controller online using deep deterministic policy gradient (DDPG) algorithm. The AI controller with an actor-critical architecture realizes model-free control with strong self-adaptive ability for different control objects, which can be used for different types of DC-DC switching converters. The performance of a buck DC-DC switching converter with the AI controller is compared with a neural network-PID controller through simulation. The simulation results show that the settling time is improved by at least 65% and overshoot/undershoot is decreased by at least 43%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"39 1","pages":"435-438"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73681658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660357
You Yuejuan, Liu Dexi, Liu Yawei, Shi Lei
In order to study the influence of Silicon Through Via (TSV) morphology on RF performance, HFSS is used to model and simulate a single truncated cone shaped TSV. By using control single variable method, firstly, we change the radius difference $Delta r$ between the TSV upper and lower ends to change TSV sidewall inclination angle $theta$, and TSV shape; Then, fix $theta$ and change TSV upper end radius, two insulation layers and substrate thickness h and then analyze RF performance changes. The simulation results show that the closer $theta$ is to 90, the better the RF performance is; increasing h and TSV radius or appropriately reducing TSV sidewall insulation layer thickness can improve the electrical performance; moreover, increasing the insulation layer thickness on silicon surface alone or increasing the thickness of the two insulation layers which are integrally formed can also improve the RF performance, the impedance matching should be considered.
{"title":"Influence of Silicon Via Morphology on RF Performance of TSV","authors":"You Yuejuan, Liu Dexi, Liu Yawei, Shi Lei","doi":"10.1109/ICICM54364.2021.9660357","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660357","url":null,"abstract":"In order to study the influence of Silicon Through Via (TSV) morphology on RF performance, HFSS is used to model and simulate a single truncated cone shaped TSV. By using control single variable method, firstly, we change the radius difference $Delta r$ between the TSV upper and lower ends to change TSV sidewall inclination angle $theta$, and TSV shape; Then, fix $theta$ and change TSV upper end radius, two insulation layers and substrate thickness h and then analyze RF performance changes. The simulation results show that the closer $theta$ is to 90, the better the RF performance is; increasing h and TSV radius or appropriately reducing TSV sidewall insulation layer thickness can improve the electrical performance; moreover, increasing the insulation layer thickness on silicon surface alone or increasing the thickness of the two insulation layers which are integrally formed can also improve the RF performance, the impedance matching should be considered.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"60 1","pages":"412-416"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73984364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660305
J. Biba, S. Boche, Nezar-Hekmat Sadek, W. Hansch
The use of physical unclonable functions (PUFs) to generate fingerprints for authentication of chips or larger electronic systems or for generation of internal cryptographic keys for data transfer is investigated. With the implementation of PUFs, each chip or electronic system has its own identity, which should prevent counterfeiting and “night shift” problems. There are various approaches to creating PUFs, and one of them is the so-called coating PUF, which would open the way to cost-effective and flexible protection during and after chip fabrication. In this work, we present two different capacitance measurement methods for fabricated PUF structures consisting of individual metal-oxide-semiconductor (MOS) capacitors. The goal is to obtain an easy and highly accurate measurement setup. Our fabricated PUF chips show an intended variation in capacitance and therefore generate characteristic fingerprints. We show that the parasitic capacitances and measurement variation are much smaller than the intended fluctuation of our PUF capacitances. This enables us to generate reliable and less error-prone fingerprints. Our presented measurement methods in combination with the technological PUF structures have shown to be accurate and reliable for flexible commercial application.
{"title":"Measurement Setup for Physical Unclonable Functions","authors":"J. Biba, S. Boche, Nezar-Hekmat Sadek, W. Hansch","doi":"10.1109/ICICM54364.2021.9660305","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660305","url":null,"abstract":"The use of physical unclonable functions (PUFs) to generate fingerprints for authentication of chips or larger electronic systems or for generation of internal cryptographic keys for data transfer is investigated. With the implementation of PUFs, each chip or electronic system has its own identity, which should prevent counterfeiting and “night shift” problems. There are various approaches to creating PUFs, and one of them is the so-called coating PUF, which would open the way to cost-effective and flexible protection during and after chip fabrication. In this work, we present two different capacitance measurement methods for fabricated PUF structures consisting of individual metal-oxide-semiconductor (MOS) capacitors. The goal is to obtain an easy and highly accurate measurement setup. Our fabricated PUF chips show an intended variation in capacitance and therefore generate characteristic fingerprints. We show that the parasitic capacitances and measurement variation are much smaller than the intended fluctuation of our PUF capacitances. This enables us to generate reliable and less error-prone fingerprints. Our presented measurement methods in combination with the technological PUF structures have shown to be accurate and reliable for flexible commercial application.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"35 1","pages":"155-159"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74499835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660303
Yilu Chen, Lu Tang, Sicong Xia
This article presents a millimeter wave high-resolution digitally controlled oscillator (DCO) in 40nm CMOS technology. The proposed oscillator achieves a frequency tuning accuracy of 2.6MHz by using switched capacitor array and on-chip transformer coupling technology. The tuning range is extended to $80.88 sim 87.53mathrm{GHz}$ by digital control artificial dielectric (DiCAD) technology. The phase noise of 80.88GHz at the frequency offset of lMHz and lOMHz is -93.23dBc/Hz and - 114.05dBc/Hz, and the core circuit layout area is $0.23times 0.13 mathrm{mm}2$. In addition, the peak-to-peak output amplitude of DCO is greater than 1V, which meets the crossover requirements of the post-stage injection-locked frequency divider.
{"title":"A 80.88-87.53GHz Millimeter Wave Wide Tuning Range Digitally Controlled Oscillator in 40nm CMOS","authors":"Yilu Chen, Lu Tang, Sicong Xia","doi":"10.1109/ICICM54364.2021.9660303","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660303","url":null,"abstract":"This article presents a millimeter wave high-resolution digitally controlled oscillator (DCO) in 40nm CMOS technology. The proposed oscillator achieves a frequency tuning accuracy of 2.6MHz by using switched capacitor array and on-chip transformer coupling technology. The tuning range is extended to $80.88 sim 87.53mathrm{GHz}$ by digital control artificial dielectric (DiCAD) technology. The phase noise of 80.88GHz at the frequency offset of lMHz and lOMHz is -93.23dBc/Hz and - 114.05dBc/Hz, and the core circuit layout area is $0.23times 0.13 mathrm{mm}2$. In addition, the peak-to-peak output amplitude of DCO is greater than 1V, which meets the crossover requirements of the post-stage injection-locked frequency divider.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"26 1","pages":"151-154"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90077960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660276
Hongguang Zhang, Zhiqiang Zhang, Yuanyuan Gong, Yanan Zhang, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao
An 8Gb3200Mbps DDR4 SDRAM with fast clock gating and ODT path self-align technique is presented. Fast clock gating is utilized in the DDR4 SDRAM to pursue cut down DLL, read, write and ODT Paths stage, thus data jitters and current consumption can be reduced. ODT path delay self-align method is proposed to the DDR4 SDRAM which is implemented in DRAM process. Measurement results show fast clock gating can reduce 12 stages in DLL, read, write and ODT path and reduce 600uA current, and 5.4% jitters in Read and ODT path. What’s more, the measurement results also show the tADC variation is reduced from 220ps to 30ps with delay self-align technique.
{"title":"A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align","authors":"Hongguang Zhang, Zhiqiang Zhang, Yuanyuan Gong, Yanan Zhang, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao","doi":"10.1109/ICICM54364.2021.9660276","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660276","url":null,"abstract":"An 8Gb3200Mbps DDR4 SDRAM with fast clock gating and ODT path self-align technique is presented. Fast clock gating is utilized in the DDR4 SDRAM to pursue cut down DLL, read, write and ODT Paths stage, thus data jitters and current consumption can be reduced. ODT path delay self-align method is proposed to the DDR4 SDRAM which is implemented in DRAM process. Measurement results show fast clock gating can reduce 12 stages in DLL, read, write and ODT path and reduce 600uA current, and 5.4% jitters in Read and ODT path. What’s more, the measurement results also show the tADC variation is reduced from 220ps to 30ps with delay self-align technique.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"50 1","pages":"171-174"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78277998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660218
Yue Bing, Zhou Luyao, Yang Zhi, Zhao Lin, Lin Haofan, Yang Yong
The oil chromatographic data of the high-voltage reactor in an UHV substation was abnormal, and subsequent live detection measures were taken for this defect, including high-frequency partial discharge test, UHF partial discharge test, ultrasonic partial discharge test, and vibration monitoring. This paper comprehensively analyzed the test data, judges that there was discharge inside, and basically judged the discharge position in the Y-pillar area of the high-voltage reactor, and put forward suggestions and opinions for subsequent disposal measures and operation and maintenance measures.
{"title":"Analysis of Abnormal Defects of High Resistance of 1000 kV UHV Transmission Line","authors":"Yue Bing, Zhou Luyao, Yang Zhi, Zhao Lin, Lin Haofan, Yang Yong","doi":"10.1109/ICICM54364.2021.9660218","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660218","url":null,"abstract":"The oil chromatographic data of the high-voltage reactor in an UHV substation was abnormal, and subsequent live detection measures were taken for this defect, including high-frequency partial discharge test, UHF partial discharge test, ultrasonic partial discharge test, and vibration monitoring. This paper comprehensively analyzed the test data, judges that there was discharge inside, and basically judged the discharge position in the Y-pillar area of the high-voltage reactor, and put forward suggestions and opinions for subsequent disposal measures and operation and maintenance measures.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"36 1","pages":"362-365"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78609071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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