Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660242
Yidong Cao, Zhiping Wen
This paper presents a wide input voltage range, low quiescent current low-dropout voltage (LDO) regulator. Featuring the NPN transistors in the BGR circuit operate as the differential input pair of operational trans conductance amplifier (OTA). Current mirror with $beta$ helper structure and class AB output stage of OTA are introduced to improve the accuracy of entire circuit. The proposed LDO is simulated based on 400 nm BCD process. The simulation results shows that the proposed LDO regulator achieved 3.2$mu$A quiescent current with the fixed output voltage 3. 3V. The BGR output voltage has a 186ppm$/^{circ}$C temperature coefficient (TC) when temperature varies from - 55°C to 125°C. The proposed LDO has a line regulation of 11mV when input voltage varies from 4.3V to 24V and a load regulation of 12.8mV with load current range from 5$mu$A to 50mA. The STB(stability) analysis result shows that the circuit provides a gain over 55dB with a gain-bandwidth (GBW) above 5kHz, and a phase margin (PM) over 45 degree with a load capacitor equal to 1$mu$F for different load conditions.
{"title":"A Wide Input Voltage Range, Low Quiescent Current LDO Using Combination Structure of Bandgap and Error Amplifier","authors":"Yidong Cao, Zhiping Wen","doi":"10.1109/ICICM54364.2021.9660242","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660242","url":null,"abstract":"This paper presents a wide input voltage range, low quiescent current low-dropout voltage (LDO) regulator. Featuring the NPN transistors in the BGR circuit operate as the differential input pair of operational trans conductance amplifier (OTA). Current mirror with $beta$ helper structure and class AB output stage of OTA are introduced to improve the accuracy of entire circuit. The proposed LDO is simulated based on 400 nm BCD process. The simulation results shows that the proposed LDO regulator achieved 3.2$mu$A quiescent current with the fixed output voltage 3. 3V. The BGR output voltage has a 186ppm$/^{circ}$C temperature coefficient (TC) when temperature varies from - 55°C to 125°C. The proposed LDO has a line regulation of 11mV when input voltage varies from 4.3V to 24V and a load regulation of 12.8mV with load current range from 5$mu$A to 50mA. The STB(stability) analysis result shows that the circuit provides a gain over 55dB with a gain-bandwidth (GBW) above 5kHz, and a phase margin (PM) over 45 degree with a load capacitor equal to 1$mu$F for different load conditions.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"65 1","pages":"240-245"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79970427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660318
Qian Qi, Ming Wang, Yanhui Yang, Hongfei Hu, Yu-feng Guo, Xiaopeng Li, Youtao Zhang, Yi Zhang
This paper presents a 12-bit 4GS/s DAC in heterogeneous integration process of SMIC 0.18 $mu$ m CMOS and 0.7 $mu$ m InP HBT technology. The digital circuit is fabricated in CMOS technology to achieve high integration and low power consumption, while the analog circuit is composed by InP HBT technology with great high frequency performance. In this paper, a current-source switch structure is designed to reduce the variance of output impedance between ON and OFF states. Meanwhile, a deglitch circuit based on InP technology is added after the output of DAC to improve high frequency performance. The SFDR of the DAC at Nyquist-rate can reach more than 65dB.
本文提出了一种采用中芯国际0.18 $mu$ m CMOS和0.7 $mu$ m InP HBT技术异构集成工艺的12位4GS/s DAC。数字电路采用CMOS技术制作，实现了高集成度和低功耗，模拟电路采用InP HBT技术制作，具有很高的高频性能。本文设计了一种电流源开关结构，以减小输出阻抗在ON和OFF状态之间的变化。同时，在DAC输出后增加了基于InP技术的去glitch电路，提高了高频性能。在奈奎斯特速率下，DAC的SFDR可以达到65dB以上。
{"title":"A 12-bit 4GS/s DAC based on CMOS/InP heterogeneous integration","authors":"Qian Qi, Ming Wang, Yanhui Yang, Hongfei Hu, Yu-feng Guo, Xiaopeng Li, Youtao Zhang, Yi Zhang","doi":"10.1109/ICICM54364.2021.9660318","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660318","url":null,"abstract":"This paper presents a 12-bit 4GS/s DAC in heterogeneous integration process of SMIC 0.18 $mu$ m CMOS and 0.7 $mu$ m InP HBT technology. The digital circuit is fabricated in CMOS technology to achieve high integration and low power consumption, while the analog circuit is composed by InP HBT technology with great high frequency performance. In this paper, a current-source switch structure is designed to reduce the variance of output impedance between ON and OFF states. Meanwhile, a deglitch circuit based on InP technology is added after the output of DAC to improve high frequency performance. The SFDR of the DAC at Nyquist-rate can reach more than 65dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 817 1","pages":"201-204"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85579504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660221
Shi-Yong Chen
Using the mobile sink for data collection from all sensors is the most highly effective way to prolong the network lifetime of wireless sensor networks(WSNs). Many studies focused on the anchors selection, aiming to reduce the path length of mobile sink and prolong the network lifetime. However, the appropriateness and the number of the selected anchors, which significantly impact the network lifetime of the entire WSNs, still can be improved. This paper proposes a Dynamic Anchor Points Mechanism for data collection, called DAM, aiming to select appropriate anchors under the path length constraint for prolonging the network lifetime. The experimental results show that the proposed DAM outperforms existing data collection mechanisms in term of network lifetime and fairness index.
{"title":"Dynamic Anchors Mechanism for Data Collection Using Mobile Sink in Wireless Sensor Networks","authors":"Shi-Yong Chen","doi":"10.1109/ICICM54364.2021.9660221","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660221","url":null,"abstract":"Using the mobile sink for data collection from all sensors is the most highly effective way to prolong the network lifetime of wireless sensor networks(WSNs). Many studies focused on the anchors selection, aiming to reduce the path length of mobile sink and prolong the network lifetime. However, the appropriateness and the number of the selected anchors, which significantly impact the network lifetime of the entire WSNs, still can be improved. This paper proposes a Dynamic Anchor Points Mechanism for data collection, called DAM, aiming to select appropriate anchors under the path length constraint for prolonging the network lifetime. The experimental results show that the proposed DAM outperforms existing data collection mechanisms in term of network lifetime and fairness index.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"129 1","pages":"337-341"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85759875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Object detection is a popular direction in computer vision and digital image processing and convolutional neural network have been widely used in this field. In the forward reasoning stage, many practical applications based on embedded platforms have stringent requirements for low latency and low power consumption. FPGA are undoubtedly the optimal solution to deal with such problems. Yolo [1] is one of the high-quality frameworks for object detection. Among them, Yolov3-tiny is a lightweight network that balances accuracy and network complexity. It is also the most popular object detection network in the industry. This article introduces the complete process of mapping the network structure to the FPGA based on the Yolov3tiny algorithm and optimizes the accelerator architecture for Zedboard to make it under limited resources to achieve the best performance. The experimental results show that the detection speed of 325.036ms/img and the performance of 24.32GOPS is obtained on Zedboard and the mAP of COCO is 32.6%. Compared with Xeon E5-2673 v4 CPU, the energy efficiency is 241times and the performance is 8 times; compared with single-core ARM-A9 CPU, its energy efficiency is 180.75 times and its performance is 402.12 times.
{"title":"Yolov3-tiny Object Detection SoC Based on FPGA Platform","authors":"Hongbo Zhang, Jiaqi Jiang, Yunhao Fu, Yuchun Chang","doi":"10.1109/ICICM54364.2021.9660358","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660358","url":null,"abstract":"Object detection is a popular direction in computer vision and digital image processing and convolutional neural network have been widely used in this field. In the forward reasoning stage, many practical applications based on embedded platforms have stringent requirements for low latency and low power consumption. FPGA are undoubtedly the optimal solution to deal with such problems. Yolo [1] is one of the high-quality frameworks for object detection. Among them, Yolov3-tiny is a lightweight network that balances accuracy and network complexity. It is also the most popular object detection network in the industry. This article introduces the complete process of mapping the network structure to the FPGA based on the Yolov3tiny algorithm and optimizes the accelerator architecture for Zedboard to make it under limited resources to achieve the best performance. The experimental results show that the detection speed of 325.036ms/img and the performance of 24.32GOPS is obtained on Zedboard and the mAP of COCO is 32.6%. Compared with Xeon E5-2673 v4 CPU, the energy efficiency is 241times and the performance is 8 times; compared with single-core ARM-A9 CPU, its energy efficiency is 180.75 times and its performance is 402.12 times.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"4 1","pages":"291-294"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86376740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660357
You Yuejuan, Liu Dexi, Liu Yawei, Shi Lei
In order to study the influence of Silicon Through Via (TSV) morphology on RF performance, HFSS is used to model and simulate a single truncated cone shaped TSV. By using control single variable method, firstly, we change the radius difference $Delta r$ between the TSV upper and lower ends to change TSV sidewall inclination angle $theta$, and TSV shape; Then, fix $theta$ and change TSV upper end radius, two insulation layers and substrate thickness h and then analyze RF performance changes. The simulation results show that the closer $theta$ is to 90, the better the RF performance is; increasing h and TSV radius or appropriately reducing TSV sidewall insulation layer thickness can improve the electrical performance; moreover, increasing the insulation layer thickness on silicon surface alone or increasing the thickness of the two insulation layers which are integrally formed can also improve the RF performance, the impedance matching should be considered.
{"title":"Influence of Silicon Via Morphology on RF Performance of TSV","authors":"You Yuejuan, Liu Dexi, Liu Yawei, Shi Lei","doi":"10.1109/ICICM54364.2021.9660357","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660357","url":null,"abstract":"In order to study the influence of Silicon Through Via (TSV) morphology on RF performance, HFSS is used to model and simulate a single truncated cone shaped TSV. By using control single variable method, firstly, we change the radius difference $Delta r$ between the TSV upper and lower ends to change TSV sidewall inclination angle $theta$, and TSV shape; Then, fix $theta$ and change TSV upper end radius, two insulation layers and substrate thickness h and then analyze RF performance changes. The simulation results show that the closer $theta$ is to 90, the better the RF performance is; increasing h and TSV radius or appropriately reducing TSV sidewall insulation layer thickness can improve the electrical performance; moreover, increasing the insulation layer thickness on silicon surface alone or increasing the thickness of the two insulation layers which are integrally formed can also improve the RF performance, the impedance matching should be considered.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"60 1","pages":"412-416"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73984364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660292
Zhili Lan, Renhua Liu, Xiaojin Li, Yabin Sun, Yanling Shi
In the era of 3D device, the self-heating effect brings higher temperature to device, and significantly affects the electrical performance of device. Accurate thermal modeling is required to optimize the device structure and circuit design. In this paper, a fifth-order thermal RC network is developed to describe the transient heating process based on the transient thermal simulation of 14-nm FinFET technology. Moreover, a size-dependent dynamic thermal model including fin width, fin height, extension length and materials of the source and drain extension regions, and the thickness of the shallow trench isolation (STI) is developed to estimate the peak temperature at given frequency. The parameters are randomly selected to verify the proposed models, and the average mean relative error of the dimension-dependent model is about 0.42 %, the root mean square error is about 2.33 K.
{"title":"Thermal Transient Measurement and Dimension-dependent Modeling of Self-heated Advanced Devices","authors":"Zhili Lan, Renhua Liu, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1109/ICICM54364.2021.9660292","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660292","url":null,"abstract":"In the era of 3D device, the self-heating effect brings higher temperature to device, and significantly affects the electrical performance of device. Accurate thermal modeling is required to optimize the device structure and circuit design. In this paper, a fifth-order thermal RC network is developed to describe the transient heating process based on the transient thermal simulation of 14-nm FinFET technology. Moreover, a size-dependent dynamic thermal model including fin width, fin height, extension length and materials of the source and drain extension regions, and the thickness of the shallow trench isolation (STI) is developed to estimate the peak temperature at given frequency. The parameters are randomly selected to verify the proposed models, and the average mean relative error of the dimension-dependent model is about 0.42 %, the root mean square error is about 2.33 K.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"305-308"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81100133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660323
B. Yuan, Langqi Xiao, Jing Ying, Bingyuan Wang
Considering the hall angle sensor applications, a novel amplitude calculation circuit for sine and cosine signals is presented. It is consisted by double sampling and holding circuit, squaring circuit and summing circuit. By utilizing same MOSFETs rather than the traditional current mirror structure in the double sampling and holding circuit, the influence of the input offset voltage of the amplifier is eliminated. The proposed squaring and summing circuits eliminate the angular information to obtain the square of the amplitude of the sine and cosine signals. Spectre simulation results show that the squaring circuit works well in a 0.18 um CMOS process with 1.2 % output linearity error. The Monte Carlo simulation shows that the standard deviation of output is only 3.19 mV.
针对霍尔角传感器的应用，提出了一种新的正弦余弦信号振幅计算电路。它由双采样保持电路、平方电路和求和电路组成。通过在双采样保持电路中使用相同的mosfet而不是传统的电流镜结构，消除了放大器输入偏置电压的影响。提出的平方和求和电路消除了角度信息，得到正弦和余弦信号振幅的平方。Spectre仿真结果表明，该平方电路在0.18 um CMOS工艺中工作良好，输出线性度误差为1.2%。蒙特卡罗仿真表明，输出的标准差仅为3.19 mV。
{"title":"Low-Offset CMOS Analog Amplitude Calculation Circuit in Hall Angle Sensor","authors":"B. Yuan, Langqi Xiao, Jing Ying, Bingyuan Wang","doi":"10.1109/ICICM54364.2021.9660323","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660323","url":null,"abstract":"Considering the hall angle sensor applications, a novel amplitude calculation circuit for sine and cosine signals is presented. It is consisted by double sampling and holding circuit, squaring circuit and summing circuit. By utilizing same MOSFETs rather than the traditional current mirror structure in the double sampling and holding circuit, the influence of the input offset voltage of the amplifier is eliminated. The proposed squaring and summing circuits eliminate the angular information to obtain the square of the amplitude of the sine and cosine signals. Spectre simulation results show that the squaring circuit works well in a 0.18 um CMOS process with 1.2 % output linearity error. The Monte Carlo simulation shows that the standard deviation of output is only 3.19 mV.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"27 1","pages":"36-39"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81418550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660348
Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding
The real-time clock (RTC) integrated circuit is a special-purpose accurate clock generating circuit that is used in many microcontroller units (MCUs). In this paper, we design an ultra-low power and high-precision RTC subsystem used in general purpose MCUs. A temperature compensation scheme is designed to improve the accuracy of the RTC. The RTC uses a 1Hz clock for generating the accurate time and a 32768-Hz clock for the temperature compensation, which can reduce power consumption while maintaining high accuracy. To get the temperature from the analog-to-digital (ADC), we design an ADC controller. A power management unit (PMU) is designed to control the MCU to enter or exit the ultra-low power mode. We also build a subsystem-level verification environment for the RTC using the universal verification methodology (UVM) platform. The results show that the functions of the RTC under various conditions are correct and coverage reaches 98% in the regression test, the frequency error within the industrial temperature range is ± 1 ppm after calibration, and the accuracy meets the requirement of most MCUs.
{"title":"Design and UVM Verification of an RTC Subsystem with Temperature Compensation","authors":"Yuxin Liu, N. Tan, Xiaohui Xiao, Junhu Xia, Wanrong Hu, Yan Ding","doi":"10.1109/ICICM54364.2021.9660348","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660348","url":null,"abstract":"The real-time clock (RTC) integrated circuit is a special-purpose accurate clock generating circuit that is used in many microcontroller units (MCUs). In this paper, we design an ultra-low power and high-precision RTC subsystem used in general purpose MCUs. A temperature compensation scheme is designed to improve the accuracy of the RTC. The RTC uses a 1Hz clock for generating the accurate time and a 32768-Hz clock for the temperature compensation, which can reduce power consumption while maintaining high accuracy. To get the temperature from the analog-to-digital (ADC), we design an ADC controller. A power management unit (PMU) is designed to control the MCU to enter or exit the ultra-low power mode. We also build a subsystem-level verification environment for the RTC using the universal verification methodology (UVM) platform. The results show that the functions of the RTC under various conditions are correct and coverage reaches 98% in the regression test, the frequency error within the industrial temperature range is ± 1 ppm after calibration, and the accuracy meets the requirement of most MCUs.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"384-389"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90512566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660332
Jidong Zhou, Jihai Duan
This paper proposes a passive noise shaping successive approximation register (SAR) ADC based on split-capacitor DAC. The designed split-capacitor DAC helps to save chip area and power consumption. The designed noise shaping module helps to eliminate residual sampling. A passive gain of 6 can be achieved, and only a two-input dynamic comparator is used. The simulation results show that the ADC achieves 13.7-bit ENOB with 8 KHz signal bandwidth at the sampling rate of 400 KS/s in 180 nm CMOS technology, and the power consumption is only 7.65 uW.
{"title":"A 8KHz-Bandwidth 13.7bit-ENOB Low-Power Noise-Shaping SAR ADC Using Split-Capacitor DAC","authors":"Jidong Zhou, Jihai Duan","doi":"10.1109/ICICM54364.2021.9660332","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660332","url":null,"abstract":"This paper proposes a passive noise shaping successive approximation register (SAR) ADC based on split-capacitor DAC. The designed split-capacitor DAC helps to save chip area and power consumption. The designed noise shaping module helps to eliminate residual sampling. A passive gain of 6 can be achieved, and only a two-input dynamic comparator is used. The simulation results show that the ADC achieves 13.7-bit ENOB with 8 KHz signal bandwidth at the sampling rate of 400 KS/s in 180 nm CMOS technology, and the power consumption is only 7.65 uW.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"70 1","pages":"319-322"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73711664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660342
Hehe Zhang, Cong Tang, Liang Zou, Yajie Qin
A single-loop 3rd-order 1-bit switched-capacitor modulator in 180-nm CMOS technology is presented. A important feature of this modulator is the full-scale input signal range for high-precision and low-power application that is suitable for DC measurement. In order to achieve the full-scale input signal range, an effective signal-scaling circuit is added in the topology. The chopper stabilization technique is incorporated to calibrate the 1/f noise and DC offset. Meanwhile, the zero optimization technique is utilized in the feed-forward topology to optimize the SNR. To further improve the linearity of the modulator, the bootstrapped switches are used in sampling process. The designed modulator achieves 113.6 dB SNR over 250 Hz signal bandwidth with $pm V_{REF}$ differential input range, while drawing 110$mu$A current from a 2.7V supply and THD is below -100dB. The chip area is 1.76 mm2. This corresponds to FoM of 175.8dB.
{"title":"A 113.6 dB SNR 300μW Switched-Capacitor ΣΔ Modulator with Full-Scale Input Range","authors":"Hehe Zhang, Cong Tang, Liang Zou, Yajie Qin","doi":"10.1109/ICICM54364.2021.9660342","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660342","url":null,"abstract":"A single-loop 3rd-order 1-bit switched-capacitor modulator in 180-nm CMOS technology is presented. A important feature of this modulator is the full-scale input signal range for high-precision and low-power application that is suitable for DC measurement. In order to achieve the full-scale input signal range, an effective signal-scaling circuit is added in the topology. The chopper stabilization technique is incorporated to calibrate the 1/f noise and DC offset. Meanwhile, the zero optimization technique is utilized in the feed-forward topology to optimize the SNR. To further improve the linearity of the modulator, the bootstrapped switches are used in sampling process. The designed modulator achieves 113.6 dB SNR over 250 Hz signal bandwidth with $pm V_{REF}$ differential input range, while drawing 110$mu$A current from a 2.7V supply and THD is below -100dB. The chip area is 1.76 mm2. This corresponds to FoM of 175.8dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"94 1","pages":"101-104"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73851970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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