Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660252
Chao-Ran Zhao, Hao Zhang, Youming Zhang
In order to solve the power supply problem of the Internet of things chip and the low power supply voltage problem of the energy acquisition system, a low power supply voltage phase-locked loop circuit based on dynamic dual loops is proposed in this paper. The circuit uses dynamic dual loops technology and low voltage single side charge pump technology to realize the design of 0. 6V phase-locked loop circuit based on 40nm. The result shows that the RMS jitter of the designed PLL is less than 6. 6ps and the power consumption is 0. 39mw at 0. 6V supply voltage, which can meet the system clock requirements of IOT chip.
{"title":"Design of Low Supply Voltage Phase Locked Loop Based on Dynamic Double Loops Technology","authors":"Chao-Ran Zhao, Hao Zhang, Youming Zhang","doi":"10.1109/ICICM54364.2021.9660252","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660252","url":null,"abstract":"In order to solve the power supply problem of the Internet of things chip and the low power supply voltage problem of the energy acquisition system, a low power supply voltage phase-locked loop circuit based on dynamic dual loops is proposed in this paper. The circuit uses dynamic dual loops technology and low voltage single side charge pump technology to realize the design of 0. 6V phase-locked loop circuit based on 40nm. The result shows that the RMS jitter of the designed PLL is less than 6. 6ps and the power consumption is 0. 39mw at 0. 6V supply voltage, which can meet the system clock requirements of IOT chip.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73943456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660354
Jun’an Zhang, Cong Peng, Yi Xu
A ping-pong auto-zero instrumentation amplifier is presented in this paper. Ping-pong structure is utilized for fast calibration speed. Folded-cascode with class AB output structure are utilized as main amplifier. Folded-cascode with gain boosting structure are utilized as auxiliary amplifier. Both amplifier has a pair of additional input terminals for offset calibration. Simulation results show that the offset voltage is 0.7μV, DC gain is 150dB, unity gain bandwidth of main amplifier is 1.9MHz, common-mode rejection ratio is 130dB, and power consumption is 1.4mW. The design of this amplifier is based on 0.5μm CMOS process with a single supply voltage of 5V.
{"title":"A Ping-Pong Auto-Zero Instrumentation Amplifier Design","authors":"Jun’an Zhang, Cong Peng, Yi Xu","doi":"10.1109/ICICM54364.2021.9660354","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660354","url":null,"abstract":"A ping-pong auto-zero instrumentation amplifier is presented in this paper. Ping-pong structure is utilized for fast calibration speed. Folded-cascode with class AB output structure are utilized as main amplifier. Folded-cascode with gain boosting structure are utilized as auxiliary amplifier. Both amplifier has a pair of additional input terminals for offset calibration. Simulation results show that the offset voltage is 0.7μV, DC gain is 150dB, unity gain bandwidth of main amplifier is 1.9MHz, common-mode rejection ratio is 130dB, and power consumption is 1.4mW. The design of this amplifier is based on 0.5μm CMOS process with a single supply voltage of 5V.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75800162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a 28GHz two-stage differential power amplifier (PA) with two-way power combining is designed in 65-nm Silicon-On-Insulator (SOI) CMOS technology. Each PA cell is designed for high linearity while maintaining high gain. To provide adequate output power, differential cascode structure is selected for power stage, while the driver stage adopts differential common source topology for boosting the power gain. In the differential circuit, neutralization capacitor is added to compensate the parasitic effect of gate-to-drain capacitor of the transistor to improve the gain, while the inductive degeneration technique is adopted to increases the linearity. The impedance matching networks is implemented by transformers, low loss signal distribution and combining are achieved by coupling line balun. The simulation results demonstrate a 23.5dBm PA saturated output power with 45.7% Power-Added Efficiency (PAE) at 28-GHz, while the 1-dB compression output power (P1dB) of 21.3 dBm, and gain of 14.5 dB. The layout size of the power amplifier is 0.46 mm2, and the core area is 0.252 mm2.
{"title":"A 28GHz Power Amplifier with 23.5 dBm Psat in 65nm SOI CMOS","authors":"Dongliang Ni, Liang-Hui Li, Weijia Wu, Jiwei Huang","doi":"10.1109/ICICM54364.2021.9660283","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660283","url":null,"abstract":"In this paper, a 28GHz two-stage differential power amplifier (PA) with two-way power combining is designed in 65-nm Silicon-On-Insulator (SOI) CMOS technology. Each PA cell is designed for high linearity while maintaining high gain. To provide adequate output power, differential cascode structure is selected for power stage, while the driver stage adopts differential common source topology for boosting the power gain. In the differential circuit, neutralization capacitor is added to compensate the parasitic effect of gate-to-drain capacitor of the transistor to improve the gain, while the inductive degeneration technique is adopted to increases the linearity. The impedance matching networks is implemented by transformers, low loss signal distribution and combining are achieved by coupling line balun. The simulation results demonstrate a 23.5dBm PA saturated output power with 45.7% Power-Added Efficiency (PAE) at 28-GHz, while the 1-dB compression output power (P1dB) of 21.3 dBm, and gain of 14.5 dB. The layout size of the power amplifier is 0.46 mm2, and the core area is 0.252 mm2.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78782510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660287
Yue Bing, Zhou Luyao, Yang Zhi, Jin Yongtao, Lin Haofan, Yang Yong
This paper analyzes the cause of the failure of a composite insulator, and conducts a post-mortem inspection and test analysis on the fault insulator and non-fault insulator in the same phase. A continuous carbonized discharge channel has been formed at the low-voltage end, which is characterized by penetrating internal breakdown. The leakage current in the water diffusion test of the faulty insulator exceeded the standard, indicating that the bonding performance of the mandrel sheath has decreased significantly, which in turn caused an air gap at the mandrel-sheath interface, which caused the mandrel to be susceptible to moisture and internal discharge ablation. Degradation and carbonation of epoxy resin, etc.
{"title":"Test and Analysis of Broken String Composite Insulator","authors":"Yue Bing, Zhou Luyao, Yang Zhi, Jin Yongtao, Lin Haofan, Yang Yong","doi":"10.1109/ICICM54364.2021.9660287","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660287","url":null,"abstract":"This paper analyzes the cause of the failure of a composite insulator, and conducts a post-mortem inspection and test analysis on the fault insulator and non-fault insulator in the same phase. A continuous carbonized discharge channel has been formed at the low-voltage end, which is characterized by penetrating internal breakdown. The leakage current in the water diffusion test of the faulty insulator exceeded the standard, indicating that the bonding performance of the mandrel sheath has decreased significantly, which in turn caused an air gap at the mandrel-sheath interface, which caused the mandrel to be susceptible to moisture and internal discharge ablation. Degradation and carbonation of epoxy resin, etc.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80423546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660260
Lang Zhou, Tuo Li, Zhuo Li, Kai Liu, Hongtao Man
A MEMS film transducer used for infrared scene projection was reported. It can absorb the heat of an incident visible image and convert it into an infrared image. The transducer was designed as a thin self-suspended polyimide film with periodic composite microstructure arrays of $1300times 1300$ and high absorption of 95% in visible wavelength range. The large arrays fabricated by MEMS processes were used to limit in-plane thermal diffusion and enhance radiation spatial resolution. Based on the transducer, high equivalent blackbody temperature of 550 K was obtained at a laser power density of 1.4 W/cm2. Linear radiation power density could be controlled. High resolution infrared images were successfully generated in dual infrared bands of 3-5 and 8-12μm. These results proved the MEMS film transducer was a promising candidate in the large-scale dual-band infrared scene projection.
{"title":"Design and Fabrication of A Film Transducer with Composite Microstructures for IR Scene Projection","authors":"Lang Zhou, Tuo Li, Zhuo Li, Kai Liu, Hongtao Man","doi":"10.1109/ICICM54364.2021.9660260","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660260","url":null,"abstract":"A MEMS film transducer used for infrared scene projection was reported. It can absorb the heat of an incident visible image and convert it into an infrared image. The transducer was designed as a thin self-suspended polyimide film with periodic composite microstructure arrays of $1300times 1300$ and high absorption of 95% in visible wavelength range. The large arrays fabricated by MEMS processes were used to limit in-plane thermal diffusion and enhance radiation spatial resolution. Based on the transducer, high equivalent blackbody temperature of 550 K was obtained at a laser power density of 1.4 W/cm2. Linear radiation power density could be controlled. High resolution infrared images were successfully generated in dual infrared bands of 3-5 and 8-12μm. These results proved the MEMS film transducer was a promising candidate in the large-scale dual-band infrared scene projection.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80587354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660286
Haoyu Liu, Jing Jin, Yisu Guo, Jiwei Huang
A precision CMOS temperature-to-digital converter (TDC) for FBAR oscillator is presented in this work. The bank-swap dynamic element matching(DEM) technology is adopted in this circuit, which can reduce the mismatch error $Delta m/m$ between different current mirrors by dynamically interchanging the current mirrors of the bias current circuit and the temperature core circuit using an additional current selector switch. In addition, a self-closing fast starting circuit ensures the front-end circuit to reach its desired operating point. This circuit is designed in TSMC $0.18mu m$ CMOS process. The simulation results show that the static work current of the circuit is $52mu A$ (@27°C) under the supply voltage of 1.8V. After two-point calibration correction, the temperature measurement accuracy achieved $-0.38^{circ}C/+0.35^{circ}C$ in the range of $-45^{circ}Csim 85^{circ}C$. The core area of the circuit is $322 mu mtimes 441 mu m$.
本文介绍了一种用于FBAR振荡器的高精度CMOS温度-数字转换器(TDC)。该电路采用银行互换动态元件匹配(bank-swap dynamic element matching, DEM)技术，通过增加一个电流选择开关，将偏置电流电路的电流镜与温度铁芯电路的电流镜动态互换，减少不同电流镜之间的不匹配误差$Delta m/m$。此外，自闭快速启动电路确保前端电路达到预期的工作点。本电路采用台积电$0.18mu m$ CMOS工艺设计。仿真结果表明，在1.8V电源电压下，电路的静态工作电流为$52mu A$(@27°C)。经两点标定校正，测温精度在$-45^{circ}Csim 85^{circ}C$范围内达到$-0.38^{circ}C/+0.35^{circ}C$。电路的核心区域是$322 mu mtimes 441 mu m$。
{"title":"A CMOS Temperature Sensor Using Bank-Swap Dynamic Element Matching Technology","authors":"Haoyu Liu, Jing Jin, Yisu Guo, Jiwei Huang","doi":"10.1109/ICICM54364.2021.9660286","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660286","url":null,"abstract":"A precision CMOS temperature-to-digital converter (TDC) for FBAR oscillator is presented in this work. The bank-swap dynamic element matching(DEM) technology is adopted in this circuit, which can reduce the mismatch error $Delta m/m$ between different current mirrors by dynamically interchanging the current mirrors of the bias current circuit and the temperature core circuit using an additional current selector switch. In addition, a self-closing fast starting circuit ensures the front-end circuit to reach its desired operating point. This circuit is designed in TSMC $0.18mu m$ CMOS process. The simulation results show that the static work current of the circuit is $52mu A$ (@27°C) under the supply voltage of 1.8V. After two-point calibration correction, the temperature measurement accuracy achieved $-0.38^{circ}C/+0.35^{circ}C$ in the range of $-45^{circ}Csim 85^{circ}C$. The core area of the circuit is $322 mu mtimes 441 mu m$.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85745602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660360
Yi Zhuo, Wengao Lu, Shanzhe Yu, Ye Zhou, Jiaqi Kong, Yacong Zhang, Zhongjian Chen
This paper proposes a readout integrated circuit (ROIC) pixel for short-wavelength infrared (SWIR) focal plane arrays, including an in-pixel capacitive trans-impedance amplifier (CTIA) with correlated double sampling (CDS) circuit. An inverter-based operational amplifier is proposed, which can obtain higher gain under the same power consumption, thereby effectively reducing thermal noise. At the same time, a compact inpixel CDS is proposed, which uses fewer switches to reduce the pixel area. This pixel circuit is designed in 180nm 1P5M CMOS process. The simulation result shows that the output swing of the circuit is 1.2V, and the linearity within the output swing reaches 99.9%. The integrating capacitor is 8fF, and the pixel output noise after CDS is 11.38e-, which is 48% lower than the traditional CTIA circuit.
{"title":"A Low-Noise CTIA-based pixel with CDS for SWIR Focal Plane Arrays","authors":"Yi Zhuo, Wengao Lu, Shanzhe Yu, Ye Zhou, Jiaqi Kong, Yacong Zhang, Zhongjian Chen","doi":"10.1109/ICICM54364.2021.9660360","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660360","url":null,"abstract":"This paper proposes a readout integrated circuit (ROIC) pixel for short-wavelength infrared (SWIR) focal plane arrays, including an in-pixel capacitive trans-impedance amplifier (CTIA) with correlated double sampling (CDS) circuit. An inverter-based operational amplifier is proposed, which can obtain higher gain under the same power consumption, thereby effectively reducing thermal noise. At the same time, a compact inpixel CDS is proposed, which uses fewer switches to reduce the pixel area. This pixel circuit is designed in 180nm 1P5M CMOS process. The simulation result shows that the output swing of the circuit is 1.2V, and the linearity within the output swing reaches 99.9%. The integrating capacitor is 8fF, and the pixel output noise after CDS is 11.38e-, which is 48% lower than the traditional CTIA circuit.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73713292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660326
Shuwang Dai, Xiangjun Lu, Yong Zhang, Lei Liu, Wenxiao Fang
This paper deals with direct power injection (DPI) test research and its fabrication of test circuit board, construction of test system, and failure analysis. Such a sensitivity test aims to assist designers in assessing the IC’s (integrated circuits) susceptibility to radio frequency interferences (RFI) during the design phase of the IC. The IEC 62132-4 standard method of immunity measurement is applied to a microcontroller chip to evaluate the sensitivity of specific pins to direct power injection conducted interference. Through experiments, get the sensitive threshold and interference amplitude of the microcontroller. And through the optical microscope and scanning electron microscope to explore the reasons for the failure of the microcontroller, the main damage mechanism is thermal stress.
{"title":"Electromagnetic Conductive Immunity of a Microcontroller by Direct Power Injection","authors":"Shuwang Dai, Xiangjun Lu, Yong Zhang, Lei Liu, Wenxiao Fang","doi":"10.1109/ICICM54364.2021.9660326","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660326","url":null,"abstract":"This paper deals with direct power injection (DPI) test research and its fabrication of test circuit board, construction of test system, and failure analysis. Such a sensitivity test aims to assist designers in assessing the IC’s (integrated circuits) susceptibility to radio frequency interferences (RFI) during the design phase of the IC. The IEC 62132-4 standard method of immunity measurement is applied to a microcontroller chip to evaluate the sensitivity of specific pins to direct power injection conducted interference. Through experiments, get the sensitive threshold and interference amplitude of the microcontroller. And through the optical microscope and scanning electron microscope to explore the reasons for the failure of the microcontroller, the main damage mechanism is thermal stress.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74415312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660328
Siwei Huang, B. Dou, Jiajin Song, Xiao Li
An integrated power amplifier using 65-nm CMOS bulk technology was presented in this work. The whole PA consists of a one-way drive stage and a two-way main stage. By employing a compactly designed transformer-based output combiner, the CMOS PA occupied a small core-area of $0.47times 0.57mm^{2}$, and delivered 21.6 dBm of measured saturated output power at 10GHz, with a power added efficiency of 23.6%. The proposed PA can operate well in $8sim 15GHz$ wideband.
{"title":"An 8-15 GHz CMOS Power Amplifier with a Compact Transformer-based Output Combiner","authors":"Siwei Huang, B. Dou, Jiajin Song, Xiao Li","doi":"10.1109/ICICM54364.2021.9660328","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660328","url":null,"abstract":"An integrated power amplifier using 65-nm CMOS bulk technology was presented in this work. The whole PA consists of a one-way drive stage and a two-way main stage. By employing a compactly designed transformer-based output combiner, the CMOS PA occupied a small core-area of $0.47times 0.57mm^{2}$, and delivered 21.6 dBm of measured saturated output power at 10GHz, with a power added efficiency of 23.6%. The proposed PA can operate well in $8sim 15GHz$ wideband.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77542061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660351
Huo Hongfei, Liu Yihua, Li Xiaopeng, Zhang Youtao, Guo Yufeng, Gao Hao, Zhang Yi
A 10b 42MS/s power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented in this paper. The ADC structure is optimized for lower power consumption. For this purpose, an accuracy-enhanced DAC switching method and a comparator that can dynamically adjust current to save energy are introduced. The linearity of SAR ADCs can be improved without adding capacitors or calibration logic in this way. In 130nm CMOS process, simulation results show the ADC achieves a SNDR of 60dB for Nyquist input and consumes $510 mu mathrm{W}$ under a 1.2V power supply.
本文介绍了一种10b42ms /s的低功耗连续逼近寄存器(SAR)模数转换器(ADC)。ADC结构经过优化，可降低功耗。为此，介绍了一种提高精度的DAC开关方法和一种可以动态调节电流以节省能量的比较器。这种方法可以在不增加电容或校准逻辑的情况下改善SAR adc的线性度。在130nm CMOS工艺下，仿真结果表明，在1.2V电源下，ADC在Nyquist输入下实现了60dB的SNDR，功耗为510 mu math {W}$。
{"title":"A 10b 42MS/s SAR ADC with Power Efficient Design","authors":"Huo Hongfei, Liu Yihua, Li Xiaopeng, Zhang Youtao, Guo Yufeng, Gao Hao, Zhang Yi","doi":"10.1109/ICICM54364.2021.9660351","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660351","url":null,"abstract":"A 10b 42MS/s power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) is presented in this paper. The ADC structure is optimized for lower power consumption. For this purpose, an accuracy-enhanced DAC switching method and a comparator that can dynamically adjust current to save energy are introduced. The linearity of SAR ADCs can be improved without adding capacitors or calibration logic in this way. In 130nm CMOS process, simulation results show the ADC achieves a SNDR of 60dB for Nyquist input and consumes $510 mu mathrm{W}$ under a 1.2V power supply.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77631570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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