Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660282
Peixuan Li, Yaofang Zhang, Deli Yin, Ping Xie
With the development of flash memory, its storage density is gradually increased. A single flash memory cell can store more bits. But this makes it much less reliability. LDPC (i.e., Low Density Parity Check Code) has powerful error correction ability, which can help flash to solve this problem. However, there is a key problem with LDPC as an error-correcting code. It will make flash storage devices with low reliability suffer from high error correction delay. In this case, flash storage devices have greatly increased read latency, which affects device performance. In this work, we define high latency blocks according to LDPC latency of blocks, and propose a self-adaptive refresh scheme to reduce the read latency of flash storage devices. The basic idea is to refresh high latency blocks whenever it is detected to optimize read performance. In a periodic refresh mode, we test the performance of the refresh scheme in the case of wide workloads with different read and write ratios. The scheme reduces the average response time of flash storage devices by 6%-40% against baseline refresh schemes.
随着闪存的发展，其存储密度逐渐提高。一个闪存单元可以存储更多的比特。但这使得它的可靠性大大降低。LDPC (Low Density Parity Check Code，低密度奇偶校验码)具有强大的纠错能力，可以帮助flash解决这个问题。然而，LDPC作为纠错码存在一个关键问题。它将使低可靠性的闪存存储设备遭受高纠错延迟。在这种情况下，flash存储设备的读延迟会大大增加，从而影响设备的性能。本文根据块的LDPC延迟定义了高延迟块，并提出了一种自适应刷新方案来降低闪存设备的读取延迟。其基本思想是在检测到高延迟块时刷新高延迟块，以优化读取性能。在周期性刷新模式下，我们在具有不同读写比率的大工作负载情况下测试刷新方案的性能。与基准刷新方案相比，该方案可将闪存设备的平均响应时间减少6%-40%。
{"title":"An Efficient Refresh Strategy of Flash Memory via High Delay Blocks in LDPC","authors":"Peixuan Li, Yaofang Zhang, Deli Yin, Ping Xie","doi":"10.1109/ICICM54364.2021.9660282","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660282","url":null,"abstract":"With the development of flash memory, its storage density is gradually increased. A single flash memory cell can store more bits. But this makes it much less reliability. LDPC (i.e., Low Density Parity Check Code) has powerful error correction ability, which can help flash to solve this problem. However, there is a key problem with LDPC as an error-correcting code. It will make flash storage devices with low reliability suffer from high error correction delay. In this case, flash storage devices have greatly increased read latency, which affects device performance. In this work, we define high latency blocks according to LDPC latency of blocks, and propose a self-adaptive refresh scheme to reduce the read latency of flash storage devices. The basic idea is to refresh high latency blocks whenever it is detected to optimize read performance. In a periodic refresh mode, we test the performance of the refresh scheme in the case of wide workloads with different read and write ratios. The scheme reduces the average response time of flash storage devices by 6%-40% against baseline refresh schemes.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"45 1","pages":"299-304"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81698333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660245
Ming Liu, Na Ding, Yan Wang
This paper presents a 5-6.5 GHz transmitter with a 6-bit programmable phase shifter and a 3-stage power amplifier in 180 nm CMOS. The phase shifter consists of a 2-stage poly phase filter (PPF), an active vector modulator (AVM) and two inter-stage matching transformers. The measurement results show a RMS phase error of 1.0° to 1.88° and gain error of 0.13 dB to 0.3 dB over 5-6.5 GHz, covering 360° phase range at 5.625° resolution. Meanwhile, the transmitter achieves a gain of 27 dB, an output 1-dB compression point of 18.4 dBm, a saturated output power of 21.8 dBm and peak PAE of 12%. The core die area is 0.7mm$times 2.5$mm.
{"title":"A C-band CMOS Transmitter with a 6-bit Phase Shifter and Power Amplifier for Phased Array Systems","authors":"Ming Liu, Na Ding, Yan Wang","doi":"10.1109/ICICM54364.2021.9660245","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660245","url":null,"abstract":"This paper presents a 5-6.5 GHz transmitter with a 6-bit programmable phase shifter and a 3-stage power amplifier in 180 nm CMOS. The phase shifter consists of a 2-stage poly phase filter (PPF), an active vector modulator (AVM) and two inter-stage matching transformers. The measurement results show a RMS phase error of 1.0° to 1.88° and gain error of 0.13 dB to 0.3 dB over 5-6.5 GHz, covering 360° phase range at 5.625° resolution. Meanwhile, the transmitter achieves a gain of 27 dB, an output 1-dB compression point of 18.4 dBm, a saturated output power of 21.8 dBm and peak PAE of 12%. The core die area is 0.7mm$times 2.5$mm.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"3 1","pages":"250-253"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81917648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660336
Xingjian Yangdong, Qingsheng Hu, Yan Wang
A half-rate clock and data recovery (CDR) circuit used in a 56 Gb/s PAM4 receiver is presented. The CDR consists of a half-rate Alexander phase detector (PD), a V/I convertor, a loop filter and an LC quadrature voltage-controlled oscillator (LC-QVCO). Because PD dominates the power consumption of CDR, a half-rate architecture is employed to reduce the operation speed of D flip-flop(DFF). The cost is only a little overhead in power and complexity in a quadrature clock design. In addition, to achieve higher gain and good performance, synchronization DFFs are added in PD design. The CDR is implemented in 65 nm CMOS process, and the total area including the pads is about 0.56 mm 2. Post-simulation shows that the peak-to-peak jitter of CDR is only 1.23 ps (0.017 UI). The whole system draws a current of 37.56 mA under a 1.2 V supply, that is, consumes 45 mW.
{"title":"A Half-rate Bang-bang Clock and Data Recovery Circuit for 56 Gb/s PAM4 Receiver in 65 nm CMOS","authors":"Xingjian Yangdong, Qingsheng Hu, Yan Wang","doi":"10.1109/ICICM54364.2021.9660336","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660336","url":null,"abstract":"A half-rate clock and data recovery (CDR) circuit used in a 56 Gb/s PAM4 receiver is presented. The CDR consists of a half-rate Alexander phase detector (PD), a V/I convertor, a loop filter and an LC quadrature voltage-controlled oscillator (LC-QVCO). Because PD dominates the power consumption of CDR, a half-rate architecture is employed to reduce the operation speed of D flip-flop(DFF). The cost is only a little overhead in power and complexity in a quadrature clock design. In addition, to achieve higher gain and good performance, synchronization DFFs are added in PD design. The CDR is implemented in 65 nm CMOS process, and the total area including the pads is about 0.56 mm 2. Post-simulation shows that the peak-to-peak jitter of CDR is only 1.23 ps (0.017 UI). The whole system draws a current of 37.56 mA under a 1.2 V supply, that is, consumes 45 mW.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"424 1","pages":"28-31"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85531659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660355
Qicong Liang, Jiafei Yao, Yufeng Guo, Zhikuang Cai, Mingyuan Gu, M. Sun
This paper presents a Class AB power amplifier operating at the frequency band of 1.91 GHz-2.01 GHz. The lateral double-diffused metal oxide semiconductor (LDMOS) MW6S004N manufactured by Freescale is used to design the power amplifier for the high efficiency, good linearity and low cost features. The design procedure and evaluation of the presented power amplifier are described. The $pi$-network topology and two-stage low-pass filter network are used to design the proposed input and output matching network, which are converted to the optimum source impedance and load impedance to enhance the power transmission performance of the power amplifier. The proposed matching networks enable improvements in both linearity and efficiency. The simulation results show that the output power $P_{1 dB}$ is greater than 37.5 dBm, the power added efficiency is 52.5 % for the optimized power amplifier circuit with 1.96 GHz frequency. With two tone input signals, the power amplifier delivers 35 dBm output power, IMD3 of below than -20 dBc, IMD5 of below than -34 dBc.
{"title":"A L-Band Class AB Power Amplifier Based on the Lateral Double-diffused Metal Oxide Semiconductor Device","authors":"Qicong Liang, Jiafei Yao, Yufeng Guo, Zhikuang Cai, Mingyuan Gu, M. Sun","doi":"10.1109/ICICM54364.2021.9660355","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660355","url":null,"abstract":"This paper presents a Class AB power amplifier operating at the frequency band of 1.91 GHz-2.01 GHz. The lateral double-diffused metal oxide semiconductor (LDMOS) MW6S004N manufactured by Freescale is used to design the power amplifier for the high efficiency, good linearity and low cost features. The design procedure and evaluation of the presented power amplifier are described. The $pi$-network topology and two-stage low-pass filter network are used to design the proposed input and output matching network, which are converted to the optimum source impedance and load impedance to enhance the power transmission performance of the power amplifier. The proposed matching networks enable improvements in both linearity and efficiency. The simulation results show that the output power $P_{1 dB}$ is greater than 37.5 dBm, the power added efficiency is 52.5 % for the optimized power amplifier circuit with 1.96 GHz frequency. With two tone input signals, the power amplifier delivers 35 dBm output power, IMD3 of below than -20 dBc, IMD5 of below than -34 dBc.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"268 1","pages":"232-235"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76778452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660268
YunYan Zhou, Juan Hu, Jie Bao, Shan Lu
The rapid on-off operation of power devices will cause voltage overshoot and oscillation through the parasitic inductance, which will affect the performance and safe operation of the circuit. This paper analyzes the internal package structure of Si-SiC hybrid multi-unit IGBT power integrated module, and the parasitic inductance caused by the module package is discussed. The parasitic inductance of each commutation loop in the three-phase inverter module is very different, which will lead to three-phase imbalance. In this paper, three schemes are used to optimize the parasitic inductance of both the inverter and chopper circuits, including changing the pin position, layout optimization and local double-sides substrate. The results show that, the power commutation loop parasitic inductance in the inverter circuit is reduced by 24.1% on average, and the difference of each phase is reduced from 37.9% to 27.8%. Although the power loop parasitic inductance of the chopper circuit is not optimized, the gate loop inductance of the chopper circuit is reduced by 59.1%, and the common emitter inductance is reduced by 20.9%.
{"title":"Optimization of Parasitic Inductance for Si-SiC Hybrid Power Module Package","authors":"YunYan Zhou, Juan Hu, Jie Bao, Shan Lu","doi":"10.1109/ICICM54364.2021.9660268","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660268","url":null,"abstract":"The rapid on-off operation of power devices will cause voltage overshoot and oscillation through the parasitic inductance, which will affect the performance and safe operation of the circuit. This paper analyzes the internal package structure of Si-SiC hybrid multi-unit IGBT power integrated module, and the parasitic inductance caused by the module package is discussed. The parasitic inductance of each commutation loop in the three-phase inverter module is very different, which will lead to three-phase imbalance. In this paper, three schemes are used to optimize the parasitic inductance of both the inverter and chopper circuits, including changing the pin position, layout optimization and local double-sides substrate. The results show that, the power commutation loop parasitic inductance in the inverter circuit is reduced by 24.1% on average, and the difference of each phase is reduced from 37.9% to 27.8%. Although the power loop parasitic inductance of the chopper circuit is not optimized, the gate loop inductance of the chopper circuit is reduced by 59.1%, and the common emitter inductance is reduced by 20.9%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"57 1","pages":"114-118"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75338695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660250
Xiqin Tang, Yang Li, Wanting Liu, Shushan Qiao, Yumei Zhou, D. Shang
In this paper, a simplified and fast latch controller for asynchronous micropipeline is designed, which can be commonly employed in emerging neuromorphic computers. The natural timing relationship of control signals is concerned to reduce the complexity, and timing assumption is used as an extra dimension to improve the performance. A comprehensive comparative investigation is carried out between the new designed latch controller and existing counterparts. The comparison results show that the design method may lead to 2+times improvements over existing methods on performance, power and robustness.
{"title":"Relative Timing Latch Controller with Significant Improvement on Power, Performance, and Robustness","authors":"Xiqin Tang, Yang Li, Wanting Liu, Shushan Qiao, Yumei Zhou, D. Shang","doi":"10.1109/ICICM54364.2021.9660250","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660250","url":null,"abstract":"In this paper, a simplified and fast latch controller for asynchronous micropipeline is designed, which can be commonly employed in emerging neuromorphic computers. The natural timing relationship of control signals is concerned to reduce the complexity, and timing assumption is used as an extra dimension to improve the performance. A comprehensive comparative investigation is carried out between the new designed latch controller and existing counterparts. The comparison results show that the design method may lead to 2+times improvements over existing methods on performance, power and robustness.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"95-100"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80111275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660269
Lei Liu, Wenxiao Fang, Xiangjun Lu, Shuwang Dai
Electrical Fast Transient Pulse (EFT) is a kind of transient pulse interference caused by lightning, grounding fault or the switching of inductive load in circuit. Researchers from Cisco, Intel and other companies have proposed a model to simulate the EFT pulse coupling into the IC’s power pin and input/output (I/O) pin through the EFT transient disturbance rejection direction, which is used to study the EFT disturbance rejection capability of Microcontroller unit(MCU). However, there is no failure analysis for the failed pins. This article uses a device to conduct EFT interference experiment on MCU, and analyze the failure of the faulty pin. Experiment result shows that MCU failure occurs when the coupling voltage is about 10V, and the damage is about 30V.According to the analysis of the experimental results, during the EFT test process, the power supply pins start to fail when the coupling voltage is very small and the voltage when burning is also small, which has a great impact on the EFT performance of the entire MCU. Therefore, it is necessary to consider the protection of I/O pins and strictly design the EFT protection structure of MCU.
{"title":"Research of Microprocessor Electrical Fast Transient Pulse Group Testing","authors":"Lei Liu, Wenxiao Fang, Xiangjun Lu, Shuwang Dai","doi":"10.1109/ICICM54364.2021.9660269","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660269","url":null,"abstract":"Electrical Fast Transient Pulse (EFT) is a kind of transient pulse interference caused by lightning, grounding fault or the switching of inductive load in circuit. Researchers from Cisco, Intel and other companies have proposed a model to simulate the EFT pulse coupling into the IC’s power pin and input/output (I/O) pin through the EFT transient disturbance rejection direction, which is used to study the EFT disturbance rejection capability of Microcontroller unit(MCU). However, there is no failure analysis for the failed pins. This article uses a device to conduct EFT interference experiment on MCU, and analyze the failure of the faulty pin. Experiment result shows that MCU failure occurs when the coupling voltage is about 10V, and the damage is about 30V.According to the analysis of the experimental results, during the EFT test process, the power supply pins start to fail when the coupling voltage is very small and the voltage when burning is also small, which has a great impact on the EFT performance of the entire MCU. Therefore, it is necessary to consider the protection of I/O pins and strictly design the EFT protection structure of MCU.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"99 1","pages":"85-89"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81468863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660361
Weifeng Liang, Huimin Liu, Tao Su
In this paper, a hybrid simulation algorithm called FDTD-LUT, which bases on the finite difference time-domain (FDTD) algorithm and Look-up table (LUT) method, is proposed for analyzing the electromagnetic field of digital integrated circuits. Moreover, an electromagnetic field simulator Hybrid Electromagnetic Simulator for Integrated Circuit (HESIC) is developed by using this algorithm, which can be used for field circuit co-simulation of active-passive hybrid structure. The correctness of the algorithm is verified by comparing the simulation result of the H-tree clock distribution network (CDN) structure with the actual measured data of the H-tree CDN structure.
{"title":"A Hybrid FDTD-LUT Algorithm and Simulator for Electromagnetic Analyzing in Digital Integrated Circuits","authors":"Weifeng Liang, Huimin Liu, Tao Su","doi":"10.1109/ICICM54364.2021.9660361","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660361","url":null,"abstract":"In this paper, a hybrid simulation algorithm called FDTD-LUT, which bases on the finite difference time-domain (FDTD) algorithm and Look-up table (LUT) method, is proposed for analyzing the electromagnetic field of digital integrated circuits. Moreover, an electromagnetic field simulator Hybrid Electromagnetic Simulator for Integrated Circuit (HESIC) is developed by using this algorithm, which can be used for field circuit co-simulation of active-passive hybrid structure. The correctness of the algorithm is verified by comparing the simulation result of the H-tree clock distribution network (CDN) structure with the actual measured data of the H-tree CDN structure.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"9 1","pages":"23-27"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84291705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660322
Liu Wei, Guo Shangshang, W. Xiao, Shang Shiguang
In order to minimize the impact of SAR-ADC capacitance weight mismatch on conversion accuracy, a digital calibration algorithm applied to SAR-ADC is implemented based on sub-binary technology and perturbation technology. A Subradix-2 SAR-ADC model was established with Simulink. The LMS adaptive calibration algorithm was used to calibrate the output iteratively, and the algorithm was implemented on FPGA Xilinx Spartan-6 device. The results show that when the input signal frequency is 239.19kHz and the sampling frequency is 1MS/s, the ENOB is increased from 9.57 bit to 11.78bit.
{"title":"Background LMS Calibration Algorithm Realization for SAR-ADC","authors":"Liu Wei, Guo Shangshang, W. Xiao, Shang Shiguang","doi":"10.1109/ICICM54364.2021.9660322","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660322","url":null,"abstract":"In order to minimize the impact of SAR-ADC capacitance weight mismatch on conversion accuracy, a digital calibration algorithm applied to SAR-ADC is implemented based on sub-binary technology and perturbation technology. A Subradix-2 SAR-ADC model was established with Simulink. The LMS adaptive calibration algorithm was used to calibrate the output iteratively, and the algorithm was implemented on FPGA Xilinx Spartan-6 device. The results show that when the input signal frequency is 239.19kHz and the sampling frequency is 1MS/s, the ENOB is increased from 9.57 bit to 11.78bit.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"178 1","pages":"142-146"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80680678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660232
Tiezhen Jiang, Qi An, Jianhua Wang
Filter is an important part of wireless communication system, but parasitic passband is produced because of the periodic characteristics of microwave resonant structure. To solve this problem, periodic grooves are embedded in the outer edge of the coupling resonator of the traditional hairpin filter, and the parasitic passband is suppressed by compensating for the phase velocity between the even-mode and the odd-mode. The filter designed in this paper has a center frequency of 2. 6GHz and a bandwidth of 240 MHz. Four periodic square grooves are embedded in each resonator. Simulation results show that the filter can suppress the parasitic passband by -59dB.
{"title":"Design of hairpin bandpass filter based on periodic grooves","authors":"Tiezhen Jiang, Qi An, Jianhua Wang","doi":"10.1109/ICICM54364.2021.9660232","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660232","url":null,"abstract":"Filter is an important part of wireless communication system, but parasitic passband is produced because of the periodic characteristics of microwave resonant structure. To solve this problem, periodic grooves are embedded in the outer edge of the coupling resonator of the traditional hairpin filter, and the parasitic passband is suppressed by compensating for the phase velocity between the even-mode and the odd-mode. The filter designed in this paper has a center frequency of 2. 6GHz and a bandwidth of 240 MHz. Four periodic square grooves are embedded in each resonator. Simulation results show that the filter can suppress the parasitic passband by -59dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"67 1","pages":"347-350"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76930948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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