Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660282
Peixuan Li, Yaofang Zhang, Deli Yin, Ping Xie
With the development of flash memory, its storage density is gradually increased. A single flash memory cell can store more bits. But this makes it much less reliability. LDPC (i.e., Low Density Parity Check Code) has powerful error correction ability, which can help flash to solve this problem. However, there is a key problem with LDPC as an error-correcting code. It will make flash storage devices with low reliability suffer from high error correction delay. In this case, flash storage devices have greatly increased read latency, which affects device performance. In this work, we define high latency blocks according to LDPC latency of blocks, and propose a self-adaptive refresh scheme to reduce the read latency of flash storage devices. The basic idea is to refresh high latency blocks whenever it is detected to optimize read performance. In a periodic refresh mode, we test the performance of the refresh scheme in the case of wide workloads with different read and write ratios. The scheme reduces the average response time of flash storage devices by 6%-40% against baseline refresh schemes.
随着闪存的发展，其存储密度逐渐提高。一个闪存单元可以存储更多的比特。但这使得它的可靠性大大降低。LDPC (Low Density Parity Check Code，低密度奇偶校验码)具有强大的纠错能力，可以帮助flash解决这个问题。然而，LDPC作为纠错码存在一个关键问题。它将使低可靠性的闪存存储设备遭受高纠错延迟。在这种情况下，flash存储设备的读延迟会大大增加，从而影响设备的性能。本文根据块的LDPC延迟定义了高延迟块，并提出了一种自适应刷新方案来降低闪存设备的读取延迟。其基本思想是在检测到高延迟块时刷新高延迟块，以优化读取性能。在周期性刷新模式下，我们在具有不同读写比率的大工作负载情况下测试刷新方案的性能。与基准刷新方案相比，该方案可将闪存设备的平均响应时间减少6%-40%。
{"title":"An Efficient Refresh Strategy of Flash Memory via High Delay Blocks in LDPC","authors":"Peixuan Li, Yaofang Zhang, Deli Yin, Ping Xie","doi":"10.1109/ICICM54364.2021.9660282","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660282","url":null,"abstract":"With the development of flash memory, its storage density is gradually increased. A single flash memory cell can store more bits. But this makes it much less reliability. LDPC (i.e., Low Density Parity Check Code) has powerful error correction ability, which can help flash to solve this problem. However, there is a key problem with LDPC as an error-correcting code. It will make flash storage devices with low reliability suffer from high error correction delay. In this case, flash storage devices have greatly increased read latency, which affects device performance. In this work, we define high latency blocks according to LDPC latency of blocks, and propose a self-adaptive refresh scheme to reduce the read latency of flash storage devices. The basic idea is to refresh high latency blocks whenever it is detected to optimize read performance. In a periodic refresh mode, we test the performance of the refresh scheme in the case of wide workloads with different read and write ratios. The scheme reduces the average response time of flash storage devices by 6%-40% against baseline refresh schemes.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81698333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660245
Ming Liu, Na Ding, Yan Wang
This paper presents a 5-6.5 GHz transmitter with a 6-bit programmable phase shifter and a 3-stage power amplifier in 180 nm CMOS. The phase shifter consists of a 2-stage poly phase filter (PPF), an active vector modulator (AVM) and two inter-stage matching transformers. The measurement results show a RMS phase error of 1.0° to 1.88° and gain error of 0.13 dB to 0.3 dB over 5-6.5 GHz, covering 360° phase range at 5.625° resolution. Meanwhile, the transmitter achieves a gain of 27 dB, an output 1-dB compression point of 18.4 dBm, a saturated output power of 21.8 dBm and peak PAE of 12%. The core die area is 0.7mm$times 2.5$mm.
{"title":"A C-band CMOS Transmitter with a 6-bit Phase Shifter and Power Amplifier for Phased Array Systems","authors":"Ming Liu, Na Ding, Yan Wang","doi":"10.1109/ICICM54364.2021.9660245","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660245","url":null,"abstract":"This paper presents a 5-6.5 GHz transmitter with a 6-bit programmable phase shifter and a 3-stage power amplifier in 180 nm CMOS. The phase shifter consists of a 2-stage poly phase filter (PPF), an active vector modulator (AVM) and two inter-stage matching transformers. The measurement results show a RMS phase error of 1.0° to 1.88° and gain error of 0.13 dB to 0.3 dB over 5-6.5 GHz, covering 360° phase range at 5.625° resolution. Meanwhile, the transmitter achieves a gain of 27 dB, an output 1-dB compression point of 18.4 dBm, a saturated output power of 21.8 dBm and peak PAE of 12%. The core die area is 0.7mm$times 2.5$mm.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81917648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660336
Xingjian Yangdong, Qingsheng Hu, Yan Wang
A half-rate clock and data recovery (CDR) circuit used in a 56 Gb/s PAM4 receiver is presented. The CDR consists of a half-rate Alexander phase detector (PD), a V/I convertor, a loop filter and an LC quadrature voltage-controlled oscillator (LC-QVCO). Because PD dominates the power consumption of CDR, a half-rate architecture is employed to reduce the operation speed of D flip-flop(DFF). The cost is only a little overhead in power and complexity in a quadrature clock design. In addition, to achieve higher gain and good performance, synchronization DFFs are added in PD design. The CDR is implemented in 65 nm CMOS process, and the total area including the pads is about 0.56 mm 2. Post-simulation shows that the peak-to-peak jitter of CDR is only 1.23 ps (0.017 UI). The whole system draws a current of 37.56 mA under a 1.2 V supply, that is, consumes 45 mW.
{"title":"A Half-rate Bang-bang Clock and Data Recovery Circuit for 56 Gb/s PAM4 Receiver in 65 nm CMOS","authors":"Xingjian Yangdong, Qingsheng Hu, Yan Wang","doi":"10.1109/ICICM54364.2021.9660336","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660336","url":null,"abstract":"A half-rate clock and data recovery (CDR) circuit used in a 56 Gb/s PAM4 receiver is presented. The CDR consists of a half-rate Alexander phase detector (PD), a V/I convertor, a loop filter and an LC quadrature voltage-controlled oscillator (LC-QVCO). Because PD dominates the power consumption of CDR, a half-rate architecture is employed to reduce the operation speed of D flip-flop(DFF). The cost is only a little overhead in power and complexity in a quadrature clock design. In addition, to achieve higher gain and good performance, synchronization DFFs are added in PD design. The CDR is implemented in 65 nm CMOS process, and the total area including the pads is about 0.56 mm 2. Post-simulation shows that the peak-to-peak jitter of CDR is only 1.23 ps (0.017 UI). The whole system draws a current of 37.56 mA under a 1.2 V supply, that is, consumes 45 mW.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85531659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660355
Qicong Liang, Jiafei Yao, Yufeng Guo, Zhikuang Cai, Mingyuan Gu, M. Sun
This paper presents a Class AB power amplifier operating at the frequency band of 1.91 GHz-2.01 GHz. The lateral double-diffused metal oxide semiconductor (LDMOS) MW6S004N manufactured by Freescale is used to design the power amplifier for the high efficiency, good linearity and low cost features. The design procedure and evaluation of the presented power amplifier are described. The $pi$-network topology and two-stage low-pass filter network are used to design the proposed input and output matching network, which are converted to the optimum source impedance and load impedance to enhance the power transmission performance of the power amplifier. The proposed matching networks enable improvements in both linearity and efficiency. The simulation results show that the output power $P_{1 dB}$ is greater than 37.5 dBm, the power added efficiency is 52.5 % for the optimized power amplifier circuit with 1.96 GHz frequency. With two tone input signals, the power amplifier delivers 35 dBm output power, IMD3 of below than -20 dBc, IMD5 of below than -34 dBc.
{"title":"A L-Band Class AB Power Amplifier Based on the Lateral Double-diffused Metal Oxide Semiconductor Device","authors":"Qicong Liang, Jiafei Yao, Yufeng Guo, Zhikuang Cai, Mingyuan Gu, M. Sun","doi":"10.1109/ICICM54364.2021.9660355","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660355","url":null,"abstract":"This paper presents a Class AB power amplifier operating at the frequency band of 1.91 GHz-2.01 GHz. The lateral double-diffused metal oxide semiconductor (LDMOS) MW6S004N manufactured by Freescale is used to design the power amplifier for the high efficiency, good linearity and low cost features. The design procedure and evaluation of the presented power amplifier are described. The $pi$-network topology and two-stage low-pass filter network are used to design the proposed input and output matching network, which are converted to the optimum source impedance and load impedance to enhance the power transmission performance of the power amplifier. The proposed matching networks enable improvements in both linearity and efficiency. The simulation results show that the output power $P_{1 dB}$ is greater than 37.5 dBm, the power added efficiency is 52.5 % for the optimized power amplifier circuit with 1.96 GHz frequency. With two tone input signals, the power amplifier delivers 35 dBm output power, IMD3 of below than -20 dBc, IMD5 of below than -34 dBc.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76778452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660268
YunYan Zhou, Juan Hu, Jie Bao, Shan Lu
The rapid on-off operation of power devices will cause voltage overshoot and oscillation through the parasitic inductance, which will affect the performance and safe operation of the circuit. This paper analyzes the internal package structure of Si-SiC hybrid multi-unit IGBT power integrated module, and the parasitic inductance caused by the module package is discussed. The parasitic inductance of each commutation loop in the three-phase inverter module is very different, which will lead to three-phase imbalance. In this paper, three schemes are used to optimize the parasitic inductance of both the inverter and chopper circuits, including changing the pin position, layout optimization and local double-sides substrate. The results show that, the power commutation loop parasitic inductance in the inverter circuit is reduced by 24.1% on average, and the difference of each phase is reduced from 37.9% to 27.8%. Although the power loop parasitic inductance of the chopper circuit is not optimized, the gate loop inductance of the chopper circuit is reduced by 59.1%, and the common emitter inductance is reduced by 20.9%.
{"title":"Optimization of Parasitic Inductance for Si-SiC Hybrid Power Module Package","authors":"YunYan Zhou, Juan Hu, Jie Bao, Shan Lu","doi":"10.1109/ICICM54364.2021.9660268","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660268","url":null,"abstract":"The rapid on-off operation of power devices will cause voltage overshoot and oscillation through the parasitic inductance, which will affect the performance and safe operation of the circuit. This paper analyzes the internal package structure of Si-SiC hybrid multi-unit IGBT power integrated module, and the parasitic inductance caused by the module package is discussed. The parasitic inductance of each commutation loop in the three-phase inverter module is very different, which will lead to three-phase imbalance. In this paper, three schemes are used to optimize the parasitic inductance of both the inverter and chopper circuits, including changing the pin position, layout optimization and local double-sides substrate. The results show that, the power commutation loop parasitic inductance in the inverter circuit is reduced by 24.1% on average, and the difference of each phase is reduced from 37.9% to 27.8%. Although the power loop parasitic inductance of the chopper circuit is not optimized, the gate loop inductance of the chopper circuit is reduced by 59.1%, and the common emitter inductance is reduced by 20.9%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75338695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660255
S. Jang, W. Lai, M. Juang
This letter studies high-modulus LC injection-locked frequency dividers (ILFDs) designed with the current-reused technique, which uses two sub-circuits sharing the same dc current and device components. The current-reused ILFDs use one divide-by-3 ILFD and they include $div 6, div 9$ and $div 10$ ILFDs. These circuits cannot be obtained by cascading even-modulus ILFDs. Since the supply current to one sub-ILFD is limited by the other sub-ILFD, the design of a sub-circuit is different from the design of the voltage-mode ILFD. The current-reused $div 6$ ILFD was designed in the TSMC 0.18 $mu mathrm{m}$ BiCMOS process. It is based on a $div 2$ LC p-core ILFD stacking on a $div 3$ LC n-core capacitive cross-coupled ILFD. At the drain-source bias VDD of 1.6/1.2 V and at the incident power of 0dBm, the locking range is 3/2GHz (23.62/15.87%), from the incident frequency 11.2/11.6 GHz to 14.2/13.6 GHz. The core power consumption is 17. 47/6.312mW and the die area is $0.988 times 1.0185 mathrm{mm}^{2}$.
本文研究了采用电流重用技术设计的高模量LC注入锁定分频器(ilfd)，该技术使用两个子电路共享相同的直流电流和器件组件。当前重用的ILFD使用一个除以3的ILFD，它们包括$div 6, div 9$和$div 10$ ILFD。这些电路不能通过级联偶模ilfd获得。由于一个子ILFD的供电电流受到另一个子ILFD的限制，因此子电路的设计不同于电压型ILFD的设计。在TSMC 0.18 $mu mathrm{m}$ BiCMOS工艺中设计了电流复用$div 6$ ILFD。它基于$div 2$ LC p核ILFD叠加在$div 3$ LC n核电容交叉耦合ILFD上。在漏源偏置VDD为1.6/1.2 V、入射功率为0dBm时，锁定范围为3/2GHz (23.62/15.87)%), from the incident frequency 11.2/11.6 GHz to 14.2/13.6 GHz. The core power consumption is 17. 47/6.312mW and the die area is $0.988 times 1.0185 mathrm{mm}^{2}$.
{"title":"High-modulus Current-reused Injection-Locked Frequency Dividers (FDs) with an Odd-modulus Sub-FD","authors":"S. Jang, W. Lai, M. Juang","doi":"10.1109/ICICM54364.2021.9660255","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660255","url":null,"abstract":"This letter studies high-modulus LC injection-locked frequency dividers (ILFDs) designed with the current-reused technique, which uses two sub-circuits sharing the same dc current and device components. The current-reused ILFDs use one divide-by-3 ILFD and they include $div 6, div 9$ and $div 10$ ILFDs. These circuits cannot be obtained by cascading even-modulus ILFDs. Since the supply current to one sub-ILFD is limited by the other sub-ILFD, the design of a sub-circuit is different from the design of the voltage-mode ILFD. The current-reused $div 6$ ILFD was designed in the TSMC 0.18 $mu mathrm{m}$ BiCMOS process. It is based on a $div 2$ LC p-core ILFD stacking on a $div 3$ LC n-core capacitive cross-coupled ILFD. At the drain-source bias VDD of 1.6/1.2 V and at the incident power of 0dBm, the locking range is 3/2GHz (23.62/15.87%), from the incident frequency 11.2/11.6 GHz to 14.2/13.6 GHz. The core power consumption is 17. 47/6.312mW and the die area is $0.988 times 1.0185 mathrm{mm}^{2}$.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77083720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660232
Tiezhen Jiang, Qi An, Jianhua Wang
Filter is an important part of wireless communication system, but parasitic passband is produced because of the periodic characteristics of microwave resonant structure. To solve this problem, periodic grooves are embedded in the outer edge of the coupling resonator of the traditional hairpin filter, and the parasitic passband is suppressed by compensating for the phase velocity between the even-mode and the odd-mode. The filter designed in this paper has a center frequency of 2. 6GHz and a bandwidth of 240 MHz. Four periodic square grooves are embedded in each resonator. Simulation results show that the filter can suppress the parasitic passband by -59dB.
{"title":"Design of hairpin bandpass filter based on periodic grooves","authors":"Tiezhen Jiang, Qi An, Jianhua Wang","doi":"10.1109/ICICM54364.2021.9660232","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660232","url":null,"abstract":"Filter is an important part of wireless communication system, but parasitic passband is produced because of the periodic characteristics of microwave resonant structure. To solve this problem, periodic grooves are embedded in the outer edge of the coupling resonator of the traditional hairpin filter, and the parasitic passband is suppressed by compensating for the phase velocity between the even-mode and the odd-mode. The filter designed in this paper has a center frequency of 2. 6GHz and a bandwidth of 240 MHz. Four periodic square grooves are embedded in each resonator. Simulation results show that the filter can suppress the parasitic passband by -59dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76930948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660250
Xiqin Tang, Yang Li, Wanting Liu, Shushan Qiao, Yumei Zhou, D. Shang
In this paper, a simplified and fast latch controller for asynchronous micropipeline is designed, which can be commonly employed in emerging neuromorphic computers. The natural timing relationship of control signals is concerned to reduce the complexity, and timing assumption is used as an extra dimension to improve the performance. A comprehensive comparative investigation is carried out between the new designed latch controller and existing counterparts. The comparison results show that the design method may lead to 2+times improvements over existing methods on performance, power and robustness.
{"title":"Relative Timing Latch Controller with Significant Improvement on Power, Performance, and Robustness","authors":"Xiqin Tang, Yang Li, Wanting Liu, Shushan Qiao, Yumei Zhou, D. Shang","doi":"10.1109/ICICM54364.2021.9660250","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660250","url":null,"abstract":"In this paper, a simplified and fast latch controller for asynchronous micropipeline is designed, which can be commonly employed in emerging neuromorphic computers. The natural timing relationship of control signals is concerned to reduce the complexity, and timing assumption is used as an extra dimension to improve the performance. A comprehensive comparative investigation is carried out between the new designed latch controller and existing counterparts. The comparison results show that the design method may lead to 2+times improvements over existing methods on performance, power and robustness.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80111275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Bang-Bang phase detector (PD) design scheme of duo-binary(DB) four-level pulse amplitude modulation (PAM4) clock data recovery (CDR) with 112 Gb/s is put forward. In order to solve the problem of high signal attenuation and high bit error rate (BER) of high-speed serial transceiver, DB PAM-4 is used instead of PAM-4 technology to reduce signal loss. Aiming at the problem of complex phase detection of DB PAM-4 CDR based on multilevel modulation, a low complexity DB PAM-4 PD based on waveform filtering technique is proposed. The CDR model is constructed in Candence virtuoso with a working rate of 112 Gb/s. When the input jitter is 0. 5UI, the maximum jitter after locking is 1.2ps.
{"title":"Low complexity Bang-Bang PD Design of 112Gb/s Duo-Binary PAM-4 CDR","authors":"Jinwang Zhang, Fangxu Lv, Zhengbin Pang, Jianjun Shi, Zixiang Tang, Geng Zhang","doi":"10.1109/ICICM54364.2021.9660249","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660249","url":null,"abstract":"The Bang-Bang phase detector (PD) design scheme of duo-binary(DB) four-level pulse amplitude modulation (PAM4) clock data recovery (CDR) with 112 Gb/s is put forward. In order to solve the problem of high signal attenuation and high bit error rate (BER) of high-speed serial transceiver, DB PAM-4 is used instead of PAM-4 technology to reduce signal loss. Aiming at the problem of complex phase detection of DB PAM-4 CDR based on multilevel modulation, a low complexity DB PAM-4 PD based on waveform filtering technique is proposed. The CDR model is constructed in Candence virtuoso with a working rate of 112 Gb/s. When the input jitter is 0. 5UI, the maximum jitter after locking is 1.2ps.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86878782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660350
Hao Zhou
In this paper, a K-band GaAs pHEMT voltage-controlled oscillator chip with differential-output is presented. The differential Colpitts Structure is adopted in this circuit design with two core oscillating loops integrated inside. Simulated results show this oscillator design can operates from 22.99GHz to 27.39GHz, with its relatively tuning frequency bandwidth of 17.47%. The single-ended output power of the chip is around 5dBm. A prototype chip is fabricated using PD25 process of Win foundry and is soldered on the test printed circuit board for performance measurement. The measurement results agree well with the simulated results. The prototype chip can operate from 23.24GHz to 28.17GHz, with its tuning voltage varied from -3V to 0V, achieving a relatively tuning bandwidth of 19.18%. The measured output power of the prototype is 4.5dBm with the differential-output single-ended. Phase noise performance is also provided, with the simulated and measured results agreed with each other well. Phase noise at 100KHz offset for the operating frequency band is around -80dBc/Hz.
{"title":"A K-band Diffential-output GaAs pHEMT Voltage Controlled Oscillator","authors":"Hao Zhou","doi":"10.1109/ICICM54364.2021.9660350","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660350","url":null,"abstract":"In this paper, a K-band GaAs pHEMT voltage-controlled oscillator chip with differential-output is presented. The differential Colpitts Structure is adopted in this circuit design with two core oscillating loops integrated inside. Simulated results show this oscillator design can operates from 22.99GHz to 27.39GHz, with its relatively tuning frequency bandwidth of 17.47%. The single-ended output power of the chip is around 5dBm. A prototype chip is fabricated using PD25 process of Win foundry and is soldered on the test printed circuit board for performance measurement. The measurement results agree well with the simulated results. The prototype chip can operate from 23.24GHz to 28.17GHz, with its tuning voltage varied from -3V to 0V, achieving a relatively tuning bandwidth of 19.18%. The measured output power of the prototype is 4.5dBm with the differential-output single-ended. Phase noise performance is also provided, with the simulated and measured results agreed with each other well. Phase noise at 100KHz offset for the operating frequency band is around -80dBc/Hz.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81973124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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