Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660324
Xiaofeng Wang, Yifan Ge, Yang Gao, Hui Zhou, Min Wu, Chaoran Li
Due to the excellent energy efficiency and real-time performance, FPGA has gradually become an important computing platform for CNN inference. However, most FPGA based Deep-learning Processing Units (DPU) are not scalable enough to cope with the rapid changes in both operator type and network structure of convolutional neural networks (CNNs). To solve this problem, we proposed the Dataflow Driven Multi-core Architecture to improve the scalability of DPU. It implements different computational functions in various modules, which are connected by the streaming structures. Firstly, we designed the Basic-DPU based on the architecture, which is very efficient for standard convolution such as VGG, SSD, etc. To verify the architecture’s scalability, we then added a function module into Basic-DPU to obtain the Extended-DPU, which can accelerate both standard convolution and depthwise separable convolution in high computational efficiency. Finally, the Basic-DPU and Extended-DPU are implemented and evaluated on Xilinx xczu9eg. The experimental results show that their FPGA resource consumptions are almost the same. For the standard convolution, the actual performance reaches 470.3GOPS and 471.5GOPS. With the same test algorithm, the computational efficiency is over 90% for both of them, which is almost 1.69 times higher than the equivalent FPGA implementation. For depthwise separable convolution, their actual performance reaches 183.3GOPS and 245.2GOPS. The computational efficiency of Extended-DPU is 1.3 times that of Basic-DPU and 2.1 times that of the peer FPGA implementation.
{"title":"A More Scalable Deep-learning Processing Unit For Depthwise Separable Convolution","authors":"Xiaofeng Wang, Yifan Ge, Yang Gao, Hui Zhou, Min Wu, Chaoran Li","doi":"10.1109/ICICM54364.2021.9660324","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660324","url":null,"abstract":"Due to the excellent energy efficiency and real-time performance, FPGA has gradually become an important computing platform for CNN inference. However, most FPGA based Deep-learning Processing Units (DPU) are not scalable enough to cope with the rapid changes in both operator type and network structure of convolutional neural networks (CNNs). To solve this problem, we proposed the Dataflow Driven Multi-core Architecture to improve the scalability of DPU. It implements different computational functions in various modules, which are connected by the streaming structures. Firstly, we designed the Basic-DPU based on the architecture, which is very efficient for standard convolution such as VGG, SSD, etc. To verify the architecture’s scalability, we then added a function module into Basic-DPU to obtain the Extended-DPU, which can accelerate both standard convolution and depthwise separable convolution in high computational efficiency. Finally, the Basic-DPU and Extended-DPU are implemented and evaluated on Xilinx xczu9eg. The experimental results show that their FPGA resource consumptions are almost the same. For the standard convolution, the actual performance reaches 470.3GOPS and 471.5GOPS. With the same test algorithm, the computational efficiency is over 90% for both of them, which is almost 1.69 times higher than the equivalent FPGA implementation. For depthwise separable convolution, their actual performance reaches 183.3GOPS and 245.2GOPS. The computational efficiency of Extended-DPU is 1.3 times that of Basic-DPU and 2.1 times that of the peer FPGA implementation.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74932491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660238
Yan-Jiao Hu, Guoyong Ning, Meng Zhang, Shuoxing Li, Jidong Yin, Han Wang
To meet the need for highly integrated coupling technology for terahertz system-in-package, the design of a 900 GHz microstrip-waveguide probe based on GaAs is presented in this paper. The probe with fine airtightness is composed of two $25 mu mathrm{m}$ GaAs substrates with metallization vias. The total thickness of the probe is less than $60 mu mathrm{m}$, which makes it suitable to be applied in micro-assembly integration and system-in-package application. Working around 900 GHz, the simulation results respectively show that insert loss of the probe is 0.73 dB and return loss is 20.5 dB.
为了满足太赫兹封装系统对高集成度耦合技术的需求，本文设计了一种基于砷化镓的900 GHz微带波导探头。具有良好密封性的探头由两个$25 mu mathm {m}$ GaAs衬底和金属化过孔组成。探头的总厚度小于$60 mu mathrm{m}$，适合应用于微组装集成和系统级封装应用。仿真结果表明，在900 GHz工作时，探头的插入损耗为0.73 dB，回波损耗为20.5 dB。
{"title":"Design of 900 GHz Microstrip-Waveguide Probe","authors":"Yan-Jiao Hu, Guoyong Ning, Meng Zhang, Shuoxing Li, Jidong Yin, Han Wang","doi":"10.1109/ICICM54364.2021.9660238","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660238","url":null,"abstract":"To meet the need for highly integrated coupling technology for terahertz system-in-package, the design of a 900 GHz microstrip-waveguide probe based on GaAs is presented in this paper. The probe with fine airtightness is composed of two $25 mu mathrm{m}$ GaAs substrates with metallization vias. The total thickness of the probe is less than $60 mu mathrm{m}$, which makes it suitable to be applied in micro-assembly integration and system-in-package application. Working around 900 GHz, the simulation results respectively show that insert loss of the probe is 0.73 dB and return loss is 20.5 dB.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74955643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660297
Haidong Wang, Yufeng Guo, Jun Zhang, Maolin Zhang, Jing Chen
Due to the complexity of the impact ionization process in power devices, the classic 1-D Fulop and Chynoweth approximation is no longer appliable to the 2-D lateral power devices. In this paper, a numerical study is conducted to explore the sensitivity of the impact ionization coefficient on the structure parameters of 2-D lateral power devices in both full- and partial-depletion cases. As a result of the 2-D RESURF effect, the structure parameters are imposing a more complicated influence on the impact ionization coefficient and therefore can not be simply considered as a function of electric field profile. Therefore, based on the 2-D Poisson’s equation and avalanche breakdown criteria, a new impact ionization coefficient approximation model for a 2-D lateral power device is presented. Based on the proposed model and 2-D Poisson’s equation, the avalanche breakdown voltage (BV) can be obtained with high veracity and effectiveness. The modeling results are compared with simulations obtained by commercial TCAD numerical simulations, which are found to be in good agreement and provide guidance for the design and optimization of 2D lateral power devices.
{"title":"A Numerical Study of the Impact Ionization Coefficient Approximation Model of 2-D Lateral Power Devices","authors":"Haidong Wang, Yufeng Guo, Jun Zhang, Maolin Zhang, Jing Chen","doi":"10.1109/ICICM54364.2021.9660297","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660297","url":null,"abstract":"Due to the complexity of the impact ionization process in power devices, the classic 1-D Fulop and Chynoweth approximation is no longer appliable to the 2-D lateral power devices. In this paper, a numerical study is conducted to explore the sensitivity of the impact ionization coefficient on the structure parameters of 2-D lateral power devices in both full- and partial-depletion cases. As a result of the 2-D RESURF effect, the structure parameters are imposing a more complicated influence on the impact ionization coefficient and therefore can not be simply considered as a function of electric field profile. Therefore, based on the 2-D Poisson’s equation and avalanche breakdown criteria, a new impact ionization coefficient approximation model for a 2-D lateral power device is presented. Based on the proposed model and 2-D Poisson’s equation, the avalanche breakdown voltage (BV) can be obtained with high veracity and effectiveness. The modeling results are compared with simulations obtained by commercial TCAD numerical simulations, which are found to be in good agreement and provide guidance for the design and optimization of 2D lateral power devices.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80221724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660271
Shuoxing Li, Xiao Wang, Meng Zhang, Yan-Jiao Hu, Lu Tang, Han Wang
This paper introduces the design and implementation of array heterodyne-receiver chips working at 850GHz. For the designing process of high-integrated array chips, the parasitic effect is one of the major difficulties. To reduce the influence of parasitic effect, the mixer is designed to utilize a parallel diode which simplifies the direct-current bias circuit, LO is designed to adopt a direct nine-fold multiplier chain. As a result, array monolithic chips in symmetrical $2 times2$ form have high integration and low noise figure. The simulation results prove the rationality, correctness, and feasibility of the design, which has reference significance for the engineering research of terahertz domain.
{"title":"Design of 850 GHz 2×2 Array Heterodyne-receiver Chips Based on Schottky-diode GaAs Process","authors":"Shuoxing Li, Xiao Wang, Meng Zhang, Yan-Jiao Hu, Lu Tang, Han Wang","doi":"10.1109/ICICM54364.2021.9660271","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660271","url":null,"abstract":"This paper introduces the design and implementation of array heterodyne-receiver chips working at 850GHz. For the designing process of high-integrated array chips, the parasitic effect is one of the major difficulties. To reduce the influence of parasitic effect, the mixer is designed to utilize a parallel diode which simplifies the direct-current bias circuit, LO is designed to adopt a direct nine-fold multiplier chain. As a result, array monolithic chips in symmetrical $2 times2$ form have high integration and low noise figure. The simulation results prove the rationality, correctness, and feasibility of the design, which has reference significance for the engineering research of terahertz domain.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85219725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660353
Yu Jiwu, Yan Yingdong
In order to improve the automatic production efficiency and realize the detection data sharing, this study designed and developed an automated throttle motor detection system based on the Internet of Things (IoT) technology. The system was established on the basis of the three-layer architecture of IoT technology, and consisted of the front-end detection device, data transmission device, throttle motor detection data (TMDD) server, and remote management subsystem. The sensors in the front-end detection device were used to sample the throttle motor data and display the data locally, and the TMDD server was used to share the data received from different detection lines. The custom communication protocol was used to encode the detection data and parameters to improve the reliability of data transmission. Compared with most existing detection systems, the proposed detection system performs well on the data acquisition, transmission, data storage and management, and completes the throttle motor factory detection and fatigue detection, which effectively simplify the operation of the system and realize the data sharing and online management of different detection points through local net and Internet.
{"title":"Application of IoT Technology in Throttle Motor Detection System","authors":"Yu Jiwu, Yan Yingdong","doi":"10.1109/ICICM54364.2021.9660353","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660353","url":null,"abstract":"In order to improve the automatic production efficiency and realize the detection data sharing, this study designed and developed an automated throttle motor detection system based on the Internet of Things (IoT) technology. The system was established on the basis of the three-layer architecture of IoT technology, and consisted of the front-end detection device, data transmission device, throttle motor detection data (TMDD) server, and remote management subsystem. The sensors in the front-end detection device were used to sample the throttle motor data and display the data locally, and the TMDD server was used to share the data received from different detection lines. The custom communication protocol was used to encode the detection data and parameters to improve the reliability of data transmission. Compared with most existing detection systems, the proposed detection system performs well on the data acquisition, transmission, data storage and management, and completes the throttle motor factory detection and fatigue detection, which effectively simplify the operation of the system and realize the data sharing and online management of different detection points through local net and Internet.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86915019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660272
Chao Xie, Yuan Ma, Zijian Tang, Milin Zhang
This paper proposed design of a low power potentiostat for electrochemical biosensing with high input dynamic range. A current compensation circuit is proposed to extend the detection range. Chopper stabilization potentiostat is used to suppress the low-frequency noise, realizing a high accuracy. The proposed design was fabricated in 0.18-$mu$m CMOS process occupying a silicon area of 0.43 mm2. The experimental results show a dynamic range of 68 dB with a power consumption of 105 $mu$W.
{"title":"Design of a 68 dB Input Dynamic Range Potentiostat for Electrochemical Biosensing","authors":"Chao Xie, Yuan Ma, Zijian Tang, Milin Zhang","doi":"10.1109/ICICM54364.2021.9660272","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660272","url":null,"abstract":"This paper proposed design of a low power potentiostat for electrochemical biosensing with high input dynamic range. A current compensation circuit is proposed to extend the detection range. Chopper stabilization potentiostat is used to suppress the low-frequency noise, realizing a high accuracy. The proposed design was fabricated in 0.18-$mu$m CMOS process occupying a silicon area of 0.43 mm2. The experimental results show a dynamic range of 68 dB with a power consumption of 105 $mu$W.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89278225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660274
Chunfeng Bai, Kai Zhang
Fully integrated LDOs are analyzed in this paper. Focused on SoC applications, a 20-mA 1.2-V full-on-chip NMOS LDO with fast transient response is designed. Compact size and low quiescent current are obtained owning the proposed adaptive biasing circuits. With only 7$-mu$A quiescent current, the response time to 100X positive load current step in 1-ns is only 60-ns.
本文分析了完全集成的贷款抵押贷款。针对SoC应用，设计了具有快速瞬态响应的20 ma 1.2 v全片NMOS LDO。该自适应偏置电路具有体积小、静态电流小等优点。当静态电流仅为7 μ A时，在1-ns内对100X正负载电流阶跃的响应时间仅为60-ns。
{"title":"A Fast Fully-Integrated LDO with Compact-Size and LOW-IQ for SoC Applications","authors":"Chunfeng Bai, Kai Zhang","doi":"10.1109/ICICM54364.2021.9660274","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660274","url":null,"abstract":"Fully integrated LDOs are analyzed in this paper. Focused on SoC applications, a 20-mA 1.2-V full-on-chip NMOS LDO with fast transient response is designed. Compact size and low quiescent current are obtained owning the proposed adaptive biasing circuits. With only 7$-mu$A quiescent current, the response time to 100X positive load current step in 1-ns is only 60-ns.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83496556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 12-bit 350-MS/s pipelined Analog-to-Digital Converter (ADC) in 40-nm CMOS is presented in this paper. The architecture of 5 stages and 1 backend flash sub-ADC is chosen to ensure the completion of 12bit analog-to-digital conversion. The ADC leverages SHA-less constructure and appropriate sampling capacitors to reduce power consumption and setting errors. In order to fulfill gain and bandwidth requirements, a two-stage op-amp with miller compensation is designed and simulated. The direct current gain, poles and zeros of the amplifier are derived afterward. The results reveal that the ADC achieves a 10.07 bits ENOB and 70. S6dB SFDR at 350 MS/s sample rate. The layout occupies 0.1875 mm2 area and consumes 123 mW at 1.1-V supplies.
{"title":"A 12-bit 350-MS/s Pipelined ADC in 40-nm CMOS","authors":"Weiqi Gu, Peng Miao, Fei Li, Huan Wang, Bowen Ding","doi":"10.1109/ICICM54364.2021.9660359","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660359","url":null,"abstract":"A 12-bit 350-MS/s pipelined Analog-to-Digital Converter (ADC) in 40-nm CMOS is presented in this paper. The architecture of 5 stages and 1 backend flash sub-ADC is chosen to ensure the completion of 12bit analog-to-digital conversion. The ADC leverages SHA-less constructure and appropriate sampling capacitors to reduce power consumption and setting errors. In order to fulfill gain and bandwidth requirements, a two-stage op-amp with miller compensation is designed and simulated. The direct current gain, poles and zeros of the amplifier are derived afterward. The results reveal that the ADC achieves a 10.07 bits ENOB and 70. S6dB SFDR at 350 MS/s sample rate. The layout occupies 0.1875 mm2 area and consumes 123 mW at 1.1-V supplies.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84070326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660219
Genyin Ma, F. Meng
This paper presents a 220GHz quadrupler based on the advanced 130nmSiGe HBT process. The circuit adopts differential amplifier structure and active balun to reduce device redundancy of impedance matching network. A 1/4$lambda$@220GHz harmonic reflector is proposed to reduce the influence of transistor parasitic capacitance and improve the output power. Compensation capacitor technology is introduced to improve the amplitude and phase characteristics of differential signals. This design features an output power of -0.572dBm, a bandwidth of 19 GHz, consumes 0.14 W of dc power and occupies 0.203 mm2 of chip area.
{"title":"Design of a 220GHz Frequency Quadrupler in 0.13 µ m SiGe Technology","authors":"Genyin Ma, F. Meng","doi":"10.1109/ICICM54364.2021.9660219","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660219","url":null,"abstract":"This paper presents a 220GHz quadrupler based on the advanced 130nmSiGe HBT process. The circuit adopts differential amplifier structure and active balun to reduce device redundancy of impedance matching network. A 1/4$lambda$@220GHz harmonic reflector is proposed to reduce the influence of transistor parasitic capacitance and improve the output power. Compensation capacitor technology is introduced to improve the amplitude and phase characteristics of differential signals. This design features an output power of -0.572dBm, a bandwidth of 19 GHz, consumes 0.14 W of dc power and occupies 0.203 mm2 of chip area.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73178107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660362
Yujia Huang, Qiao Meng, Fei Li, Jianwei Zhang
In this paper, a parasitic capacitance calibration scheme of split structure SAR ADC based on redundant bridged capacitor is proposed. A digitally controlled compensation capacitor array is used for parasitic capacitor calibration. By the comparison of the MSB-side last-bit capacitor and all the capacitors in LSB-side, the calibration capacitor array is employed to compensate the weight error caused by the parasitic capacitor. Compared with other similar calibration techniques, this calibration scheme is suitable for top-plate sampling architecture. The prototype is implemented in 40nm CMOS technology, the core area is 350um*250um. After calibration, an SNDR of 68.85dB and an SFDR of 83.11dB are achieved with the with the Nyquist rate input at a sampling rate of 160MS/s, consuming the core power of 2.1mW at 1.1V supply voltage.
{"title":"The Parasitic Capacitance Effect Calibration Scheme of The Split Structure SAR ADC","authors":"Yujia Huang, Qiao Meng, Fei Li, Jianwei Zhang","doi":"10.1109/ICICM54364.2021.9660362","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660362","url":null,"abstract":"In this paper, a parasitic capacitance calibration scheme of split structure SAR ADC based on redundant bridged capacitor is proposed. A digitally controlled compensation capacitor array is used for parasitic capacitor calibration. By the comparison of the MSB-side last-bit capacitor and all the capacitors in LSB-side, the calibration capacitor array is employed to compensate the weight error caused by the parasitic capacitor. Compared with other similar calibration techniques, this calibration scheme is suitable for top-plate sampling architecture. The prototype is implemented in 40nm CMOS technology, the core area is 350um*250um. After calibration, an SNDR of 68.85dB and an SFDR of 83.11dB are achieved with the with the Nyquist rate input at a sampling rate of 160MS/s, consuming the core power of 2.1mW at 1.1V supply voltage.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76114261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：