In order to adapt to the application of electronic devices such as wideband receivers, high-precision and high-speed ADCs have become a hot research topic. In this paper, a 13-bit successive approximation analog-to-digital converter (SAR ADC) with a conversion rate of 500-MS/s is introduced. The voltage domain interpolation (Interpolated) technique is used to achieve 4 bits per conversion, and the number of reduced comparators is reduced to half by using the time domain interpolation structure. The SAR ADC redundancy correction technique based on the pipelined ADC redundancy correction principle is investigated and discussed, allowing the ADC to have ± 0.5 LSB misalignment per conversion.
{"title":"A 13-bit Hybrid Interpolated SAR ADC","authors":"Yiqun Wang, Peng Miao, Fei Li, Huan Wang, Bowen Ding, Weiqi Gu","doi":"10.1109/ICICM54364.2021.9660340","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660340","url":null,"abstract":"In order to adapt to the application of electronic devices such as wideband receivers, high-precision and high-speed ADCs have become a hot research topic. In this paper, a 13-bit successive approximation analog-to-digital converter (SAR ADC) with a conversion rate of 500-MS/s is introduced. The voltage domain interpolation (Interpolated) technique is used to achieve 4 bits per conversion, and the number of reduced comparators is reduced to half by using the time domain interpolation structure. The SAR ADC redundancy correction technique based on the pipelined ADC redundancy correction principle is investigated and discussed, allowing the ADC to have ± 0.5 LSB misalignment per conversion.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"23 1","pages":"65-68"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85254847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660223
Ying Li, Hong Ma, Xin Ge, Xiaowan Dai, Yongshan Hu, Yulu Chen, Xiaodong Wang
We have developed a $128 times128$ cryogenic readout circuit suitable for Silicon-based Blocked-impurity-band detector by means of 0.18 m CMOS technology in this paper, which can be used at 6K temperature. Based on the extraction of parameters and the establishment of the cryogenic temperature model of MOSFET, we focus on the design of the pixel circuit and readout mode. In the design, the correlated double sampling technology is also used to reduce the noise generated in the channel. The designed readout circuit can work at both room temperature and 6K, where the working frequency is 1MHz, the maximum power consumption is 127.38mW, and the output swing is about 2V.
本文采用0.18 m CMOS技术，开发了一种适用于硅基阻塞杂质带探测器的$128 times128$低温读出电路，可在6K温度下使用。在参数提取和MOSFET低温模型建立的基础上，重点设计了像素电路和读出模式。在设计中，还采用了相关双采样技术来降低信道中产生的噪声。所设计的读出电路可以在室温和6K下工作，其中工作频率为1MHz，最大功耗为127.38mW，输出摆幅约为2V。
{"title":"Design of a 128×128 Cryogenic Readout Circuit for Silicon-based Blocked-impurity-band Detector","authors":"Ying Li, Hong Ma, Xin Ge, Xiaowan Dai, Yongshan Hu, Yulu Chen, Xiaodong Wang","doi":"10.1109/ICICM54364.2021.9660223","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660223","url":null,"abstract":"We have developed a $128 times128$ cryogenic readout circuit suitable for Silicon-based Blocked-impurity-band detector by means of 0.18 m CMOS technology in this paper, which can be used at 6K temperature. Based on the extraction of parameters and the establishment of the cryogenic temperature model of MOSFET, we focus on the design of the pixel circuit and readout mode. In the design, the correlated double sampling technology is also used to reduce the noise generated in the channel. The designed readout circuit can work at both room temperature and 6K, where the working frequency is 1MHz, the maximum power consumption is 127.38mW, and the output swing is about 2V.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"54 1","pages":"19-22"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86255554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660329
Wanting Liu, Xiqin Tang, Yang Li, Zhijun Wang, Fei Xia, Shushan Qiao, Yumei Zhou, D. Shang
The two’s complement of a number is defined as the one’s complement of that number plus 1, while the addition operation tends to consume more resources and power. This paper proposes a novel two’s complement generator without involving addition, which can solve this problem. The results show the proposed solution can simplify design, improve performance and reduce power compared with traditional adder-based solutions. In addition, the new design is based on regular cells and fully modular, which leads to good scalability and straightforward assembly into large systems. Furthermore, the proposed design supports multi-functions, and it is also suited for use in arithmetic units, including adders, multipliers to speed up two’s complement operations.
{"title":"A Fast Two’s Complement Generator","authors":"Wanting Liu, Xiqin Tang, Yang Li, Zhijun Wang, Fei Xia, Shushan Qiao, Yumei Zhou, D. Shang","doi":"10.1109/ICICM54364.2021.9660329","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660329","url":null,"abstract":"The two’s complement of a number is defined as the one’s complement of that number plus 1, while the addition operation tends to consume more resources and power. This paper proposes a novel two’s complement generator without involving addition, which can solve this problem. The results show the proposed solution can simplify design, improve performance and reduce power compared with traditional adder-based solutions. In addition, the new design is based on regular cells and fully modular, which leads to good scalability and straightforward assembly into large systems. Furthermore, the proposed design supports multi-functions, and it is also suited for use in arithmetic units, including adders, multipliers to speed up two’s complement operations.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 2","pages":"328-331"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91481251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660337
Xiao Yun Chen, Lu Tang, Xuan Shen
In this paper, a two-step Time-to-Digital converter (TDC) with a matching coarse-fine interface circuit for all-digital phase-locked loop (ADPLL) in a 40nm CMOS process is presented. A low-precision quantization architecture is used for the coarse stage of the designed two-step TDC to achieve wide dynamic range, and a high-precision quantization architecture is used for the fine stage to ensure higher resolution. A matching coarse-fine interface structure is proposed to reduce the transmission error. The simulation results show that the TDC can balance the performance of resolution, power consumption and dynamic range. The 32-level delay chain is used for the first-stage TDC with a quantization accuracy of 53. 8ps, and a 15-level delay chain with a quantization accuracy of 6. 2ps adopted in the second stage TDC. Under the condition that the reference frequency is 100MHz and its core chip size is $0.0431 mm^{2}$.
{"title":"A High-Resolution Two-Step Time-to-Digital Conversion in 40 nm CMOS","authors":"Xiao Yun Chen, Lu Tang, Xuan Shen","doi":"10.1109/ICICM54364.2021.9660337","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660337","url":null,"abstract":"In this paper, a two-step Time-to-Digital converter (TDC) with a matching coarse-fine interface circuit for all-digital phase-locked loop (ADPLL) in a 40nm CMOS process is presented. A low-precision quantization architecture is used for the coarse stage of the designed two-step TDC to achieve wide dynamic range, and a high-precision quantization architecture is used for the fine stage to ensure higher resolution. A matching coarse-fine interface structure is proposed to reduce the transmission error. The simulation results show that the TDC can balance the performance of resolution, power consumption and dynamic range. The 32-level delay chain is used for the first-stage TDC with a quantization accuracy of 53. 8ps, and a 15-level delay chain with a quantization accuracy of 6. 2ps adopted in the second stage TDC. Under the condition that the reference frequency is 100MHz and its core chip size is $0.0431 mm^{2}$.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 1","pages":"189-192"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89467656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660258
Rengang Li, Tuo Li, Kai Liu, Hongtao Man, Xiaofeng Zou, Changhong Wang
With the continuous progress of semiconductor technology, integrated circuits (ICs) have been applied to various electronic devices, such as computers, mobile phones, industrial controllers and so on. System on chip (SoC) is a special IC chip with system architecture, generally including computing logic, acceleration logic, and peripheral units. It has the advantages of small size, low power consumption, and high flexibility, and has been widely used. In the SoC chip design process, logical timing is usually very tight, which will lead to great difficulties in the logic synthesis stage. In general, the conventional synthesis method will manually increase the proportion of path groups, low voltage threshold (LVT) cells, ultra-low voltage threshold (ULVT) cells to improve timing performance, but its timing closure is slow, which will prolong the whole SoC chip design cycle. In order to improve the convergence speed of the SoC chip logic synthesis, this paper proposes a progressive automatic logic synthesis (PALS) method, which adopts progressive form to add path groups, insert LVT and ULVT cells, and performs iteration automatically. In this method, the iterative optimization constraints have the advantages of gradual progression and comprehensive coverage, which improves the convergence speed of logic synthesis effectively. In addition, ARM CortexA7 is synthesized using PALS method, and the experimental results show that the timing convergence time of the PALS method proposed in this paper is reduced by 12% compared with the conventional method, proving the superiority of the PALS method.
{"title":"A Progressive Automatic Logic Synthesis Method for Timing-Limited SoC Design","authors":"Rengang Li, Tuo Li, Kai Liu, Hongtao Man, Xiaofeng Zou, Changhong Wang","doi":"10.1109/ICICM54364.2021.9660258","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660258","url":null,"abstract":"With the continuous progress of semiconductor technology, integrated circuits (ICs) have been applied to various electronic devices, such as computers, mobile phones, industrial controllers and so on. System on chip (SoC) is a special IC chip with system architecture, generally including computing logic, acceleration logic, and peripheral units. It has the advantages of small size, low power consumption, and high flexibility, and has been widely used. In the SoC chip design process, logical timing is usually very tight, which will lead to great difficulties in the logic synthesis stage. In general, the conventional synthesis method will manually increase the proportion of path groups, low voltage threshold (LVT) cells, ultra-low voltage threshold (ULVT) cells to improve timing performance, but its timing closure is slow, which will prolong the whole SoC chip design cycle. In order to improve the convergence speed of the SoC chip logic synthesis, this paper proposes a progressive automatic logic synthesis (PALS) method, which adopts progressive form to add path groups, insert LVT and ULVT cells, and performs iteration automatically. In this method, the iterative optimization constraints have the advantages of gradual progression and comprehensive coverage, which improves the convergence speed of logic synthesis effectively. In addition, ARM CortexA7 is synthesized using PALS method, and the experimental results show that the timing convergence time of the PALS method proposed in this paper is reduced by 12% compared with the conventional method, proving the superiority of the PALS method.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"227-231"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90323454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660259
Fen Guo, Tuo Li, Hongtao Man, Kai Liu, Xiaoliang Wang
In this paper, an enhanced heat dissipation structure, combining diamond substrate and diamond spreader, is considered for further improving the heat dissipation efficiency of GaNRF devices. The steady-state simulation is performed to analyze the thermal management ability of heat dissipation structures. The simulation is mainly focused on the comparisons of heat transfer capability and characteristics for double-diamond heat dissipation structure and the others, including GaN on SiC, GaN on diamond and GaN on SiC with diamond spreader. Simulation demonstrates that the junction temperature of device with double-diamond structure is 120°C, significantly lower than that on SiC substrate, since the coordination of diamond substrate and diamond spreader strengthens heat dissipation in both directions. The results also show that the heat dissipation performance of device is improved about 15 % by adding only 10 $mu$m diamond spreader in double-diamond structure compared to that of single diamond substrate. In addition, the heat transfer ability could be further enhanced by optimizing the spreader thickness and the interface thermal resistance.
为了进一步提高GaNRF器件的散热效率，本文考虑了一种结合金刚石衬底和金刚石扩散片的增强散热结构。通过稳态仿真分析了散热结构的热管理能力。模拟主要比较了双金刚石散热结构与GaN on SiC、GaN on diamond和GaN on SiC带金刚石扩散器的散热结构的传热能力和特性。仿真结果表明，双金刚石结构器件的结温为120℃，明显低于SiC衬底的结温，这是由于金刚石衬底与金刚石扩散器的协同作用增强了双向散热。结果还表明，与单金刚石衬底相比，在双金刚石结构中仅添加10 $mu$m金刚石衬底，器件的散热性能提高了约15%。此外，通过优化扩散板厚度和界面热阻，可以进一步提高传热能力。
{"title":"Enhanced Heat Dissipation of GaN RF Devices Based on Double-diamond Structure","authors":"Fen Guo, Tuo Li, Hongtao Man, Kai Liu, Xiaoliang Wang","doi":"10.1109/ICICM54364.2021.9660259","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660259","url":null,"abstract":"In this paper, an enhanced heat dissipation structure, combining diamond substrate and diamond spreader, is considered for further improving the heat dissipation efficiency of GaNRF devices. The steady-state simulation is performed to analyze the thermal management ability of heat dissipation structures. The simulation is mainly focused on the comparisons of heat transfer capability and characteristics for double-diamond heat dissipation structure and the others, including GaN on SiC, GaN on diamond and GaN on SiC with diamond spreader. Simulation demonstrates that the junction temperature of device with double-diamond structure is 120°C, significantly lower than that on SiC substrate, since the coordination of diamond substrate and diamond spreader strengthens heat dissipation in both directions. The results also show that the heat dissipation performance of device is improved about 15 % by adding only 10 $mu$m diamond spreader in double-diamond structure compared to that of single diamond substrate. In addition, the heat transfer ability could be further enhanced by optimizing the spreader thickness and the interface thermal resistance.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"55-60"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88577253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660263
Bo Liu, Zongmin Wang, Tieliang Zhang, Lei Zhang, Song Yang, Long Yang
The JESD204B is a serializer interface between data converters and logic device. Clock and data recovery (CDR) circuit is one of the core circuits of high-speed serial interface. This paper presents a 12. 5Gbps phase interpolator (PI)-based quarter-rate CDR ofJESD204B interface. After detailed loop analysis, this work puts forward a novel first-order CDR loop with adaptive filtering coefficient. The filter coefficient can be adjusted with the frequency offset and phase error which could reduce the jitter of recovery clock and data and make the loop have strong frequency offset tracking ability. This CDR occupies area of 0.4mm2 and consumes a power of 34mW with a supply voltage 1. 2V in TSMC 65nm CMOS technology. The post simulation result shows that the frequency offset tracking range is 300ppm with 12. 5Gbps data rate. The jitter of recovered data and recovery clock are 0. 006UI and 0. 012UI when there is no jitter in the input data.
{"title":"A 12.5Gbps PI-based Quarter-Rate Clock and Data Recovery Circuit with an Adaptive filter of JESD204B Standard","authors":"Bo Liu, Zongmin Wang, Tieliang Zhang, Lei Zhang, Song Yang, Long Yang","doi":"10.1109/ICICM54364.2021.9660263","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660263","url":null,"abstract":"The JESD204B is a serializer interface between data converters and logic device. Clock and data recovery (CDR) circuit is one of the core circuits of high-speed serial interface. This paper presents a 12. 5Gbps phase interpolator (PI)-based quarter-rate CDR ofJESD204B interface. After detailed loop analysis, this work puts forward a novel first-order CDR loop with adaptive filtering coefficient. The filter coefficient can be adjusted with the frequency offset and phase error which could reduce the jitter of recovery clock and data and make the loop have strong frequency offset tracking ability. This CDR occupies area of 0.4mm2 and consumes a power of 34mW with a supply voltage 1. 2V in TSMC 65nm CMOS technology. The post simulation result shows that the frequency offset tracking range is 300ppm with 12. 5Gbps data rate. The jitter of recovered data and recovery clock are 0. 006UI and 0. 012UI when there is no jitter in the input data.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"5-13"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80687674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660316
Yan Wang, Qingsheng Hu, Xinyu Song
This paper presents a 40Gb/s PAM4 transmitter with a 3-tap fractionally-spaced equalizer (FSE) in 65nm CMOS technology. In order to improve the signal quality, a FSE instead of a symbol-space equalizer (SSE) is realized. In addition, the nonlinearity between the high and low bit output current is reduced by employing low-voltage cascode current source. Post simulation result shows that by boosting the high frequency components effectively, PAM4 signals with clear eye-diagram can be obtained at receiver for a channel with 6.45 dB attenuation @10 GHz. The minimum vertical and horizontal opening of the eye diagram is about 154 mVpp and near 0.6UI. The total area of the transmitter is about 705μm × 495μm including I/O pads and the power consumption is about 72mW under 1.2V power supply.
本文介绍了一种采用65nm CMOS技术的40Gb/s PAM4发射机，该发射机具有3分路分数间隔均衡器(FSE)。为了提高信号质量，采用FSE代替符号空间均衡器(SSE)。此外，通过采用低压级联电流源，降低了高低位输出电流之间的非线性。后置仿真结果表明，通过对高频分量的有效增强，可以在接收机处获得具有清晰眼图的PAM4信号，信道衰减为6.45 dB @10 GHz。眼图的最小垂直和水平开口约为154 mVpp，接近0.6UI。包括I/O垫在内，发射机的总面积约为705μm × 495μm，在1.2V电源下，功耗约为72mW。
{"title":"A 40Gb/s PAM4 Transmitter with 3-tap FSE for Serial Link System","authors":"Yan Wang, Qingsheng Hu, Xinyu Song","doi":"10.1109/ICICM54364.2021.9660316","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660316","url":null,"abstract":"This paper presents a 40Gb/s PAM4 transmitter with a 3-tap fractionally-spaced equalizer (FSE) in 65nm CMOS technology. In order to improve the signal quality, a FSE instead of a symbol-space equalizer (SSE) is realized. In addition, the nonlinearity between the high and low bit output current is reduced by employing low-voltage cascode current source. Post simulation result shows that by boosting the high frequency components effectively, PAM4 signals with clear eye-diagram can be obtained at receiver for a channel with 6.45 dB attenuation @10 GHz. The minimum vertical and horizontal opening of the eye diagram is about 154 mVpp and near 0.6UI. The total area of the transmitter is about 705μm × 495μm including I/O pads and the power consumption is about 72mW under 1.2V power supply.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"6 1","pages":"417-420"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90143600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660290
Yuqi Bing, Zhao Lin, Lin Haofan, Yang Yong
Abstract-On-load tap-changer is a switching device that provides a constant voltage for a transformer when the load changes. The basic principle is to realize the switching between taps in the transformer winding without interrupting the load current, thereby changing the number of winding turns, that is, the voltage ratio of the transformer, and finally achieving the purpose of voltage regulation. In this paper, the characteristic parameters are collected by time domain analysis method, which provides the basis for discriminating the later fault warning.
{"title":"Analysis of Time Domain Characteristic of Transformer On-load Tap-changer","authors":"Yuqi Bing, Zhao Lin, Lin Haofan, Yang Yong","doi":"10.1109/ICICM54364.2021.9660290","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660290","url":null,"abstract":"Abstract-On-load tap-changer is a switching device that provides a constant voltage for a transformer when the load changes. The basic principle is to realize the switching between taps in the transformer winding without interrupting the load current, thereby changing the number of winding turns, that is, the voltage ratio of the transformer, and finally achieving the purpose of voltage regulation. In this paper, the characteristic parameters are collected by time domain analysis method, which provides the basis for discriminating the later fault warning.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"56 1","pages":"390-393"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81382671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660315
Ziran Chen, Mengjia Huang, Zhi Huang, Han Wang, Le He, Meng Zhang
A Ku-band low noise amplifier (LNA) is presented in this paper, which is suitable for the Ku-band satellite communication receiving channel. The miniaturized LNA is established based on the micro-system design principle. The two-stage hetero-junction FET cascade structure is adopted. Based on a reasonable selection of matching structure, a low-pass filter (LPF) is added to suppress out-of-band interference. And the EDA software is applied to optimize the matching circuit. According to the results, the LNA achieves a noise Figure (NF) less than 1.55dB and a gain greater than 24dB in the working frequency range of 12GHz to 13GHz, meanwhile the input and output are well matched.
{"title":"Design of Ku-Band Low Noise Amplifier for Satellite Communication Applications","authors":"Ziran Chen, Mengjia Huang, Zhi Huang, Han Wang, Le He, Meng Zhang","doi":"10.1109/ICICM54364.2021.9660315","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660315","url":null,"abstract":"A Ku-band low noise amplifier (LNA) is presented in this paper, which is suitable for the Ku-band satellite communication receiving channel. The miniaturized LNA is established based on the micro-system design principle. The two-stage hetero-junction FET cascade structure is adopted. Based on a reasonable selection of matching structure, a low-pass filter (LPF) is added to suppress out-of-band interference. And the EDA software is applied to optimize the matching circuit. According to the results, the LNA achieves a noise Figure (NF) less than 1.55dB and a gain greater than 24dB in the working frequency range of 12GHz to 13GHz, meanwhile the input and output are well matched.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"89 1","pages":"342-346"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82516381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：