Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660329
Wanting Liu, Xiqin Tang, Yang Li, Zhijun Wang, Fei Xia, Shushan Qiao, Yumei Zhou, D. Shang
The two’s complement of a number is defined as the one’s complement of that number plus 1, while the addition operation tends to consume more resources and power. This paper proposes a novel two’s complement generator without involving addition, which can solve this problem. The results show the proposed solution can simplify design, improve performance and reduce power compared with traditional adder-based solutions. In addition, the new design is based on regular cells and fully modular, which leads to good scalability and straightforward assembly into large systems. Furthermore, the proposed design supports multi-functions, and it is also suited for use in arithmetic units, including adders, multipliers to speed up two’s complement operations.
{"title":"A Fast Two’s Complement Generator","authors":"Wanting Liu, Xiqin Tang, Yang Li, Zhijun Wang, Fei Xia, Shushan Qiao, Yumei Zhou, D. Shang","doi":"10.1109/ICICM54364.2021.9660329","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660329","url":null,"abstract":"The two’s complement of a number is defined as the one’s complement of that number plus 1, while the addition operation tends to consume more resources and power. This paper proposes a novel two’s complement generator without involving addition, which can solve this problem. The results show the proposed solution can simplify design, improve performance and reduce power compared with traditional adder-based solutions. In addition, the new design is based on regular cells and fully modular, which leads to good scalability and straightforward assembly into large systems. Furthermore, the proposed design supports multi-functions, and it is also suited for use in arithmetic units, including adders, multipliers to speed up two’s complement operations.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91481251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660263
Bo Liu, Zongmin Wang, Tieliang Zhang, Lei Zhang, Song Yang, Long Yang
The JESD204B is a serializer interface between data converters and logic device. Clock and data recovery (CDR) circuit is one of the core circuits of high-speed serial interface. This paper presents a 12. 5Gbps phase interpolator (PI)-based quarter-rate CDR ofJESD204B interface. After detailed loop analysis, this work puts forward a novel first-order CDR loop with adaptive filtering coefficient. The filter coefficient can be adjusted with the frequency offset and phase error which could reduce the jitter of recovery clock and data and make the loop have strong frequency offset tracking ability. This CDR occupies area of 0.4mm2 and consumes a power of 34mW with a supply voltage 1. 2V in TSMC 65nm CMOS technology. The post simulation result shows that the frequency offset tracking range is 300ppm with 12. 5Gbps data rate. The jitter of recovered data and recovery clock are 0. 006UI and 0. 012UI when there is no jitter in the input data.
{"title":"A 12.5Gbps PI-based Quarter-Rate Clock and Data Recovery Circuit with an Adaptive filter of JESD204B Standard","authors":"Bo Liu, Zongmin Wang, Tieliang Zhang, Lei Zhang, Song Yang, Long Yang","doi":"10.1109/ICICM54364.2021.9660263","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660263","url":null,"abstract":"The JESD204B is a serializer interface between data converters and logic device. Clock and data recovery (CDR) circuit is one of the core circuits of high-speed serial interface. This paper presents a 12. 5Gbps phase interpolator (PI)-based quarter-rate CDR ofJESD204B interface. After detailed loop analysis, this work puts forward a novel first-order CDR loop with adaptive filtering coefficient. The filter coefficient can be adjusted with the frequency offset and phase error which could reduce the jitter of recovery clock and data and make the loop have strong frequency offset tracking ability. This CDR occupies area of 0.4mm2 and consumes a power of 34mW with a supply voltage 1. 2V in TSMC 65nm CMOS technology. The post simulation result shows that the frequency offset tracking range is 300ppm with 12. 5Gbps data rate. The jitter of recovered data and recovery clock are 0. 006UI and 0. 012UI when there is no jitter in the input data.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80687674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660270
Yue Bing, Yang Zhi, Zhou Luyao, Zhao Lin, Lin Haofan, Yang Yong
An accident occurred in the substation due to a 220 kV voltage transformer failure that caused a bus differential protection alarm. This article comprehensively analyzes the cause of the failure based on the cause of the incident, the on-site test and inspection situation and the disassembly situation of the factory. The article comprehensively uses protection monitoring waveform analysis, infrared temperature measurement and field test to carry out failure mechanism analysis, and provides reference opinions for subsequent maintenance and repair of related products of the same type to improve equipment operation and maintenance level.
{"title":"Analysis Report of A Phase CVT Fault in 220kV Auxiliary Section I of 500kV Substation","authors":"Yue Bing, Yang Zhi, Zhou Luyao, Zhao Lin, Lin Haofan, Yang Yong","doi":"10.1109/ICICM54364.2021.9660270","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660270","url":null,"abstract":"An accident occurred in the substation due to a 220 kV voltage transformer failure that caused a bus differential protection alarm. This article comprehensively analyzes the cause of the failure based on the cause of the incident, the on-site test and inspection situation and the disassembly situation of the factory. The article comprehensively uses protection monitoring waveform analysis, infrared temperature measurement and field test to carry out failure mechanism analysis, and provides reference opinions for subsequent maintenance and repair of related products of the same type to improve equipment operation and maintenance level.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77874885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660227
Xinru Chen, Bo Yang, Cheng Li, Xinxing Guo
The tunnel magnetoresistive (TMR) accelerometer is a new generation of high-precision inertial sensitive devices. In this work, a micromechanical TMR accelerometer based on electrostatic force feedback is proposed. A permanent magnet film is connected with the seismic mass. The input acceleration leads to a certain displacement of the sensitive structure, thereby causes the change of the magnetic field strength. The magnitude of the acceleration is obtained by detecting the evolution of the magnetic field. On the other hand, the feedback force that pulls the mass back to the initial position is continuously generated, therefore, the mass is always in an equilibrium position. According to the simulation analysis, the simulated sensitivity of the sensitive structure is 125.6um/g and the maximum value of the magnetic field intensity changing with the displacement is 0.1mT/mm. Consequently, the mechanical sensitivity of the micromechanical accelerometer in our proposal design is 12.56uT/g. With the effective electrostatic force feedback structure design, the proposed tunnel magnetoresistive accelerometer has a more extensive dynamic range and remarkable stability.
{"title":"Design and Simulation of a Tunnel Magnetoresistive Accelerometer Based on Electrostatic Force Feedback","authors":"Xinru Chen, Bo Yang, Cheng Li, Xinxing Guo","doi":"10.1109/ICICM54364.2021.9660227","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660227","url":null,"abstract":"The tunnel magnetoresistive (TMR) accelerometer is a new generation of high-precision inertial sensitive devices. In this work, a micromechanical TMR accelerometer based on electrostatic force feedback is proposed. A permanent magnet film is connected with the seismic mass. The input acceleration leads to a certain displacement of the sensitive structure, thereby causes the change of the magnetic field strength. The magnitude of the acceleration is obtained by detecting the evolution of the magnetic field. On the other hand, the feedback force that pulls the mass back to the initial position is continuously generated, therefore, the mass is always in an equilibrium position. According to the simulation analysis, the simulated sensitivity of the sensitive structure is 125.6um/g and the maximum value of the magnetic field intensity changing with the displacement is 0.1mT/mm. Consequently, the mechanical sensitivity of the micromechanical accelerometer in our proposal design is 12.56uT/g. With the effective electrostatic force feedback structure design, the proposed tunnel magnetoresistive accelerometer has a more extensive dynamic range and remarkable stability.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76351664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a 28-GHz high efficiency outphasing power amplifier (PA) with Chireix compensation in 65-nm Silicon-On-Insulator (SOI) CMOS technology is proposed. To improve the power-back-off (PBO) efficiency, the PA uses a current-mode inverse outphasing architecture, which supports compatibility with current-mode PAs, highly efficient active load modulation. Meanwhile, the neutralization capacitor and source degeneration inductor technology is employed to tradeoff linearity and high efficiency requirements. At 28GHz with a supply voltage of 2.5/1.2V, the complete outphasing PA achieves a simulated saturated output power of 23.8dBm with 45.1% power-added efficiency (PAE) and 6dB back-off PAE of 25.2%, 1-dB compression output power of 21.8dBm, and gain of 16.6dB. The simulation results also show that the PA is unconditionally stable in the whole working frequency band. The power amplifier has a layout size of 1.02 mm2 and a core area of 0.46 mm2.
{"title":"A 28-GHz Current-Mode Inverse-Outphasing Power Amplifier in 65-nm CMOS","authors":"Liang-Hui Li, Dongliang Ni, Jiazheng Chen, Jiwei Huang","doi":"10.1109/ICICM54364.2021.9660333","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660333","url":null,"abstract":"In this paper, a 28-GHz high efficiency outphasing power amplifier (PA) with Chireix compensation in 65-nm Silicon-On-Insulator (SOI) CMOS technology is proposed. To improve the power-back-off (PBO) efficiency, the PA uses a current-mode inverse outphasing architecture, which supports compatibility with current-mode PAs, highly efficient active load modulation. Meanwhile, the neutralization capacitor and source degeneration inductor technology is employed to tradeoff linearity and high efficiency requirements. At 28GHz with a supply voltage of 2.5/1.2V, the complete outphasing PA achieves a simulated saturated output power of 23.8dBm with 45.1% power-added efficiency (PAE) and 6dB back-off PAE of 25.2%, 1-dB compression output power of 21.8dBm, and gain of 16.6dB. The simulation results also show that the PA is unconditionally stable in the whole working frequency band. The power amplifier has a layout size of 1.02 mm2 and a core area of 0.46 mm2.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76369369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660244
Jun’an Zhang, Jinxin Hu, Tiehu Li
This paper presented an equivalent circuit based on a 65nm NMOS model to simulate the hot carrier injection (HCI) effect. Under HCI effect, many electrical characteristics such as threshold voltage, trans conductance, drain-source current, gate leakage current, etc, will be obviously changed during a long period of operation time and under different voltage stress. The method of directly modifying SPICE model to simulate HCI effect is complex, and it may lead to non-convergence. Based on an NMOSFET model of a 65nm CMOS PDK, adding some common electrical components and arithmetic units to form an equivalent circuit is a practical way. This model has 4 input parameters, such as width of gate (W), length of gate (L), environment temperature (Temp), operation period (Year). The voltage stress of drain source, drain-gate, gate-source are also considered in this model. The simulation results show that the electrical performance of NMOS transistor under HCI is fitted many measured data of published papers. This equivalent circuit model can be used in the integrated circuit to estimate the effect of HCI.
{"title":"An Equivalent Circuit of Hot Carrier Injection in Short-channel N-MOSFET","authors":"Jun’an Zhang, Jinxin Hu, Tiehu Li","doi":"10.1109/ICICM54364.2021.9660244","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660244","url":null,"abstract":"This paper presented an equivalent circuit based on a 65nm NMOS model to simulate the hot carrier injection (HCI) effect. Under HCI effect, many electrical characteristics such as threshold voltage, trans conductance, drain-source current, gate leakage current, etc, will be obviously changed during a long period of operation time and under different voltage stress. The method of directly modifying SPICE model to simulate HCI effect is complex, and it may lead to non-convergence. Based on an NMOSFET model of a 65nm CMOS PDK, adding some common electrical components and arithmetic units to form an equivalent circuit is a practical way. This model has 4 input parameters, such as width of gate (W), length of gate (L), environment temperature (Temp), operation period (Year). The voltage stress of drain source, drain-gate, gate-source are also considered in this model. The simulation results show that the electrical performance of NMOS transistor under HCI is fitted many measured data of published papers. This equivalent circuit model can be used in the integrated circuit to estimate the effect of HCI.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80186917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to adapt to the application of electronic devices such as wideband receivers, high-precision and high-speed ADCs have become a hot research topic. In this paper, a 13-bit successive approximation analog-to-digital converter (SAR ADC) with a conversion rate of 500-MS/s is introduced. The voltage domain interpolation (Interpolated) technique is used to achieve 4 bits per conversion, and the number of reduced comparators is reduced to half by using the time domain interpolation structure. The SAR ADC redundancy correction technique based on the pipelined ADC redundancy correction principle is investigated and discussed, allowing the ADC to have ± 0.5 LSB misalignment per conversion.
{"title":"A 13-bit Hybrid Interpolated SAR ADC","authors":"Yiqun Wang, Peng Miao, Fei Li, Huan Wang, Bowen Ding, Weiqi Gu","doi":"10.1109/ICICM54364.2021.9660340","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660340","url":null,"abstract":"In order to adapt to the application of electronic devices such as wideband receivers, high-precision and high-speed ADCs have become a hot research topic. In this paper, a 13-bit successive approximation analog-to-digital converter (SAR ADC) with a conversion rate of 500-MS/s is introduced. The voltage domain interpolation (Interpolated) technique is used to achieve 4 bits per conversion, and the number of reduced comparators is reduced to half by using the time domain interpolation structure. The SAR ADC redundancy correction technique based on the pipelined ADC redundancy correction principle is investigated and discussed, allowing the ADC to have ± 0.5 LSB misalignment per conversion.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85254847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660316
Yan Wang, Qingsheng Hu, Xinyu Song
This paper presents a 40Gb/s PAM4 transmitter with a 3-tap fractionally-spaced equalizer (FSE) in 65nm CMOS technology. In order to improve the signal quality, a FSE instead of a symbol-space equalizer (SSE) is realized. In addition, the nonlinearity between the high and low bit output current is reduced by employing low-voltage cascode current source. Post simulation result shows that by boosting the high frequency components effectively, PAM4 signals with clear eye-diagram can be obtained at receiver for a channel with 6.45 dB attenuation @10 GHz. The minimum vertical and horizontal opening of the eye diagram is about 154 mVpp and near 0.6UI. The total area of the transmitter is about 705μm × 495μm including I/O pads and the power consumption is about 72mW under 1.2V power supply.
本文介绍了一种采用65nm CMOS技术的40Gb/s PAM4发射机，该发射机具有3分路分数间隔均衡器(FSE)。为了提高信号质量，采用FSE代替符号空间均衡器(SSE)。此外，通过采用低压级联电流源，降低了高低位输出电流之间的非线性。后置仿真结果表明，通过对高频分量的有效增强，可以在接收机处获得具有清晰眼图的PAM4信号，信道衰减为6.45 dB @10 GHz。眼图的最小垂直和水平开口约为154 mVpp，接近0.6UI。包括I/O垫在内，发射机的总面积约为705μm × 495μm，在1.2V电源下，功耗约为72mW。
{"title":"A 40Gb/s PAM4 Transmitter with 3-tap FSE for Serial Link System","authors":"Yan Wang, Qingsheng Hu, Xinyu Song","doi":"10.1109/ICICM54364.2021.9660316","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660316","url":null,"abstract":"This paper presents a 40Gb/s PAM4 transmitter with a 3-tap fractionally-spaced equalizer (FSE) in 65nm CMOS technology. In order to improve the signal quality, a FSE instead of a symbol-space equalizer (SSE) is realized. In addition, the nonlinearity between the high and low bit output current is reduced by employing low-voltage cascode current source. Post simulation result shows that by boosting the high frequency components effectively, PAM4 signals with clear eye-diagram can be obtained at receiver for a channel with 6.45 dB attenuation @10 GHz. The minimum vertical and horizontal opening of the eye diagram is about 154 mVpp and near 0.6UI. The total area of the transmitter is about 705μm × 495μm including I/O pads and the power consumption is about 72mW under 1.2V power supply.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90143600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660290
Yuqi Bing, Zhao Lin, Lin Haofan, Yang Yong
Abstract-On-load tap-changer is a switching device that provides a constant voltage for a transformer when the load changes. The basic principle is to realize the switching between taps in the transformer winding without interrupting the load current, thereby changing the number of winding turns, that is, the voltage ratio of the transformer, and finally achieving the purpose of voltage regulation. In this paper, the characteristic parameters are collected by time domain analysis method, which provides the basis for discriminating the later fault warning.
{"title":"Analysis of Time Domain Characteristic of Transformer On-load Tap-changer","authors":"Yuqi Bing, Zhao Lin, Lin Haofan, Yang Yong","doi":"10.1109/ICICM54364.2021.9660290","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660290","url":null,"abstract":"Abstract-On-load tap-changer is a switching device that provides a constant voltage for a transformer when the load changes. The basic principle is to realize the switching between taps in the transformer winding without interrupting the load current, thereby changing the number of winding turns, that is, the voltage ratio of the transformer, and finally achieving the purpose of voltage regulation. In this paper, the characteristic parameters are collected by time domain analysis method, which provides the basis for discriminating the later fault warning.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81382671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660315
Ziran Chen, Mengjia Huang, Zhi Huang, Han Wang, Le He, Meng Zhang
A Ku-band low noise amplifier (LNA) is presented in this paper, which is suitable for the Ku-band satellite communication receiving channel. The miniaturized LNA is established based on the micro-system design principle. The two-stage hetero-junction FET cascade structure is adopted. Based on a reasonable selection of matching structure, a low-pass filter (LPF) is added to suppress out-of-band interference. And the EDA software is applied to optimize the matching circuit. According to the results, the LNA achieves a noise Figure (NF) less than 1.55dB and a gain greater than 24dB in the working frequency range of 12GHz to 13GHz, meanwhile the input and output are well matched.
{"title":"Design of Ku-Band Low Noise Amplifier for Satellite Communication Applications","authors":"Ziran Chen, Mengjia Huang, Zhi Huang, Han Wang, Le He, Meng Zhang","doi":"10.1109/ICICM54364.2021.9660315","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660315","url":null,"abstract":"A Ku-band low noise amplifier (LNA) is presented in this paper, which is suitable for the Ku-band satellite communication receiving channel. The miniaturized LNA is established based on the micro-system design principle. The two-stage hetero-junction FET cascade structure is adopted. Based on a reasonable selection of matching structure, a low-pass filter (LPF) is added to suppress out-of-band interference. And the EDA software is applied to optimize the matching circuit. According to the results, the LNA achieves a noise Figure (NF) less than 1.55dB and a gain greater than 24dB in the working frequency range of 12GHz to 13GHz, meanwhile the input and output are well matched.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82516381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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