Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660341
Hongwei Guo, Zhiqun Li, Aiyuan Miao, Xiaowei Wang, Zhennan Li
This paper proposes an automatic gain control (AGC) amplifier consisting of a linear-in-dB VGA, a peak detector (PD), an error amplifier and a loop filter. The AGC chip is fabricated in a 22nm CMOS technology and consuming power of 13.5 mW under the supply voltage of 1-V. The linear-in-dB VGA realizes the gain adjusting without using extra exponential voltage generating modules, which largely reduces corresponding chip area of this AGC to $0.006 mm^{2}$. The linear-in-dB gain dynamic range is 35 dB and the 3-dB bandwidth is about 1 GHz, satisfying the operating frequency band.
本文提出了一种自动增益控制放大器(AGC)，该放大器由一个db内线性VGA、一个峰值检测器(PD)、一个误差放大器和一个环路滤波器组成。AGC芯片采用22nm CMOS工艺制造，在1 v电源电压下功耗为13.5 mW。线性-in- db VGA在不使用额外的指数电压产生模块的情况下实现了增益调节，大大减小了AGC的相应芯片面积至0.006 mm^{2}$。线性dB增益动态范围为35db, 3db带宽约为1ghz，满足工作频带。
{"title":"An Automatic Gain Control Amplifier with Linear-in-dB Gain in 22nm CMOS","authors":"Hongwei Guo, Zhiqun Li, Aiyuan Miao, Xiaowei Wang, Zhennan Li","doi":"10.1109/ICICM54364.2021.9660341","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660341","url":null,"abstract":"This paper proposes an automatic gain control (AGC) amplifier consisting of a linear-in-dB VGA, a peak detector (PD), an error amplifier and a loop filter. The AGC chip is fabricated in a 22nm CMOS technology and consuming power of 13.5 mW under the supply voltage of 1-V. The linear-in-dB VGA realizes the gain adjusting without using extra exponential voltage generating modules, which largely reduces corresponding chip area of this AGC to $0.006 mm^{2}$. The linear-in-dB gain dynamic range is 35 dB and the 3-dB bandwidth is about 1 GHz, satisfying the operating frequency band.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"21 1","pages":"272-275"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81996828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660239
Jie Wang, Shuqin Geng, Xiaohong Peng, Xuefeng Li, Qian Sun, Pengkun Li
This article describes the UVM verification platform built with system verilog language, which realizes the functional verification of Direct Memory Access, and achieves verification of the correctness of DUT functions and coverage statistics. The verification results show that DMA functions correctly in different working modes, and the coverage rate has reached 100% collection. The UVM verification platform has high flexibility, can greatly improve the verification efficiency and the reusability of the verification platform, and meet the needs of IC verification.
{"title":"DMA Function Verification Based on UVM Verification Platform","authors":"Jie Wang, Shuqin Geng, Xiaohong Peng, Xuefeng Li, Qian Sun, Pengkun Li","doi":"10.1109/ICICM54364.2021.9660239","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660239","url":null,"abstract":"This article describes the UVM verification platform built with system verilog language, which realizes the functional verification of Direct Memory Access, and achieves verification of the correctness of DUT functions and coverage statistics. The verification results show that DMA functions correctly in different working modes, and the coverage rate has reached 100% collection. The UVM verification platform has high flexibility, can greatly improve the verification efficiency and the reusability of the verification platform, and meet the needs of IC verification.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"39 1","pages":"276-279"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80940056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660241
Yuan Liang, Zhiqun Li, Dongdong Chen, Xiaowei Wang, Zhennan Li
An anti-blocking down-conversion mixer circuit with operating frequency of 2.4-5.25 GHz based on 22-nm CMOS process is presented in this paper, which is mainly composed of four modules: passive switch pair, 25% duty cycle generator, switched capacitor array and baseband amplifier circuit with DC cancellation function. High resilience to out-of-band interference is achieved thanks to a mixer-based RF blocker filter. The results show that under 1V power supply voltage, the voltage conversion gain is better than 18 dB, the noise Figure is less than 13 dB, and the operating current is less than 9 mA.
{"title":"A 22nm CMOS 2.4-5.25GHz Mixer Resilient to Out-of-Band Blockers","authors":"Yuan Liang, Zhiqun Li, Dongdong Chen, Xiaowei Wang, Zhennan Li","doi":"10.1109/ICICM54364.2021.9660241","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660241","url":null,"abstract":"An anti-blocking down-conversion mixer circuit with operating frequency of 2.4-5.25 GHz based on 22-nm CMOS process is presented in this paper, which is mainly composed of four modules: passive switch pair, 25% duty cycle generator, switched capacitor array and baseband amplifier circuit with DC cancellation function. High resilience to out-of-band interference is achieved thanks to a mixer-based RF blocker filter. The results show that under 1V power supply voltage, the voltage conversion gain is better than 18 dB, the noise Figure is less than 13 dB, and the operating current is less than 9 mA.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"13 1","pages":"179-183"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83450780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660288
Chi Zhang, Longbin Zhu, Rui Yang, Zhijun Zhou, Qiao Meng, Zhigong Wang
A high impedance path with linear DC and frequency response is critical in neural signal applications, such as biasing the neural signal to protect the living cells against overheating, increasing the feedback gain and forming a very large time constant cut-off frequency of a filter. When in integrated circuit (IC) form, pseudo resistors (PR) yield a large resistance within an acceptable die area. However, its linearity is limited by the nonlinear MOS transistors in weak inversion. The linearity can be improved by utilizing a voltage buffer. However, the impedance of the voltage buffer is limited by the output resistance of the amplifier. In this paper, a feedback-controlled technique targeting neural signal applications is proposed. It substantially employs a high impedance, and provides an enhanced linearity with a wide frequency range.
{"title":"A Feedback-Controlled Technique with High Impedance and High Linearity for Neural Signal Applications","authors":"Chi Zhang, Longbin Zhu, Rui Yang, Zhijun Zhou, Qiao Meng, Zhigong Wang","doi":"10.1109/ICICM54364.2021.9660288","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660288","url":null,"abstract":"A high impedance path with linear DC and frequency response is critical in neural signal applications, such as biasing the neural signal to protect the living cells against overheating, increasing the feedback gain and forming a very large time constant cut-off frequency of a filter. When in integrated circuit (IC) form, pseudo resistors (PR) yield a large resistance within an acceptable die area. However, its linearity is limited by the nonlinear MOS transistors in weak inversion. The linearity can be improved by utilizing a voltage buffer. However, the impedance of the voltage buffer is limited by the output resistance of the amplifier. In this paper, a feedback-controlled technique targeting neural signal applications is proposed. It substantially employs a high impedance, and provides an enhanced linearity with a wide frequency range.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"235 1","pages":"313-318"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77078195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A battery-less thermoelectric energy harvesting power management integrated circuit (PMIC) with low self startup voltage is implemented in a 180 nm CMOS process. A two stage step-by-step self-startup circuit enables operation the system from input voltages as low as 10 mV. A maximum power point tracking (MPPT) circuit with a frequency trimming technique is employed to extract the maximum energy from the TEG under a smaller temperature gradient and improve the overall stability of the system. Zero-current sensing (ZCS) detects the position of zero current during the discharge of the inductor and ends the discharge process in time by using two comparator monitoring methods, greatly reducing the energy backflow at the load side and improving the conversion efficiency. With a minimum cold-start voltage of180 mV and a minimum operating voltage of10 mV, the average power consumption of the PMIC was 24.6 $mu$W, the output voltage range was 1.7 V, and the end-to-end conversion efficiency of the boost converter was 78.3%.
{"title":"A Power Management Unit for Battery-Less TEG Energy Harvesting With Low Voltage Self-Startup","authors":"Peng Cui, Baolin Wei, Zhanrong Liang, Xueming Wei, Weilin Xu","doi":"10.1109/ICICM54364.2021.9660277","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660277","url":null,"abstract":"A battery-less thermoelectric energy harvesting power management integrated circuit (PMIC) with low self startup voltage is implemented in a 180 nm CMOS process. A two stage step-by-step self-startup circuit enables operation the system from input voltages as low as 10 mV. A maximum power point tracking (MPPT) circuit with a frequency trimming technique is employed to extract the maximum energy from the TEG under a smaller temperature gradient and improve the overall stability of the system. Zero-current sensing (ZCS) detects the position of zero current during the discharge of the inductor and ends the discharge process in time by using two comparator monitoring methods, greatly reducing the energy backflow at the load side and improving the conversion efficiency. With a minimum cold-start voltage of180 mV and a minimum operating voltage of10 mV, the average power consumption of the PMIC was 24.6 $mu$W, the output voltage range was 1.7 V, and the end-to-end conversion efficiency of the boost converter was 78.3%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"5 1","pages":"160-165"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90648136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660270
Yue Bing, Yang Zhi, Zhou Luyao, Zhao Lin, Lin Haofan, Yang Yong
An accident occurred in the substation due to a 220 kV voltage transformer failure that caused a bus differential protection alarm. This article comprehensively analyzes the cause of the failure based on the cause of the incident, the on-site test and inspection situation and the disassembly situation of the factory. The article comprehensively uses protection monitoring waveform analysis, infrared temperature measurement and field test to carry out failure mechanism analysis, and provides reference opinions for subsequent maintenance and repair of related products of the same type to improve equipment operation and maintenance level.
{"title":"Analysis Report of A Phase CVT Fault in 220kV Auxiliary Section I of 500kV Substation","authors":"Yue Bing, Yang Zhi, Zhou Luyao, Zhao Lin, Lin Haofan, Yang Yong","doi":"10.1109/ICICM54364.2021.9660270","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660270","url":null,"abstract":"An accident occurred in the substation due to a 220 kV voltage transformer failure that caused a bus differential protection alarm. This article comprehensively analyzes the cause of the failure based on the cause of the incident, the on-site test and inspection situation and the disassembly situation of the factory. The article comprehensively uses protection monitoring waveform analysis, infrared temperature measurement and field test to carry out failure mechanism analysis, and provides reference opinions for subsequent maintenance and repair of related products of the same type to improve equipment operation and maintenance level.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"29 1","pages":"376-379"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77874885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660227
Xinru Chen, Bo Yang, Cheng Li, Xinxing Guo
The tunnel magnetoresistive (TMR) accelerometer is a new generation of high-precision inertial sensitive devices. In this work, a micromechanical TMR accelerometer based on electrostatic force feedback is proposed. A permanent magnet film is connected with the seismic mass. The input acceleration leads to a certain displacement of the sensitive structure, thereby causes the change of the magnetic field strength. The magnitude of the acceleration is obtained by detecting the evolution of the magnetic field. On the other hand, the feedback force that pulls the mass back to the initial position is continuously generated, therefore, the mass is always in an equilibrium position. According to the simulation analysis, the simulated sensitivity of the sensitive structure is 125.6um/g and the maximum value of the magnetic field intensity changing with the displacement is 0.1mT/mm. Consequently, the mechanical sensitivity of the micromechanical accelerometer in our proposal design is 12.56uT/g. With the effective electrostatic force feedback structure design, the proposed tunnel magnetoresistive accelerometer has a more extensive dynamic range and remarkable stability.
{"title":"Design and Simulation of a Tunnel Magnetoresistive Accelerometer Based on Electrostatic Force Feedback","authors":"Xinru Chen, Bo Yang, Cheng Li, Xinxing Guo","doi":"10.1109/ICICM54364.2021.9660227","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660227","url":null,"abstract":"The tunnel magnetoresistive (TMR) accelerometer is a new generation of high-precision inertial sensitive devices. In this work, a micromechanical TMR accelerometer based on electrostatic force feedback is proposed. A permanent magnet film is connected with the seismic mass. The input acceleration leads to a certain displacement of the sensitive structure, thereby causes the change of the magnetic field strength. The magnitude of the acceleration is obtained by detecting the evolution of the magnetic field. On the other hand, the feedback force that pulls the mass back to the initial position is continuously generated, therefore, the mass is always in an equilibrium position. According to the simulation analysis, the simulated sensitivity of the sensitive structure is 125.6um/g and the maximum value of the magnetic field intensity changing with the displacement is 0.1mT/mm. Consequently, the mechanical sensitivity of the micromechanical accelerometer in our proposal design is 12.56uT/g. With the effective electrostatic force feedback structure design, the proposed tunnel magnetoresistive accelerometer has a more extensive dynamic range and remarkable stability.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"159 1","pages":"90-94"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76351664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a 28-GHz high efficiency outphasing power amplifier (PA) with Chireix compensation in 65-nm Silicon-On-Insulator (SOI) CMOS technology is proposed. To improve the power-back-off (PBO) efficiency, the PA uses a current-mode inverse outphasing architecture, which supports compatibility with current-mode PAs, highly efficient active load modulation. Meanwhile, the neutralization capacitor and source degeneration inductor technology is employed to tradeoff linearity and high efficiency requirements. At 28GHz with a supply voltage of 2.5/1.2V, the complete outphasing PA achieves a simulated saturated output power of 23.8dBm with 45.1% power-added efficiency (PAE) and 6dB back-off PAE of 25.2%, 1-dB compression output power of 21.8dBm, and gain of 16.6dB. The simulation results also show that the PA is unconditionally stable in the whole working frequency band. The power amplifier has a layout size of 1.02 mm2 and a core area of 0.46 mm2.
{"title":"A 28-GHz Current-Mode Inverse-Outphasing Power Amplifier in 65-nm CMOS","authors":"Liang-Hui Li, Dongliang Ni, Jiazheng Chen, Jiwei Huang","doi":"10.1109/ICICM54364.2021.9660333","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660333","url":null,"abstract":"In this paper, a 28-GHz high efficiency outphasing power amplifier (PA) with Chireix compensation in 65-nm Silicon-On-Insulator (SOI) CMOS technology is proposed. To improve the power-back-off (PBO) efficiency, the PA uses a current-mode inverse outphasing architecture, which supports compatibility with current-mode PAs, highly efficient active load modulation. Meanwhile, the neutralization capacitor and source degeneration inductor technology is employed to tradeoff linearity and high efficiency requirements. At 28GHz with a supply voltage of 2.5/1.2V, the complete outphasing PA achieves a simulated saturated output power of 23.8dBm with 45.1% power-added efficiency (PAE) and 6dB back-off PAE of 25.2%, 1-dB compression output power of 21.8dBm, and gain of 16.6dB. The simulation results also show that the PA is unconditionally stable in the whole working frequency band. The power amplifier has a layout size of 1.02 mm2 and a core area of 0.46 mm2.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"34 1","pages":"268-271"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76369369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660244
Jun’an Zhang, Jinxin Hu, Tiehu Li
This paper presented an equivalent circuit based on a 65nm NMOS model to simulate the hot carrier injection (HCI) effect. Under HCI effect, many electrical characteristics such as threshold voltage, trans conductance, drain-source current, gate leakage current, etc, will be obviously changed during a long period of operation time and under different voltage stress. The method of directly modifying SPICE model to simulate HCI effect is complex, and it may lead to non-convergence. Based on an NMOSFET model of a 65nm CMOS PDK, adding some common electrical components and arithmetic units to form an equivalent circuit is a practical way. This model has 4 input parameters, such as width of gate (W), length of gate (L), environment temperature (Temp), operation period (Year). The voltage stress of drain source, drain-gate, gate-source are also considered in this model. The simulation results show that the electrical performance of NMOS transistor under HCI is fitted many measured data of published papers. This equivalent circuit model can be used in the integrated circuit to estimate the effect of HCI.
{"title":"An Equivalent Circuit of Hot Carrier Injection in Short-channel N-MOSFET","authors":"Jun’an Zhang, Jinxin Hu, Tiehu Li","doi":"10.1109/ICICM54364.2021.9660244","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660244","url":null,"abstract":"This paper presented an equivalent circuit based on a 65nm NMOS model to simulate the hot carrier injection (HCI) effect. Under HCI effect, many electrical characteristics such as threshold voltage, trans conductance, drain-source current, gate leakage current, etc, will be obviously changed during a long period of operation time and under different voltage stress. The method of directly modifying SPICE model to simulate HCI effect is complex, and it may lead to non-convergence. Based on an NMOSFET model of a 65nm CMOS PDK, adding some common electrical components and arithmetic units to form an equivalent circuit is a practical way. This model has 4 input parameters, such as width of gate (W), length of gate (L), environment temperature (Temp), operation period (Year). The voltage stress of drain source, drain-gate, gate-source are also considered in this model. The simulation results show that the electrical performance of NMOS transistor under HCI is fitted many measured data of published papers. This equivalent circuit model can be used in the integrated circuit to estimate the effect of HCI.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"397 1","pages":"45-49"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80186917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660247
Zhangjun Shi, Xiaojin Li, Yabin Sun, Yanling Shi
An electro-thermal co-optimization has been carried out on silicon-on-insulator (SOI) accumulation mode tri-gate (ATG) LDMOS by TCAD simulation. Internal electric field, temperature distribution, critical heat removal path and the thermal resistance of SOI-ATG LDMOS are investigated, providing deep insights into its self-heating mechanism and thermal-aware design. Besides, the junction depth of source/drain, ambient temperature and boundary thermal resistance are optimized to mitigate the self-heating effect (SHE) in SOI-ATG LDMOS. Furthermore, different trench dielectrics are also compared to achieve an electro-thermal co-optimization of SOI-ATG LDMOS.
{"title":"Electro-thermal Investigation on SOI Accumulation Mode Tri-gate LDMOS","authors":"Zhangjun Shi, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1109/ICICM54364.2021.9660247","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660247","url":null,"abstract":"An electro-thermal co-optimization has been carried out on silicon-on-insulator (SOI) accumulation mode tri-gate (ATG) LDMOS by TCAD simulation. Internal electric field, temperature distribution, critical heat removal path and the thermal resistance of SOI-ATG LDMOS are investigated, providing deep insights into its self-heating mechanism and thermal-aware design. Besides, the junction depth of source/drain, ambient temperature and boundary thermal resistance are optimized to mitigate the self-heating effect (SHE) in SOI-ATG LDMOS. Furthermore, different trench dielectrics are also compared to achieve an electro-thermal co-optimization of SOI-ATG LDMOS.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"37 1","pages":"210-213"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81599248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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