Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660341
Hongwei Guo, Zhiqun Li, Aiyuan Miao, Xiaowei Wang, Zhennan Li
This paper proposes an automatic gain control (AGC) amplifier consisting of a linear-in-dB VGA, a peak detector (PD), an error amplifier and a loop filter. The AGC chip is fabricated in a 22nm CMOS technology and consuming power of 13.5 mW under the supply voltage of 1-V. The linear-in-dB VGA realizes the gain adjusting without using extra exponential voltage generating modules, which largely reduces corresponding chip area of this AGC to $0.006 mm^{2}$. The linear-in-dB gain dynamic range is 35 dB and the 3-dB bandwidth is about 1 GHz, satisfying the operating frequency band.
本文提出了一种自动增益控制放大器(AGC)，该放大器由一个db内线性VGA、一个峰值检测器(PD)、一个误差放大器和一个环路滤波器组成。AGC芯片采用22nm CMOS工艺制造，在1 v电源电压下功耗为13.5 mW。线性-in- db VGA在不使用额外的指数电压产生模块的情况下实现了增益调节，大大减小了AGC的相应芯片面积至0.006 mm^{2}$。线性dB增益动态范围为35db, 3db带宽约为1ghz，满足工作频带。
{"title":"An Automatic Gain Control Amplifier with Linear-in-dB Gain in 22nm CMOS","authors":"Hongwei Guo, Zhiqun Li, Aiyuan Miao, Xiaowei Wang, Zhennan Li","doi":"10.1109/ICICM54364.2021.9660341","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660341","url":null,"abstract":"This paper proposes an automatic gain control (AGC) amplifier consisting of a linear-in-dB VGA, a peak detector (PD), an error amplifier and a loop filter. The AGC chip is fabricated in a 22nm CMOS technology and consuming power of 13.5 mW under the supply voltage of 1-V. The linear-in-dB VGA realizes the gain adjusting without using extra exponential voltage generating modules, which largely reduces corresponding chip area of this AGC to $0.006 mm^{2}$. The linear-in-dB gain dynamic range is 35 dB and the 3-dB bandwidth is about 1 GHz, satisfying the operating frequency band.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"21 1","pages":"272-275"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81996828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660239
Jie Wang, Shuqin Geng, Xiaohong Peng, Xuefeng Li, Qian Sun, Pengkun Li
This article describes the UVM verification platform built with system verilog language, which realizes the functional verification of Direct Memory Access, and achieves verification of the correctness of DUT functions and coverage statistics. The verification results show that DMA functions correctly in different working modes, and the coverage rate has reached 100% collection. The UVM verification platform has high flexibility, can greatly improve the verification efficiency and the reusability of the verification platform, and meet the needs of IC verification.
{"title":"DMA Function Verification Based on UVM Verification Platform","authors":"Jie Wang, Shuqin Geng, Xiaohong Peng, Xuefeng Li, Qian Sun, Pengkun Li","doi":"10.1109/ICICM54364.2021.9660239","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660239","url":null,"abstract":"This article describes the UVM verification platform built with system verilog language, which realizes the functional verification of Direct Memory Access, and achieves verification of the correctness of DUT functions and coverage statistics. The verification results show that DMA functions correctly in different working modes, and the coverage rate has reached 100% collection. The UVM verification platform has high flexibility, can greatly improve the verification efficiency and the reusability of the verification platform, and meet the needs of IC verification.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"39 1","pages":"276-279"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80940056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660241
Yuan Liang, Zhiqun Li, Dongdong Chen, Xiaowei Wang, Zhennan Li
An anti-blocking down-conversion mixer circuit with operating frequency of 2.4-5.25 GHz based on 22-nm CMOS process is presented in this paper, which is mainly composed of four modules: passive switch pair, 25% duty cycle generator, switched capacitor array and baseband amplifier circuit with DC cancellation function. High resilience to out-of-band interference is achieved thanks to a mixer-based RF blocker filter. The results show that under 1V power supply voltage, the voltage conversion gain is better than 18 dB, the noise Figure is less than 13 dB, and the operating current is less than 9 mA.
{"title":"A 22nm CMOS 2.4-5.25GHz Mixer Resilient to Out-of-Band Blockers","authors":"Yuan Liang, Zhiqun Li, Dongdong Chen, Xiaowei Wang, Zhennan Li","doi":"10.1109/ICICM54364.2021.9660241","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660241","url":null,"abstract":"An anti-blocking down-conversion mixer circuit with operating frequency of 2.4-5.25 GHz based on 22-nm CMOS process is presented in this paper, which is mainly composed of four modules: passive switch pair, 25% duty cycle generator, switched capacitor array and baseband amplifier circuit with DC cancellation function. High resilience to out-of-band interference is achieved thanks to a mixer-based RF blocker filter. The results show that under 1V power supply voltage, the voltage conversion gain is better than 18 dB, the noise Figure is less than 13 dB, and the operating current is less than 9 mA.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"13 1","pages":"179-183"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83450780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660288
Chi Zhang, Longbin Zhu, Rui Yang, Zhijun Zhou, Qiao Meng, Zhigong Wang
A high impedance path with linear DC and frequency response is critical in neural signal applications, such as biasing the neural signal to protect the living cells against overheating, increasing the feedback gain and forming a very large time constant cut-off frequency of a filter. When in integrated circuit (IC) form, pseudo resistors (PR) yield a large resistance within an acceptable die area. However, its linearity is limited by the nonlinear MOS transistors in weak inversion. The linearity can be improved by utilizing a voltage buffer. However, the impedance of the voltage buffer is limited by the output resistance of the amplifier. In this paper, a feedback-controlled technique targeting neural signal applications is proposed. It substantially employs a high impedance, and provides an enhanced linearity with a wide frequency range.
{"title":"A Feedback-Controlled Technique with High Impedance and High Linearity for Neural Signal Applications","authors":"Chi Zhang, Longbin Zhu, Rui Yang, Zhijun Zhou, Qiao Meng, Zhigong Wang","doi":"10.1109/ICICM54364.2021.9660288","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660288","url":null,"abstract":"A high impedance path with linear DC and frequency response is critical in neural signal applications, such as biasing the neural signal to protect the living cells against overheating, increasing the feedback gain and forming a very large time constant cut-off frequency of a filter. When in integrated circuit (IC) form, pseudo resistors (PR) yield a large resistance within an acceptable die area. However, its linearity is limited by the nonlinear MOS transistors in weak inversion. The linearity can be improved by utilizing a voltage buffer. However, the impedance of the voltage buffer is limited by the output resistance of the amplifier. In this paper, a feedback-controlled technique targeting neural signal applications is proposed. It substantially employs a high impedance, and provides an enhanced linearity with a wide frequency range.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"235 1","pages":"313-318"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77078195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A battery-less thermoelectric energy harvesting power management integrated circuit (PMIC) with low self startup voltage is implemented in a 180 nm CMOS process. A two stage step-by-step self-startup circuit enables operation the system from input voltages as low as 10 mV. A maximum power point tracking (MPPT) circuit with a frequency trimming technique is employed to extract the maximum energy from the TEG under a smaller temperature gradient and improve the overall stability of the system. Zero-current sensing (ZCS) detects the position of zero current during the discharge of the inductor and ends the discharge process in time by using two comparator monitoring methods, greatly reducing the energy backflow at the load side and improving the conversion efficiency. With a minimum cold-start voltage of180 mV and a minimum operating voltage of10 mV, the average power consumption of the PMIC was 24.6 $mu$W, the output voltage range was 1.7 V, and the end-to-end conversion efficiency of the boost converter was 78.3%.
{"title":"A Power Management Unit for Battery-Less TEG Energy Harvesting With Low Voltage Self-Startup","authors":"Peng Cui, Baolin Wei, Zhanrong Liang, Xueming Wei, Weilin Xu","doi":"10.1109/ICICM54364.2021.9660277","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660277","url":null,"abstract":"A battery-less thermoelectric energy harvesting power management integrated circuit (PMIC) with low self startup voltage is implemented in a 180 nm CMOS process. A two stage step-by-step self-startup circuit enables operation the system from input voltages as low as 10 mV. A maximum power point tracking (MPPT) circuit with a frequency trimming technique is employed to extract the maximum energy from the TEG under a smaller temperature gradient and improve the overall stability of the system. Zero-current sensing (ZCS) detects the position of zero current during the discharge of the inductor and ends the discharge process in time by using two comparator monitoring methods, greatly reducing the energy backflow at the load side and improving the conversion efficiency. With a minimum cold-start voltage of180 mV and a minimum operating voltage of10 mV, the average power consumption of the PMIC was 24.6 $mu$W, the output voltage range was 1.7 V, and the end-to-end conversion efficiency of the boost converter was 78.3%.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"5 1","pages":"160-165"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90648136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660259
Fen Guo, Tuo Li, Hongtao Man, Kai Liu, Xiaoliang Wang
In this paper, an enhanced heat dissipation structure, combining diamond substrate and diamond spreader, is considered for further improving the heat dissipation efficiency of GaNRF devices. The steady-state simulation is performed to analyze the thermal management ability of heat dissipation structures. The simulation is mainly focused on the comparisons of heat transfer capability and characteristics for double-diamond heat dissipation structure and the others, including GaN on SiC, GaN on diamond and GaN on SiC with diamond spreader. Simulation demonstrates that the junction temperature of device with double-diamond structure is 120°C, significantly lower than that on SiC substrate, since the coordination of diamond substrate and diamond spreader strengthens heat dissipation in both directions. The results also show that the heat dissipation performance of device is improved about 15 % by adding only 10 $mu$m diamond spreader in double-diamond structure compared to that of single diamond substrate. In addition, the heat transfer ability could be further enhanced by optimizing the spreader thickness and the interface thermal resistance.
为了进一步提高GaNRF器件的散热效率，本文考虑了一种结合金刚石衬底和金刚石扩散片的增强散热结构。通过稳态仿真分析了散热结构的热管理能力。模拟主要比较了双金刚石散热结构与GaN on SiC、GaN on diamond和GaN on SiC带金刚石扩散器的散热结构的传热能力和特性。仿真结果表明，双金刚石结构器件的结温为120℃，明显低于SiC衬底的结温，这是由于金刚石衬底与金刚石扩散器的协同作用增强了双向散热。结果还表明，与单金刚石衬底相比，在双金刚石结构中仅添加10 $mu$m金刚石衬底，器件的散热性能提高了约15%。此外，通过优化扩散板厚度和界面热阻，可以进一步提高传热能力。
{"title":"Enhanced Heat Dissipation of GaN RF Devices Based on Double-diamond Structure","authors":"Fen Guo, Tuo Li, Hongtao Man, Kai Liu, Xiaoliang Wang","doi":"10.1109/ICICM54364.2021.9660259","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660259","url":null,"abstract":"In this paper, an enhanced heat dissipation structure, combining diamond substrate and diamond spreader, is considered for further improving the heat dissipation efficiency of GaNRF devices. The steady-state simulation is performed to analyze the thermal management ability of heat dissipation structures. The simulation is mainly focused on the comparisons of heat transfer capability and characteristics for double-diamond heat dissipation structure and the others, including GaN on SiC, GaN on diamond and GaN on SiC with diamond spreader. Simulation demonstrates that the junction temperature of device with double-diamond structure is 120°C, significantly lower than that on SiC substrate, since the coordination of diamond substrate and diamond spreader strengthens heat dissipation in both directions. The results also show that the heat dissipation performance of device is improved about 15 % by adding only 10 $mu$m diamond spreader in double-diamond structure compared to that of single diamond substrate. In addition, the heat transfer ability could be further enhanced by optimizing the spreader thickness and the interface thermal resistance.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"55-60"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88577253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660223
Ying Li, Hong Ma, Xin Ge, Xiaowan Dai, Yongshan Hu, Yulu Chen, Xiaodong Wang
We have developed a $128 times128$ cryogenic readout circuit suitable for Silicon-based Blocked-impurity-band detector by means of 0.18 m CMOS technology in this paper, which can be used at 6K temperature. Based on the extraction of parameters and the establishment of the cryogenic temperature model of MOSFET, we focus on the design of the pixel circuit and readout mode. In the design, the correlated double sampling technology is also used to reduce the noise generated in the channel. The designed readout circuit can work at both room temperature and 6K, where the working frequency is 1MHz, the maximum power consumption is 127.38mW, and the output swing is about 2V.
本文采用0.18 m CMOS技术，开发了一种适用于硅基阻塞杂质带探测器的$128 times128$低温读出电路，可在6K温度下使用。在参数提取和MOSFET低温模型建立的基础上，重点设计了像素电路和读出模式。在设计中，还采用了相关双采样技术来降低信道中产生的噪声。所设计的读出电路可以在室温和6K下工作，其中工作频率为1MHz，最大功耗为127.38mW，输出摆幅约为2V。
{"title":"Design of a 128×128 Cryogenic Readout Circuit for Silicon-based Blocked-impurity-band Detector","authors":"Ying Li, Hong Ma, Xin Ge, Xiaowan Dai, Yongshan Hu, Yulu Chen, Xiaodong Wang","doi":"10.1109/ICICM54364.2021.9660223","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660223","url":null,"abstract":"We have developed a $128 times128$ cryogenic readout circuit suitable for Silicon-based Blocked-impurity-band detector by means of 0.18 m CMOS technology in this paper, which can be used at 6K temperature. Based on the extraction of parameters and the establishment of the cryogenic temperature model of MOSFET, we focus on the design of the pixel circuit and readout mode. In the design, the correlated double sampling technology is also used to reduce the noise generated in the channel. The designed readout circuit can work at both room temperature and 6K, where the working frequency is 1MHz, the maximum power consumption is 127.38mW, and the output swing is about 2V.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"54 1","pages":"19-22"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86255554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660247
Zhangjun Shi, Xiaojin Li, Yabin Sun, Yanling Shi
An electro-thermal co-optimization has been carried out on silicon-on-insulator (SOI) accumulation mode tri-gate (ATG) LDMOS by TCAD simulation. Internal electric field, temperature distribution, critical heat removal path and the thermal resistance of SOI-ATG LDMOS are investigated, providing deep insights into its self-heating mechanism and thermal-aware design. Besides, the junction depth of source/drain, ambient temperature and boundary thermal resistance are optimized to mitigate the self-heating effect (SHE) in SOI-ATG LDMOS. Furthermore, different trench dielectrics are also compared to achieve an electro-thermal co-optimization of SOI-ATG LDMOS.
{"title":"Electro-thermal Investigation on SOI Accumulation Mode Tri-gate LDMOS","authors":"Zhangjun Shi, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1109/ICICM54364.2021.9660247","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660247","url":null,"abstract":"An electro-thermal co-optimization has been carried out on silicon-on-insulator (SOI) accumulation mode tri-gate (ATG) LDMOS by TCAD simulation. Internal electric field, temperature distribution, critical heat removal path and the thermal resistance of SOI-ATG LDMOS are investigated, providing deep insights into its self-heating mechanism and thermal-aware design. Besides, the junction depth of source/drain, ambient temperature and boundary thermal resistance are optimized to mitigate the self-heating effect (SHE) in SOI-ATG LDMOS. Furthermore, different trench dielectrics are also compared to achieve an electro-thermal co-optimization of SOI-ATG LDMOS.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"37 1","pages":"210-213"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81599248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660337
Xiao Yun Chen, Lu Tang, Xuan Shen
In this paper, a two-step Time-to-Digital converter (TDC) with a matching coarse-fine interface circuit for all-digital phase-locked loop (ADPLL) in a 40nm CMOS process is presented. A low-precision quantization architecture is used for the coarse stage of the designed two-step TDC to achieve wide dynamic range, and a high-precision quantization architecture is used for the fine stage to ensure higher resolution. A matching coarse-fine interface structure is proposed to reduce the transmission error. The simulation results show that the TDC can balance the performance of resolution, power consumption and dynamic range. The 32-level delay chain is used for the first-stage TDC with a quantization accuracy of 53. 8ps, and a 15-level delay chain with a quantization accuracy of 6. 2ps adopted in the second stage TDC. Under the condition that the reference frequency is 100MHz and its core chip size is $0.0431 mm^{2}$.
{"title":"A High-Resolution Two-Step Time-to-Digital Conversion in 40 nm CMOS","authors":"Xiao Yun Chen, Lu Tang, Xuan Shen","doi":"10.1109/ICICM54364.2021.9660337","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660337","url":null,"abstract":"In this paper, a two-step Time-to-Digital converter (TDC) with a matching coarse-fine interface circuit for all-digital phase-locked loop (ADPLL) in a 40nm CMOS process is presented. A low-precision quantization architecture is used for the coarse stage of the designed two-step TDC to achieve wide dynamic range, and a high-precision quantization architecture is used for the fine stage to ensure higher resolution. A matching coarse-fine interface structure is proposed to reduce the transmission error. The simulation results show that the TDC can balance the performance of resolution, power consumption and dynamic range. The 32-level delay chain is used for the first-stage TDC with a quantization accuracy of 53. 8ps, and a 15-level delay chain with a quantization accuracy of 6. 2ps adopted in the second stage TDC. Under the condition that the reference frequency is 100MHz and its core chip size is $0.0431 mm^{2}$.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 1","pages":"189-192"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89467656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-22DOI: 10.1109/ICICM54364.2021.9660258
Rengang Li, Tuo Li, Kai Liu, Hongtao Man, Xiaofeng Zou, Changhong Wang
With the continuous progress of semiconductor technology, integrated circuits (ICs) have been applied to various electronic devices, such as computers, mobile phones, industrial controllers and so on. System on chip (SoC) is a special IC chip with system architecture, generally including computing logic, acceleration logic, and peripheral units. It has the advantages of small size, low power consumption, and high flexibility, and has been widely used. In the SoC chip design process, logical timing is usually very tight, which will lead to great difficulties in the logic synthesis stage. In general, the conventional synthesis method will manually increase the proportion of path groups, low voltage threshold (LVT) cells, ultra-low voltage threshold (ULVT) cells to improve timing performance, but its timing closure is slow, which will prolong the whole SoC chip design cycle. In order to improve the convergence speed of the SoC chip logic synthesis, this paper proposes a progressive automatic logic synthesis (PALS) method, which adopts progressive form to add path groups, insert LVT and ULVT cells, and performs iteration automatically. In this method, the iterative optimization constraints have the advantages of gradual progression and comprehensive coverage, which improves the convergence speed of logic synthesis effectively. In addition, ARM CortexA7 is synthesized using PALS method, and the experimental results show that the timing convergence time of the PALS method proposed in this paper is reduced by 12% compared with the conventional method, proving the superiority of the PALS method.
{"title":"A Progressive Automatic Logic Synthesis Method for Timing-Limited SoC Design","authors":"Rengang Li, Tuo Li, Kai Liu, Hongtao Man, Xiaofeng Zou, Changhong Wang","doi":"10.1109/ICICM54364.2021.9660258","DOIUrl":"https://doi.org/10.1109/ICICM54364.2021.9660258","url":null,"abstract":"With the continuous progress of semiconductor technology, integrated circuits (ICs) have been applied to various electronic devices, such as computers, mobile phones, industrial controllers and so on. System on chip (SoC) is a special IC chip with system architecture, generally including computing logic, acceleration logic, and peripheral units. It has the advantages of small size, low power consumption, and high flexibility, and has been widely used. In the SoC chip design process, logical timing is usually very tight, which will lead to great difficulties in the logic synthesis stage. In general, the conventional synthesis method will manually increase the proportion of path groups, low voltage threshold (LVT) cells, ultra-low voltage threshold (ULVT) cells to improve timing performance, but its timing closure is slow, which will prolong the whole SoC chip design cycle. In order to improve the convergence speed of the SoC chip logic synthesis, this paper proposes a progressive automatic logic synthesis (PALS) method, which adopts progressive form to add path groups, insert LVT and ULVT cells, and performs iteration automatically. In this method, the iterative optimization constraints have the advantages of gradual progression and comprehensive coverage, which improves the convergence speed of logic synthesis effectively. In addition, ARM CortexA7 is synthesized using PALS method, and the experimental results show that the timing convergence time of the PALS method proposed in this paper is reduced by 12% compared with the conventional method, proving the superiority of the PALS method.","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"11 1","pages":"227-231"},"PeriodicalIF":0.0,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90323454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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