H. Theuss, C. Geissler, Franz-Xaver Muehlbauer, Claus von Waechter, T. Kilger, J. Wagner, T. Fischer, U. Bartl, Stephan Helbig, A. Sigl, D. Maier, B. Goller, Matthias Vobl, M. Herrmann, J. Lodermeyer, U. Krumbein, A. Dehé
This work presents a fully functional miniaturized MEMS microphone demonstrator assembled within a modified Fan Out Wafer Level Package (FOWLP) process chain. Core of the development is the adaption of the FOWLP-process to MEMS-microphones, which have not yet been fully processed in the wafer fab. Instead, these microphone chips contain non-released membranes making them sufficiently robust to withstand backend processes, such as laminating and molding. The membrane release itself is performed on the reconstituted mold-wafer and postponed to a later process step. Mechanical stress effects induced by the package onto the MEMS are limited to a minimum by the implementation of stress decoupling suspension structures on the MEMS die.
{"title":"A MEMS Microphone in a FOWLP","authors":"H. Theuss, C. Geissler, Franz-Xaver Muehlbauer, Claus von Waechter, T. Kilger, J. Wagner, T. Fischer, U. Bartl, Stephan Helbig, A. Sigl, D. Maier, B. Goller, Matthias Vobl, M. Herrmann, J. Lodermeyer, U. Krumbein, A. Dehé","doi":"10.1109/ECTC.2019.00134","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00134","url":null,"abstract":"This work presents a fully functional miniaturized MEMS microphone demonstrator assembled within a modified Fan Out Wafer Level Package (FOWLP) process chain. Core of the development is the adaption of the FOWLP-process to MEMS-microphones, which have not yet been fully processed in the wafer fab. Instead, these microphone chips contain non-released membranes making them sufficiently robust to withstand backend processes, such as laminating and molding. The membrane release itself is performed on the reconstituted mold-wafer and postponed to a later process step. Mechanical stress effects induced by the package onto the MEMS are limited to a minimum by the implementation of stress decoupling suspension structures on the MEMS die.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"110 1","pages":"855-860"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77454261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The recent development of electronic materials that can maintain electrical performance while undergoing large applied strains have demonstrated potential for use in a new breed of electronic systems. The rapid development of these electronic systems that are flexible, stretchable, and/or wearable necessitates the concurrent development of robust mechanical and electrical test methods to improve their design and reliability. In this paper, one such mechanical test method is discussed in which a stretchable electronic test coupon is mounted onto an inflatable bladder of known geometry to induce multiaxial strains, while in-situ 4-point resistance measurement is employed to assess the device's performance and electromechanical integrity. The material combination of a stretchable screen-printed silver ink cured onto a thermoplastic polyurethane (TPU) substrate is studied given the proclivity for the use of TPU in wearable devices. A dome-shaped bladder configuration is employed in this work to study the performance of printed conductors under biaxial stretching. Various monotonic and cyclic loading regimes are employed to characterize the fatigue behavior and maximum use conditions of the samples. Volume of water displaced into the bladder during inflation is measured and correlated to the induced multiaxial strains on the mounted devices using 3D digital image correlation. Relationships between resistance and applied multiaxial strains are presented. Experimental results are compared with literature, and plausible extensions of the test method including direct printing on the bladder material are discussed.
{"title":"Bladder Inflation Stretch Test Method for Reliability Characterization of Wearable Electronics","authors":"Benjamin G. Stewart, S. Sitaraman","doi":"10.1109/ECTC.2019.00065","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00065","url":null,"abstract":"The recent development of electronic materials that can maintain electrical performance while undergoing large applied strains have demonstrated potential for use in a new breed of electronic systems. The rapid development of these electronic systems that are flexible, stretchable, and/or wearable necessitates the concurrent development of robust mechanical and electrical test methods to improve their design and reliability. In this paper, one such mechanical test method is discussed in which a stretchable electronic test coupon is mounted onto an inflatable bladder of known geometry to induce multiaxial strains, while in-situ 4-point resistance measurement is employed to assess the device's performance and electromechanical integrity. The material combination of a stretchable screen-printed silver ink cured onto a thermoplastic polyurethane (TPU) substrate is studied given the proclivity for the use of TPU in wearable devices. A dome-shaped bladder configuration is employed in this work to study the performance of printed conductors under biaxial stretching. Various monotonic and cyclic loading regimes are employed to characterize the fatigue behavior and maximum use conditions of the samples. Volume of water displaced into the bladder during inflation is measured and correlated to the induced multiaxial strains on the mounted devices using 3D digital image correlation. Relationships between resistance and applied multiaxial strains are presented. Experimental results are compared with literature, and plausible extensions of the test method including direct printing on the bladder material are discussed.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"31 2 1","pages":"382-391"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77077626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Liu, Boris Vaisband, A. Hanna, Yandong Luo, Zhe Wan, S. Iyer
At UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we have been developing a fine pitch heterogeneous wafer-scale platform with a single level of hierarchy called the silicon interconnect fabric (Si-IF). The Si-IF is a platform for heterogeneous integration of different bare dies at fine pitch (2 to 10 µm) and close proximity (<100 µm die spacing). The Si-IF platform can accommodate an entire 50 kW data center on a single 300 mm diameter wafer. Power delivery and heat extraction are fundamental challenges. To minimize the overhead of power conversion, current at mission (point-of-load) voltage is planned to be delivered directly to the assembly; this requires a uniform delivery of tens of kilo-amperes. Our approach is to deliver the current from the back of the Si-IF, using cooled Cu fins and through wafer vias (TWVs), to the front side of the wafer, where the dies are assembled facedown. TWVs are a key component of this power delivery system and are required to penetrate through the entire thickness of the Si-IF (500 - 700 µm). A process for fabrication of large-sized (100 µm diameter) TWVs for the Si-IF is described in this paper. The TWVs are etched in 500 µm Si wafer (aspect ratio of 1:5) and are designed to enable back-side power delivery to the integrated system. Each TWV exhibits a resistance of 1.1 mΩ with an extracted resistivity of 1.73⋅10^-8 Ωm. The scale and performance of these large-sized TWVs supports high current density for power delivery applications.
{"title":"Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric","authors":"M. Liu, Boris Vaisband, A. Hanna, Yandong Luo, Zhe Wan, S. Iyer","doi":"10.1109/ECTC.2019.00093","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00093","url":null,"abstract":"At UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we have been developing a fine pitch heterogeneous wafer-scale platform with a single level of hierarchy called the silicon interconnect fabric (Si-IF). The Si-IF is a platform for heterogeneous integration of different bare dies at fine pitch (2 to 10 µm) and close proximity (<100 µm die spacing). The Si-IF platform can accommodate an entire 50 kW data center on a single 300 mm diameter wafer. Power delivery and heat extraction are fundamental challenges. To minimize the overhead of power conversion, current at mission (point-of-load) voltage is planned to be delivered directly to the assembly; this requires a uniform delivery of tens of kilo-amperes. Our approach is to deliver the current from the back of the Si-IF, using cooled Cu fins and through wafer vias (TWVs), to the front side of the wafer, where the dies are assembled facedown. TWVs are a key component of this power delivery system and are required to penetrate through the entire thickness of the Si-IF (500 - 700 µm). A process for fabrication of large-sized (100 µm diameter) TWVs for the Si-IF is described in this paper. The TWVs are etched in 500 µm Si wafer (aspect ratio of 1:5) and are designed to enable back-side power delivery to the integrated system. Each TWV exhibits a resistance of 1.1 mΩ with an extracted resistivity of 1.73⋅10^-8 Ωm. The scale and performance of these large-sized TWVs supports high current density for power delivery applications.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"579-586"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75679857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xin Wang, Qian Wang, Jian Cai, Changmin Song, Yang Hu, Yang Zhao, Yu Pei
Cu and unoxidized graphene composite films were prepared by electroplating under room temperature. Graphene was added to the electrolyte of Cu to form composite materials to improve the performance of Cu for interconnection. Composite electrolyte containing high concentration of graphene (up to 0.5 g/L) was prepared by adding CTAB as surfactant. And ultrasound was also used to increase dispersion degree and reduce graphene agglomeration in electrolyte. Average coefficient of thermal expansion (CTE) of the composite films determined by thermo-mechanical analysis (TMA) shows a decrease from 17.3 ppm/K to 14.2 ppm/K from 260 K to 320 K, which reduce CTE by 18 % compared with Cu. CTE of the composite materials can be reduced to 10 ppm/K at 243 K, which is only 60 % of CTE of Cu. The thermal conductivity of the composite materials measured by phase sensitive transient thermo-reflectance (PSTTR) technique shows an improvement from 385 W/m.K to 468 W/m.K. CTE and thermal conductivity of the composite materials both decrease with the increase of current density. And they also both increase with the increase of graphene concentration. The composite materials also show good mechanical properties. The average hardness is 2.5 GPa, which is about 2 times of Cu. And the average elastic modulus is 145 GPa, which is 38 % higher than that of Cu. The resistivity of the composite materials is basically equivalent to that of pure Cu. Result of the experiment proved that the composite materials have better performance under low temperature conditions. The improvement of material properties makes composite materials have good application prospects for 3D interconnection in the near future.
{"title":"Preparation and Characterization of Electroplated Cu/Graphene Composite","authors":"Xin Wang, Qian Wang, Jian Cai, Changmin Song, Yang Hu, Yang Zhao, Yu Pei","doi":"10.1109/ECTC.2019.00-12","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-12","url":null,"abstract":"Cu and unoxidized graphene composite films were prepared by electroplating under room temperature. Graphene was added to the electrolyte of Cu to form composite materials to improve the performance of Cu for interconnection. Composite electrolyte containing high concentration of graphene (up to 0.5 g/L) was prepared by adding CTAB as surfactant. And ultrasound was also used to increase dispersion degree and reduce graphene agglomeration in electrolyte. Average coefficient of thermal expansion (CTE) of the composite films determined by thermo-mechanical analysis (TMA) shows a decrease from 17.3 ppm/K to 14.2 ppm/K from 260 K to 320 K, which reduce CTE by 18 % compared with Cu. CTE of the composite materials can be reduced to 10 ppm/K at 243 K, which is only 60 % of CTE of Cu. The thermal conductivity of the composite materials measured by phase sensitive transient thermo-reflectance (PSTTR) technique shows an improvement from 385 W/m.K to 468 W/m.K. CTE and thermal conductivity of the composite materials both decrease with the increase of current density. And they also both increase with the increase of graphene concentration. The composite materials also show good mechanical properties. The average hardness is 2.5 GPa, which is about 2 times of Cu. And the average elastic modulus is 145 GPa, which is 38 % higher than that of Cu. The resistivity of the composite materials is basically equivalent to that of pure Cu. Result of the experiment proved that the composite materials have better performance under low temperature conditions. The improvement of material properties makes composite materials have good application prospects for 3D interconnection in the near future.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"2234-2239"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90657814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Taejoo Hwang, D. Oh, Jaechoon Kim, Euseok Song, Taehun Kim, Kilsoo Kim, Joungphil Lee, Taehwan Kim
As information technologies evolve with the 4th industry revolution, such as artificial intelligence and 5G mobile communication, much more computing power and data bandwidth are required for both mobile and server systems. However, one-dimensional thermal packaging solutions such as a heat spreader or high conductive materials are not sufficient to solve the heat dissipation problems for the system-in-packages. In this research, a novel thermal dissipation technology based on two-dimensional heat flow was studied for the 5G high thermal power system-in-package modems and high performance computing logics. By applying a high thermal conductive material such as silver paste to conventional epoxy mold compound structures and creating direct high thermal dissipation paths from a bottom logic die to the heat spreader, it can bypass memory die that is more sensitive to the temperature rise than the logic die. The thermal performance of this novel technology was demonstrated using actual 5G modem system-in-packages comprised of a modem and two LPDDR4x dice. In conclusion, two-dimensional heat dissipation technique using thermal chimney is effective to reduce thermal crosstalk between top memory and bottom logic dice. Consequently, the overall system thermal performance was able to be improved by reducing heat flow through top memory dice.
{"title":"The Thermal Dissipation Characteristics of The Novel System-In-Package Technology (ICE-SiP) for Mobile and 3D High-end Packages","authors":"Taejoo Hwang, D. Oh, Jaechoon Kim, Euseok Song, Taehun Kim, Kilsoo Kim, Joungphil Lee, Taehwan Kim","doi":"10.1109/ECTC.2019.00098","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00098","url":null,"abstract":"As information technologies evolve with the 4th industry revolution, such as artificial intelligence and 5G mobile communication, much more computing power and data bandwidth are required for both mobile and server systems. However, one-dimensional thermal packaging solutions such as a heat spreader or high conductive materials are not sufficient to solve the heat dissipation problems for the system-in-packages. In this research, a novel thermal dissipation technology based on two-dimensional heat flow was studied for the 5G high thermal power system-in-package modems and high performance computing logics. By applying a high thermal conductive material such as silver paste to conventional epoxy mold compound structures and creating direct high thermal dissipation paths from a bottom logic die to the heat spreader, it can bypass memory die that is more sensitive to the temperature rise than the logic die. The thermal performance of this novel technology was demonstrated using actual 5G modem system-in-packages comprised of a modem and two LPDDR4x dice. In conclusion, two-dimensional heat dissipation technique using thermal chimney is effective to reduce thermal crosstalk between top memory and bottom logic dice. Consequently, the overall system thermal performance was able to be improved by reducing heat flow through top memory dice.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"614-619"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87548914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Coudrain, J. Charbonnier, A. Garnier, P. Vivet, R. Vélard, A. Vinci, F. Ponthenier, A. Farcy, R. Segaud, P. Chausse, L. Arnaud, D. Lattard, E. Guthmuller, G. Romano, A. Gueugnot, F. Berger, J. Beltritti, T. Mourier, M. Gottardi, S. Minoret, C. Ribiére, G. Romero, Pierre-Emile Philip, Y. Exbrayat, D. Scevola, D. Campos, M. Argoud, N. Allouti, R. Eleouet, César Fuguet Tortolero, C. Aumont, D. Dutoit, Corinne Legalland, J. Michailos, S. Chéramy, G. Simon
We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.
{"title":"Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures","authors":"P. Coudrain, J. Charbonnier, A. Garnier, P. Vivet, R. Vélard, A. Vinci, F. Ponthenier, A. Farcy, R. Segaud, P. Chausse, L. Arnaud, D. Lattard, E. Guthmuller, G. Romano, A. Gueugnot, F. Berger, J. Beltritti, T. Mourier, M. Gottardi, S. Minoret, C. Ribiére, G. Romero, Pierre-Emile Philip, Y. Exbrayat, D. Scevola, D. Campos, M. Argoud, N. Allouti, R. Eleouet, César Fuguet Tortolero, C. Aumont, D. Dutoit, Corinne Legalland, J. Michailos, S. Chéramy, G. Simon","doi":"10.1109/ECTC.2019.00092","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00092","url":null,"abstract":"We report the first successful technology integration of chiplets on an active silicon interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are discussed. Built up technology is presented and focused on 3D interconnects process and characterization. 3D packaging is presented up to the successful structural test and characterization of the demonstrator.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"569-578"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82807709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nicholas Kam, M. Hook, Celal Con, K. Karim, M. Mayer
Wirebonding performed at elevated temperatures is the standard interconnect process for integrated circuits, typically with the use of low-cost copper bonding wire. However, for specific applications it is necessary for wire bonds to be reliably joined at room-temperature. This paper details the development of a room-temperature ball bonding process using a 2-stage optimization method. The first stage optimizes ball geometry by applying a 32 design of experiment to bonding parameters impact force (IF) and electric flame-off (EFO) current. In the second stage bond shear strength is optimized by stepwise increase in ultrasonic amplitude. Target ball bond values were attained at optimized parameters: IF of 1331 mN, EFO current of 59.9 mA, and an ultrasonic amplitude of 26.46 US%. Pad lift during bonding was observed at excessive ultrasonic amplitudes above 40 US%, as determined by optical images at the bond interface. Bonding parameters at room-temperature (23°C) were increased when compared to a high temperature process (175°C) to account for reduced thermal energy. For the same geometry at room-temperature a 7 % increase to impact force was required. EFO current levels remained relatively constant between the two bonding temperatures. For the same shear strength at room-temperature a 18 % increase in ultrasound amplitude was required. The confirmed average shear strength achieved via the room-temperature process was 116 MPa. Higher values are possible.
{"title":"Room-Temperature Bonding with Pd Coated Cu Wire on Al Pads: Ball Bond Optimization with 2-Stage Methodology","authors":"Nicholas Kam, M. Hook, Celal Con, K. Karim, M. Mayer","doi":"10.1109/ECTC.2019.00-14","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-14","url":null,"abstract":"Wirebonding performed at elevated temperatures is the standard interconnect process for integrated circuits, typically with the use of low-cost copper bonding wire. However, for specific applications it is necessary for wire bonds to be reliably joined at room-temperature. This paper details the development of a room-temperature ball bonding process using a 2-stage optimization method. The first stage optimizes ball geometry by applying a 32 design of experiment to bonding parameters impact force (IF) and electric flame-off (EFO) current. In the second stage bond shear strength is optimized by stepwise increase in ultrasonic amplitude. Target ball bond values were attained at optimized parameters: IF of 1331 mN, EFO current of 59.9 mA, and an ultrasonic amplitude of 26.46 US%. Pad lift during bonding was observed at excessive ultrasonic amplitudes above 40 US%, as determined by optical images at the bond interface. Bonding parameters at room-temperature (23°C) were increased when compared to a high temperature process (175°C) to account for reduced thermal energy. For the same geometry at room-temperature a 7 % increase to impact force was required. EFO current levels remained relatively constant between the two bonding temperatures. For the same shear strength at room-temperature a 18 % increase in ultrasound amplitude was required. The confirmed average shear strength achieved via the room-temperature process was 116 MPa. Higher values are possible.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"4 1","pages":"2219-2224"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82629657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ramón A. Sosa, K. Mohan, L. Nguyen, R. Tummala, A. Antoniou, V. Smet
Off-chip interconnection pitch scaling has been aggressively driven over the last several decades by the continuous need for higher bandwidth and computing power in smaller form factors in emerging high-performance computing systems. It is expected to reach below 10µm I/O pitch in the near future, beyond the fundamental limits of traditional solder-based interconnection technologies. While the Cu pillar with solder caps technology remains attractive in chip-to-substrate (C2S) applications as it can accommodate substrate and chip non-coplanarities during assembly through melting of the solder, all-Cu interconnections are now pursued as the next interconnection node for their pitch and performance scalability. However, direct Cu-Cu bonding faces several key challenges that have hindered large-scale adoption in C2S, including its relatively high elastic modulus, giving low compliance in assembly. To address this challenge, a novel interconnection technology - Cu pillar with nanocopper caps - is proposed where a solid-state sub-20 GPa modulus nanoporous Cu cap is introduced to replace the solder cap and retain solder-like compliance in assembly, while achieving bulk-like properties through densification in low-temperature sintering. This paper presents the design of this new interconnection system, the developed wafer bumping process, compatible with current industry infrastructures, and a first assembly demonstration where a seamless interface was achieved.
{"title":"Cu Pillar with Nanocopper Caps: The Next Interconnection Node Beyond Traditional Cu Pillar","authors":"Ramón A. Sosa, K. Mohan, L. Nguyen, R. Tummala, A. Antoniou, V. Smet","doi":"10.1109/ECTC.2019.00104","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00104","url":null,"abstract":"Off-chip interconnection pitch scaling has been aggressively driven over the last several decades by the continuous need for higher bandwidth and computing power in smaller form factors in emerging high-performance computing systems. It is expected to reach below 10µm I/O pitch in the near future, beyond the fundamental limits of traditional solder-based interconnection technologies. While the Cu pillar with solder caps technology remains attractive in chip-to-substrate (C2S) applications as it can accommodate substrate and chip non-coplanarities during assembly through melting of the solder, all-Cu interconnections are now pursued as the next interconnection node for their pitch and performance scalability. However, direct Cu-Cu bonding faces several key challenges that have hindered large-scale adoption in C2S, including its relatively high elastic modulus, giving low compliance in assembly. To address this challenge, a novel interconnection technology - Cu pillar with nanocopper caps - is proposed where a solid-state sub-20 GPa modulus nanoporous Cu cap is introduced to replace the solder cap and retain solder-like compliance in assembly, while achieving bulk-like properties through densification in low-temperature sintering. This paper presents the design of this new interconnection system, the developed wafer bumping process, compatible with current industry infrastructures, and a first assembly demonstration where a seamless interface was achieved.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"655-660"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88413418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Sakuma, B. Webb, R. Narayanan, Avner Abrami, Jeff Rogers, J. Knickerbocker, S. Heisig
This paper describes the sensor, electronics, software, modeling, and characterization of a fingernail-mounted RF-connected wearable strain sensor system that measures nail deformation from finger movement. Applications to health monitoring and human computer interfaces in homes, hospitals, and workplaces are discussed. The mechanical deformation of a fingertip pressed or drawn against a plate is demonstrated using a three-dimensional finite-element linear-elastic model to predict the signal level, optimum sensor locations and the type and location of deformation expected for different finger motions. The 3D finite-element linear elastic model is derived from X-ray images of a human finger but generalized and parameterized to allow new models to be created by scaling internal and external parameters such as skin thickness and nail and finger shape to predict sensor system performance for a more general human population. Our analysis finds that a single sensor mounted in the center of the nail will respond to typical grip pressures on the fingertip with readily detectible strain amplitudes but that a multi-sensor array will be sensitive to more general haptic phenomena such as the direction and magnitude of frictional loads and loading of the distal phalangeal joint. It is shown that depending on finger use and loading the nail exhibits shifts in direction, location and sign of strain over the fingernail surface. Measurement data from a simple multi-sensor array is shown to be useful in distinguishing between load conditions, however additional sensors are required for full determination.
{"title":"A Wearable Fingernail Deformation Sensing System and Three-Dimensional Finite Element Model of Fingertip","authors":"K. Sakuma, B. Webb, R. Narayanan, Avner Abrami, Jeff Rogers, J. Knickerbocker, S. Heisig","doi":"10.1109/ECTC.2019.00047","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00047","url":null,"abstract":"This paper describes the sensor, electronics, software, modeling, and characterization of a fingernail-mounted RF-connected wearable strain sensor system that measures nail deformation from finger movement. Applications to health monitoring and human computer interfaces in homes, hospitals, and workplaces are discussed. The mechanical deformation of a fingertip pressed or drawn against a plate is demonstrated using a three-dimensional finite-element linear-elastic model to predict the signal level, optimum sensor locations and the type and location of deformation expected for different finger motions. The 3D finite-element linear elastic model is derived from X-ray images of a human finger but generalized and parameterized to allow new models to be created by scaling internal and external parameters such as skin thickness and nail and finger shape to predict sensor system performance for a more general human population. Our analysis finds that a single sensor mounted in the center of the nail will respond to typical grip pressures on the fingertip with readily detectible strain amplitudes but that a multi-sensor array will be sensitive to more general haptic phenomena such as the direction and magnitude of frictional loads and loading of the distal phalangeal joint. It is shown that depending on finger use and loading the nail exhibits shifts in direction, location and sign of strain over the fingernail surface. Measurement data from a simple multi-sensor array is shown to be useful in distinguishing between load conditions, however additional sensors are required for full determination.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"270-276"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80043336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes solder joint reliability studies for DDR memories using single side and double side mount modules in the application of consumer and automotive fields. The types of DDRs include LPDDR4 and GDDR5. The components are from well-known memory manufacturers. Both experimental work and numerical simulation are employed to understand the reliability and failure mechanisms. It is found the reliability of DDRs changes with different DDR types as well as suppliers. LPDDR4 has much lower reliability as compared to that of GDDR5. The reason is the low ball profile which has increased the thermal stress for LPDDR4. However, the most critical factor is the double side mount vs. single side mount configuration. Both experimental and FEA results show corner fill may be a better choice in handling both mechanical and thermal stresses. To enhance the solder joint reliability, one effective way is to employ corner fill, edge bond or underfill. However, in order to get better reliability, corner fill and underfill are normally recommended.
{"title":"Solder Joint Reliability of Double-Side Mounted DDR Modules for Consumer and Automotive Applications","authors":"Dongji Xie, Joe Hai, Zhongming Wu, M. Economou","doi":"10.1109/ECTC.2019.00080","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00080","url":null,"abstract":"This paper describes solder joint reliability studies for DDR memories using single side and double side mount modules in the application of consumer and automotive fields. The types of DDRs include LPDDR4 and GDDR5. The components are from well-known memory manufacturers. Both experimental work and numerical simulation are employed to understand the reliability and failure mechanisms. It is found the reliability of DDRs changes with different DDR types as well as suppliers. LPDDR4 has much lower reliability as compared to that of GDDR5. The reason is the low ball profile which has increased the thermal stress for LPDDR4. However, the most critical factor is the double side mount vs. single side mount configuration. Both experimental and FEA results show corner fill may be a better choice in handling both mechanical and thermal stresses. To enhance the solder joint reliability, one effective way is to employ corner fill, edge bond or underfill. However, in order to get better reliability, corner fill and underfill are normally recommended.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"77 1","pages":"486-492"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80219670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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