A. Ghannam, Niek van Haare, Julian Bravin, Elisabeth Brandl, Birgit Brandstätter, H. Klingler, B. Auer, P. Meunier, S. Kersjes
In this work, a new wafer-level 3D packaging technology is developed to enable integration of an ultra-thin QFN-like (quad-flat no-leads) 3D package that targets both effective electrical and thermal properties and a thickness smaller than 200 µm. The proposed architecture allows 3D interconnection of stacked staggered dies and integration of compact, high-performance 3D integrated passive devices inside the package for added functionality and electrical performance. The developed technology consists of using debonding from a temporary carrier, Cu 2D-RDL (Redistribution Layer), accurate thin die pick & place, 3D-RDL and overmolding processes to integrate a QFN-like 3D package. Interconnection between die and package I/O is achieved using conformal 3D-RDL, thus without wire-bond, flip-chip or TSV.
{"title":"Ultra-Thin QFN-Like 3D Package with 3D Integrated Passive Devices","authors":"A. Ghannam, Niek van Haare, Julian Bravin, Elisabeth Brandl, Birgit Brandstätter, H. Klingler, B. Auer, P. Meunier, S. Kersjes","doi":"10.1109/ECTC.2019.00276","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00276","url":null,"abstract":"In this work, a new wafer-level 3D packaging technology is developed to enable integration of an ultra-thin QFN-like (quad-flat no-leads) 3D package that targets both effective electrical and thermal properties and a thickness smaller than 200 µm. The proposed architecture allows 3D interconnection of stacked staggered dies and integration of compact, high-performance 3D integrated passive devices inside the package for added functionality and electrical performance. The developed technology consists of using debonding from a temporary carrier, Cu 2D-RDL (Redistribution Layer), accurate thin die pick & place, 3D-RDL and overmolding processes to integrate a QFN-like 3D package. Interconnection between die and package I/O is achieved using conformal 3D-RDL, thus without wire-bond, flip-chip or TSV.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"259 1","pages":"1789-1795"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77105110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Arad Azizi, Matthias A. Daeumer, Jacob C. Simmons, B. Sammakia, B. Murray, Scott N. Schiffres
We previously demonstrated how the Sn3Ag4Ti alloy can robustly bond onto silicon via selective laser melting (SLM). By employing this technology, thermal management devices (e.g., micro-channels, vapor chamber evaporators, heat pipes) can be directly printed onto the electronic package (silicon die) without using thermal interface materials. Under immersion two-phase cooling (pool boiling), we compare the performance of three chip cooling methods (conventional heat sink, bare silicon die and additively manufactured metal micro-fins) under high heat flux conditions (100 W/cm^2). Heat transfer simulations show a significant reduction in the chip temperature for the silicon micro-fins. Reduction of the chip operating temperature or increase in clock speed are some of the advantages of this technology, which results from the elimination of thermal interface materials in the electronic package. Performance and reliability aspects of this technology are discussed through experiments and computational models.
{"title":"Additive Laser Metal Deposition Onto Silicon for Enhanced Microelectronics Cooling","authors":"Arad Azizi, Matthias A. Daeumer, Jacob C. Simmons, B. Sammakia, B. Murray, Scott N. Schiffres","doi":"10.1109/ECTC.2019.00302","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00302","url":null,"abstract":"We previously demonstrated how the Sn3Ag4Ti alloy can robustly bond onto silicon via selective laser melting (SLM). By employing this technology, thermal management devices (e.g., micro-channels, vapor chamber evaporators, heat pipes) can be directly printed onto the electronic package (silicon die) without using thermal interface materials. Under immersion two-phase cooling (pool boiling), we compare the performance of three chip cooling methods (conventional heat sink, bare silicon die and additively manufactured metal micro-fins) under high heat flux conditions (100 W/cm^2). Heat transfer simulations show a significant reduction in the chip temperature for the silicon micro-fins. Reduction of the chip operating temperature or increase in clock speed are some of the advantages of this technology, which results from the elimination of thermal interface materials in the electronic package. Performance and reliability aspects of this technology are discussed through experiments and computational models.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"1970-1976"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81472405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. C. Durgun, Z. Qian, K. Aygun, R. Mahajan, T. Hoang, Sergey Y. Shumarayev
Heterogeneous integration facilitates faster design cycles with optimal functional IP module and silicon node combinations, but requires ultra-high bandwidth for the die-to-die communications. Fine pitch interconnects can meet such high bandwidth demands with simpler circuits, lower power and less latency. Hence, it is of utmost importance to understand the performance of these interconnects at different speeds and channel lengths. This paper focuses on a parametric study over the basic design parameters of a generic fine pitch interconnect, to explore the electrical performance limits. As a result of this study, practical guidelines are provided for the die-to-die channel design.
{"title":"Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration","authors":"A. C. Durgun, Z. Qian, K. Aygun, R. Mahajan, T. Hoang, Sergey Y. Shumarayev","doi":"10.1109/ECTC.2019.00106","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00106","url":null,"abstract":"Heterogeneous integration facilitates faster design cycles with optimal functional IP module and silicon node combinations, but requires ultra-high bandwidth for the die-to-die communications. Fine pitch interconnects can meet such high bandwidth demands with simpler circuits, lower power and less latency. Hence, it is of utmost importance to understand the performance of these interconnects at different speeds and channel lengths. This paper focuses on a parametric study over the basic design parameters of a generic fine pitch interconnect, to explore the electrical performance limits. As a result of this study, practical guidelines are provided for the die-to-die channel design.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"29 1","pages":"667-673"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88511397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sang Yong Park, Juyeong Nam, Ji Ni Shim, Jun Kyu Lee, Yongtae Kwon, Chang Woo Lee, Jong Heon Kim, N. Kim
In this paper, the development of a new optical chip in board (CiB) package adapting Fan-out technology that offers thermal, electrical and thin structure benefit was reported. Optical CiB package contain 4 optical die and is made smaller and thinner than market with the redistribution layer technology of FO-WLP. The key advantages such as high production yield, low cost and simple process steps surpass the conventional optical packages that depends on high precision alignment but always difficult to achieve good performance. Through finally demonstrated that communication is possible at the target speed of 10Gbps/Ch through actual measurement. In this paper describes the structural features of Embedded optical CiB package with integration of nepes'Fan-out technology.
{"title":"CiB(Chip in Board) Optical Engine Module Using Advanced Fan-Out Package Technology","authors":"Sang Yong Park, Juyeong Nam, Ji Ni Shim, Jun Kyu Lee, Yongtae Kwon, Chang Woo Lee, Jong Heon Kim, N. Kim","doi":"10.1109/ECTC.2019.00091","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00091","url":null,"abstract":"In this paper, the development of a new optical chip in board (CiB) package adapting Fan-out technology that offers thermal, electrical and thin structure benefit was reported. Optical CiB package contain 4 optical die and is made smaller and thinner than market with the redistribution layer technology of FO-WLP. The key advantages such as high production yield, low cost and simple process steps surpass the conventional optical packages that depends on high precision alignment but always difficult to achieve good performance. Through finally demonstrated that communication is possible at the target speed of 10Gbps/Ch through actual measurement. In this paper describes the structural features of Embedded optical CiB package with integration of nepes'Fan-out technology.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"47 1","pages":"563-568"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85763568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
WLCSP packaging is wildly use in portable electronic products such as phone, watch, and intelligent bracelet. The advantages of WLCSP package are parasitic inductance minimized, reduced package size, and enhanced thermal conduction characteristics. To enable these benefits regardless of the die's functional complexity, we adopted Cu with ELK (extreme Low-K) material as inter-metal-dielectric native to advanced silicon fabrication technology, and WLCSP packing with large die size, thus fulfilling requirements for high speed & low power consumption. To investigate wafer WLCSP board level reliability performance is essential and critical for successful product launch and preventing field return risk. Test vehicles were used with combinations in PBO2 opening, PCB thickness, and PCB metal gradient, to understand stress on ELK behavior and potential impact on board level reliability. A quick stress test methodology using 75 cycles of -650C~1500C liquid-to-liquid thermal shock (LLTS), showing ~acceleration factor of 1.9 compared with TCB stress, was validated and used for shortening experiment cycle time. A 6x6 mm2 test vehicle was used for different WLCSP package PBO2 opening, PCB thickness and PCB metal design to assess board level reliability impact. LLTS 75cycles result showed larger PBO2 opening will get die edge ELK delamination defects. Higher PCB metal gradient board (more than 50%) & more thick (1mm) also got higher fail rate. For better WLCSP board level reliability structure, smaller WLCSP package PBO2 opening, thinner PCB thickness and uniform PCB metal distribution are recommended.
{"title":"WLCSP Package and PCB Design for Board Level Reliability","authors":"J. Chiu, K.C. Chang, S. Hsu, P. Tsao, M. Lii","doi":"10.1109/ECTC.2019.00121","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00121","url":null,"abstract":"WLCSP packaging is wildly use in portable electronic products such as phone, watch, and intelligent bracelet. The advantages of WLCSP package are parasitic inductance minimized, reduced package size, and enhanced thermal conduction characteristics. To enable these benefits regardless of the die's functional complexity, we adopted Cu with ELK (extreme Low-K) material as inter-metal-dielectric native to advanced silicon fabrication technology, and WLCSP packing with large die size, thus fulfilling requirements for high speed & low power consumption. To investigate wafer WLCSP board level reliability performance is essential and critical for successful product launch and preventing field return risk. Test vehicles were used with combinations in PBO2 opening, PCB thickness, and PCB metal gradient, to understand stress on ELK behavior and potential impact on board level reliability. A quick stress test methodology using 75 cycles of -650C~1500C liquid-to-liquid thermal shock (LLTS), showing ~acceleration factor of 1.9 compared with TCB stress, was validated and used for shortening experiment cycle time. A 6x6 mm2 test vehicle was used for different WLCSP package PBO2 opening, PCB thickness and PCB metal design to assess board level reliability impact. LLTS 75cycles result showed larger PBO2 opening will get die edge ELK delamination defects. Higher PCB metal gradient board (more than 50%) & more thick (1mm) also got higher fail rate. For better WLCSP board level reliability structure, smaller WLCSP package PBO2 opening, thinner PCB thickness and uniform PCB metal distribution are recommended.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"763-767"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75505684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sawako Shimada, K. Okada, Tomoya Kudo, Chiho Ueta, Yuya Suzuki
This paper describes material analysis and material design of high reliability solder resist (SR) with excellent performance for high density packaging. There is growing demand for higher speed and higher data bandwidth signal transmission for many applications, such as 5G communication, artificial intelligence (AI), and advanced driver-assistance systems (ADAS). Such applications require high density and high performance IC packaging with fine Cu wiring and high frequency signal transmission. Solder resist materials for such packaging need to satisfy many special properties, such as high resistance to Cu electrochemical migration, strong adhesion to low profile Cu layers, and accurate photo-lithography resolution. However, development of a solder resist material that has all the excellent properties above is highly challenging, because many of these properties are trade-off. Indeed, adhesion of conventional SR to low profile Cu layer dropped more than 80% after high temperature and moisture HAST condition. Additionally, photolithography resolution below 50 μm was highly challenging due to light scattering. To overcome the trade-offs, this research began with the detail material analysis of the organic and inorganic components in SR materials. First analysis in polymer structures showed that resin with less shrinkage and less hydrolysis increased the initial adhesion, as well as adhesion after high temperature and high moisture condition. Next study on filler type and surface treatment revealed that the organic and inorganic surface treatment were effective to improve adhesion stability and resolution. This can be explained by the higher electrical affinity and less light scattering. By integrating the fundamental analyses, a new SR with excellent adhesion stability (85% of initial adhesion), high photolithography resolution below 40 μm, and excellent Cu migration resistance below 8 μm L/S.
{"title":"High Reliability Solder Resist with Strong Adhesion and High Resolution for High Density Packaging","authors":"Sawako Shimada, K. Okada, Tomoya Kudo, Chiho Ueta, Yuya Suzuki","doi":"10.1109/ECTC.2019.00159","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00159","url":null,"abstract":"This paper describes material analysis and material design of high reliability solder resist (SR) with excellent performance for high density packaging. There is growing demand for higher speed and higher data bandwidth signal transmission for many applications, such as 5G communication, artificial intelligence (AI), and advanced driver-assistance systems (ADAS). Such applications require high density and high performance IC packaging with fine Cu wiring and high frequency signal transmission. Solder resist materials for such packaging need to satisfy many special properties, such as high resistance to Cu electrochemical migration, strong adhesion to low profile Cu layers, and accurate photo-lithography resolution. However, development of a solder resist material that has all the excellent properties above is highly challenging, because many of these properties are trade-off. Indeed, adhesion of conventional SR to low profile Cu layer dropped more than 80% after high temperature and moisture HAST condition. Additionally, photolithography resolution below 50 μm was highly challenging due to light scattering. To overcome the trade-offs, this research began with the detail material analysis of the organic and inorganic components in SR materials. First analysis in polymer structures showed that resin with less shrinkage and less hydrolysis increased the initial adhesion, as well as adhesion after high temperature and high moisture condition. Next study on filler type and surface treatment revealed that the organic and inorganic surface treatment were effective to improve adhesion stability and resolution. This can be explained by the higher electrical affinity and less light scattering. By integrating the fundamental analyses, a new SR with excellent adhesion stability (85% of initial adhesion), high photolithography resolution below 40 μm, and excellent Cu migration resistance below 8 μm L/S.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"97 1","pages":"1015-1021"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75292622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The modeling of moisture diffusion plays an important role for the integrity and reliability of electronic packages. In this paper, a new normalization approach and its implementation using ANSYS finite element analysis software are presented. Such an approach can solve the diffusion problem with varying temperature and humidity. Two different options in moisture diffusion modeling provided by ANSYS are discussed. As a validation, the numerical results are compared to that using the conventional normalization approach.
{"title":"Improved Finite Element Modeling of Moisture Diffusion Considering Discontinuity at Material Interfaces in Electronic Packages","authors":"Lulu Ma, R. Joshi, Keith Keith Newman, Xuejun Fan","doi":"10.1109/ECTC.2019.00127","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00127","url":null,"abstract":"The modeling of moisture diffusion plays an important role for the integrity and reliability of electronic packages. In this paper, a new normalization approach and its implementation using ANSYS finite element analysis software are presented. Such an approach can solve the diffusion problem with varying temperature and humidity. Two different options in moisture diffusion modeling provided by ANSYS are discussed. As a validation, the numerical results are compared to that using the conventional normalization approach.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"108 1","pages":"806-810"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73702957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel shell resonator, fountain like resonator (FLR). The FLR is of doughnut shape, anchored at the outer rim to enlarge the bonding or support area. The working mode, wineglass n=2 mode, is generated by the inner rim. Finite element mechanical (FEM) simulation is utilized to analyze the influence of shell size on the resonant frequencies. The foaming process is adopted to fabricated the FLR. The frequency response is obtained by Laser Doppler Vibrometer (LDV), and the wineglass n=2 frequency of this resonator is 50.1kHz. The novel shell resonator with doughnut shape shows potential for gyroscopic application.
{"title":"Micro Fountain-Like Resonators","authors":"Jianfeng Zhang, J. Shang, Bin Luo, Zhaoxi Su","doi":"10.1109/ECTC.2019.00139","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00139","url":null,"abstract":"This paper presents a novel shell resonator, fountain like resonator (FLR). The FLR is of doughnut shape, anchored at the outer rim to enlarge the bonding or support area. The working mode, wineglass n=2 mode, is generated by the inner rim. Finite element mechanical (FEM) simulation is utilized to analyze the influence of shell size on the resonant frequencies. The foaming process is adopted to fabricated the FLR. The frequency response is obtained by Laser Doppler Vibrometer (LDV), and the wineglass n=2 frequency of this resonator is 50.1kHz. The novel shell resonator with doughnut shape shows potential for gyroscopic application.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"890-895"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74762437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Weifeng Liu, W. Uy, Alex Chan, D. Shangguan, Andy Behr, Takatoshi Abe, Fukao Tomohiro
Flexible hybrid electronics (FHE) are manufactured by combining traditional circuit board fabrication and assembly processes with emerging printed electronics technology. By integrating surface mounted electronic components with printed stretchable conductive circuits and compliant/stretchable substrates these hybrid constructions have potential to revolutionize electronic assemblies used for Internet of Things (IOT), wearable, medical, wellness, automotive and aerospace markets. By employing FHE principles, designers can create heterogeneous electronic systems with unique form factors and functionality. These devices can conform to the curves of a human body or even be applied to the surface of or molded within an irregularly shaped mechanical structure. FHEs also offer the promise of light-weight and cost-effectiveness, scalable manufacturing. The FHE industry remains in the early stages of development. A variety of design, material, assembly and reliability issues remain to be addressed. For example, the typical polymer based conductive pastes used for forming FHE circuit structures are not as conductive as the etched copper on traditional printed circuit boards (PCBs.) Additionally, most of these polymer-based conductive pastes are not readily solderable and the electrical interconnections formed with conductive adhesives in current FHE designs may not be as conductive or reliable as those formed with solder. Additionally, commercially available stretchable thermoplastic film substrates have relatively low thermal resistance and cannot withstand the current lead-free surface mount technology (SMT) reflow temperatures. This paper discusses these challenges and presents an FHE manufacturing process utilizing a stretchable thermosetting polymer substrate, a combination of both screen-printed stretchable conductive paste and etched copper structure, and the conventional SMT processes to create a functional proof of concept double-sided device integrating both active and passive components.
{"title":"Development of Flexible Hybrid Electronics Using Reflow Assembly with Stretchable Film","authors":"Weifeng Liu, W. Uy, Alex Chan, D. Shangguan, Andy Behr, Takatoshi Abe, Fukao Tomohiro","doi":"10.1109/ECTC.2019.00197","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00197","url":null,"abstract":"Flexible hybrid electronics (FHE) are manufactured by combining traditional circuit board fabrication and assembly processes with emerging printed electronics technology. By integrating surface mounted electronic components with printed stretchable conductive circuits and compliant/stretchable substrates these hybrid constructions have potential to revolutionize electronic assemblies used for Internet of Things (IOT), wearable, medical, wellness, automotive and aerospace markets. By employing FHE principles, designers can create heterogeneous electronic systems with unique form factors and functionality. These devices can conform to the curves of a human body or even be applied to the surface of or molded within an irregularly shaped mechanical structure. FHEs also offer the promise of light-weight and cost-effectiveness, scalable manufacturing. The FHE industry remains in the early stages of development. A variety of design, material, assembly and reliability issues remain to be addressed. For example, the typical polymer based conductive pastes used for forming FHE circuit structures are not as conductive as the etched copper on traditional printed circuit boards (PCBs.) Additionally, most of these polymer-based conductive pastes are not readily solderable and the electrical interconnections formed with conductive adhesives in current FHE designs may not be as conductive or reliable as those formed with solder. Additionally, commercially available stretchable thermoplastic film substrates have relatively low thermal resistance and cannot withstand the current lead-free surface mount technology (SMT) reflow temperatures. This paper discusses these challenges and presents an FHE manufacturing process utilizing a stretchable thermosetting polymer substrate, a combination of both screen-printed stretchable conductive paste and etched copper structure, and the conventional SMT processes to create a functional proof of concept double-sided device integrating both active and passive components.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"10 1","pages":"1272-1278"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78691313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Waidhas, Jan Proschwitz, Christoph Pietryga, Thomas Wagner, B. Keser
Board level reliability investigations have been performed on 36 mm² wafer level packages (WLP) with a 0.3 mm ball pitch. Three different solder ball alloys were included in the temperature cycling, thermal shock and mechanical shock test. In addition to daisy chain test vehicles to address the solder joint reliability, 28 nm die packaged with WLP were included in the assessment to check the stress impact on extreme low K dielectric (ELK) in the die back-end-of-line (BEOL). The tests have included selected studies on the influence of printed circuit board (PCB) thickness and usage of a board level underfill. WLP with SAC-Q solder ball show a significant improvement versus the industry standard SAC405 solder balls. In temperature cycling on board (TCoB), WLP's with SAC-Q (SAC405 with 3% Bi) achieve more than 2000 cycles without fail in temperature range from -40°C to 85°C on a 0.8 mm thick PCB, whereby first fails with SAC405 balls were observed above 800 cycles. All WLP's with LF35 (SAC125Ni) solder alloy fail before 1000 cycles. The failure mode in TCoB changes from solder joint fatigue for SAC405 and LF35 to Cu redistribution layer (RDL) cracks for SAC-Q. The 28 nm functional die packaged with WLP show no ELK crack or any other fail after 1000 cycles for SAC-Q alloy balls. The TCoB with SAC405 WLP pass 2000 cycles without fail when an underfill was applied. Non-underfilled WLP with SAC405 balls assembled on a thickness reduced 0.4 mm PCB show also a significant improvement with a first fail above 1900 cycles. WLP with SAC-Q and SAC405 passed mechanical shock (24 drops at 10k g).
{"title":"Study of the Board Level Reliability Performance of a Large 0.3 mm Pitch Wafer Level Package","authors":"B. Waidhas, Jan Proschwitz, Christoph Pietryga, Thomas Wagner, B. Keser","doi":"10.1109/ECTC.2019.00179","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00179","url":null,"abstract":"Board level reliability investigations have been performed on 36 mm² wafer level packages (WLP) with a 0.3 mm ball pitch. Three different solder ball alloys were included in the temperature cycling, thermal shock and mechanical shock test. In addition to daisy chain test vehicles to address the solder joint reliability, 28 nm die packaged with WLP were included in the assessment to check the stress impact on extreme low K dielectric (ELK) in the die back-end-of-line (BEOL). The tests have included selected studies on the influence of printed circuit board (PCB) thickness and usage of a board level underfill. WLP with SAC-Q solder ball show a significant improvement versus the industry standard SAC405 solder balls. In temperature cycling on board (TCoB), WLP's with SAC-Q (SAC405 with 3% Bi) achieve more than 2000 cycles without fail in temperature range from -40°C to 85°C on a 0.8 mm thick PCB, whereby first fails with SAC405 balls were observed above 800 cycles. All WLP's with LF35 (SAC125Ni) solder alloy fail before 1000 cycles. The failure mode in TCoB changes from solder joint fatigue for SAC405 and LF35 to Cu redistribution layer (RDL) cracks for SAC-Q. The 28 nm functional die packaged with WLP show no ELK crack or any other fail after 1000 cycles for SAC-Q alloy balls. The TCoB with SAC405 WLP pass 2000 cycles without fail when an underfill was applied. Non-underfilled WLP with SAC405 balls assembled on a thickness reduced 0.4 mm PCB show also a significant improvement with a first fail above 1900 cycles. WLP with SAC-Q and SAC405 passed mechanical shock (24 drops at 10k g).","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"24 1","pages":"1159-1164"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78926969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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