M. Alhendi, R. Sivasubramony, J. Lombardi, D. Weerawarne, P. Borgesen, M. Poliks, A. Alizadeh
Growing demand for wearable and disposable electronics leads to a need for cost effective and compact sensor designs and fabrication. Most of the devices are multi-layered and require a carrier substrate to hold the sensors. Paper substrates have gained attention since they have the potential to act as both the sensor and the substrate itself. Paper-based printed sensors have been demonstrated and shown functional. However, device fabrication on paper is challenging because of the surface roughness, bleeding, and incompatibility with high temperature sintering processes needed to achieve high conductivity. The conductivity of the interconnects is therefore usually relatively low and imposes performance limitations. Here we report, for the first time, highly conductive silver nano-particle interconnects printed on a paper substrate and sintered with a continuous wave laser. The printing process was identified and the laser sintering parameters were optimized to achieve a conductivity of approximately 67% of the bulk material. As an example of application, interdigitated electrodes were printed and laser sintered. The leakage current was monitored while aging at 50°C /85% RH conditions and exposing to water and artificial sweat.
{"title":"Laser Sintering of Aerosol Jet Printed Conductive Interconnects on Paper Substrate","authors":"M. Alhendi, R. Sivasubramony, J. Lombardi, D. Weerawarne, P. Borgesen, M. Poliks, A. Alizadeh","doi":"10.1109/ECTC.2019.00243","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00243","url":null,"abstract":"Growing demand for wearable and disposable electronics leads to a need for cost effective and compact sensor designs and fabrication. Most of the devices are multi-layered and require a carrier substrate to hold the sensors. Paper substrates have gained attention since they have the potential to act as both the sensor and the substrate itself. Paper-based printed sensors have been demonstrated and shown functional. However, device fabrication on paper is challenging because of the surface roughness, bleeding, and incompatibility with high temperature sintering processes needed to achieve high conductivity. The conductivity of the interconnects is therefore usually relatively low and imposes performance limitations. Here we report, for the first time, highly conductive silver nano-particle interconnects printed on a paper substrate and sintered with a continuous wave laser. The printing process was identified and the laser sintering parameters were optimized to achieve a conductivity of approximately 67% of the bulk material. As an example of application, interdigitated electrodes were printed and laser sintered. The leakage current was monitored while aging at 50°C /85% RH conditions and exposing to water and artificial sweat.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"62 1","pages":"1581-1587"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84576106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hae-in Kim, Seahee Hwangbo, Renuka Bowrothu, Y. Yoon
A highly compact, multiband composite right/left-handed (CRLH) transmission line based stub for tri-band applications with two GPS (L1, L2) frequencies, and GSM frequency, is demonstrated. The advantages of this work are as follows: 1) The three frequencies are covered by a single /4 stub, providing compactness and reducing system complexity; 2) By using a substrate with a high dielectric constant, additional size reduction is realized. The lumped element circuit model has been designed using Advanced Design Systems (ADS, Keysight Technologies Inc.) and the parameters are calculated based on the bridged-CRLH (B-CRLH) circuit model. Distributed components have been designed with a numerical simulation program, High Frequency Structure Simulator (HFSS, ANSYS Inc.). The CRLH based quarter wavelength stub is characterized by the frequency-phase dispersion diagram and scattering parameters. The demonstrated design uses a meander line structure in an M-shape, the so-called M-CRLH, to provide the shunt and series capacitance and inductance, and the bridge inductance. An open-circuited quarter wavelength (λ/4) tri-band CRLH transmission line based stub is fabricated and characterized.
{"title":"Highly Compact, Multiband Composite-Right/Left-Handed(CRLH) Transmission Line Based Stub for GPS Applications","authors":"Hae-in Kim, Seahee Hwangbo, Renuka Bowrothu, Y. Yoon","doi":"10.1109/ECTC.2019.00-35","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-35","url":null,"abstract":"A highly compact, multiband composite right/left-handed (CRLH) transmission line based stub for tri-band applications with two GPS (L1, L2) frequencies, and GSM frequency, is demonstrated. The advantages of this work are as follows: 1) The three frequencies are covered by a single /4 stub, providing compactness and reducing system complexity; 2) By using a substrate with a high dielectric constant, additional size reduction is realized. The lumped element circuit model has been designed using Advanced Design Systems (ADS, Keysight Technologies Inc.) and the parameters are calculated based on the bridged-CRLH (B-CRLH) circuit model. Distributed components have been designed with a numerical simulation program, High Frequency Structure Simulator (HFSS, ANSYS Inc.). The CRLH based quarter wavelength stub is characterized by the frequency-phase dispersion diagram and scattering parameters. The demonstrated design uses a meander line structure in an M-shape, the so-called M-CRLH, to provide the shunt and series capacitance and inductance, and the bridge inductance. An open-circuited quarter wavelength (λ/4) tri-band CRLH transmission line based stub is fabricated and characterized.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"2085-2090"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83134394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Use of dry plasma etching rather than wet etching of a Cu-seed layer in a semi-additive process enabled more precise dimension controllability in the patterning of submicron-scale Cu traces due to no shift in the width of the traces. This controllability is comparable to that of competitive fabrication technologies such as that for damascene-based Cu redistribution layers. The dry etching enabled the patterning of Cu traces with an aspect ratio as high as 4.2 (L/S=0.7/0.7 µm, 3.0 µm in height) without any failures such as electrical shorts between traces. Simulation showed that an increase in the aspect ratio effectively reduced signal transmission loss due to a reduction in conductor loss. The dry etching provided very smooth surfaces on the Cu-trace side-wall (roughness as low as 0.05 µm). This further reduced the signal transmission loss compared to that of wet-etched Cu traces. Submicron-scale patterning of Cu traces using dry etching enables flexible design of redistribution layer lines in terms of signal integrity, in addition to increasing the number of signal I/Os cost effectively.
{"title":"Submicron-Scale Cu RDL Pattering Based on Semi-Additive Process for Heterogeneous Integration","authors":"T. Takano, H. Kudo, Masaya Tanaka, M. Akazawa","doi":"10.1109/ECTC.2019.00022","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00022","url":null,"abstract":"Use of dry plasma etching rather than wet etching of a Cu-seed layer in a semi-additive process enabled more precise dimension controllability in the patterning of submicron-scale Cu traces due to no shift in the width of the traces. This controllability is comparable to that of competitive fabrication technologies such as that for damascene-based Cu redistribution layers. The dry etching enabled the patterning of Cu traces with an aspect ratio as high as 4.2 (L/S=0.7/0.7 µm, 3.0 µm in height) without any failures such as electrical shorts between traces. Simulation showed that an increase in the aspect ratio effectively reduced signal transmission loss due to a reduction in conductor loss. The dry etching provided very smooth surfaces on the Cu-trace side-wall (roughness as low as 0.05 µm). This further reduced the signal transmission loss compared to that of wet-etched Cu traces. Submicron-scale patterning of Cu traces using dry etching enables flexible design of redistribution layer lines in terms of signal integrity, in addition to increasing the number of signal I/Os cost effectively.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"94-100"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82396636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Sirbu, Y. Eichhammer, H. Oppermann, T. Tekin, J. Kraft, V. Sidorov, X. Yin, J. Bauwelinck, C. Neumeyr, Francisco Soares
In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding. The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm²) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer. Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55µm wavelength is integrated within the interposer to be used for routing and switching of the optical signals. Main fabrication and packaging steps are described here, together with some demonstrator evaluation results.
{"title":"3D Silicon Photonics Interposer for Tb/s Optical Interconnects in Data Centers with Double-Side Assembled Active Components and Integrated Optical and Electrical Through Silicon Via on SOI","authors":"B. Sirbu, Y. Eichhammer, H. Oppermann, T. Tekin, J. Kraft, V. Sidorov, X. Yin, J. Bauwelinck, C. Neumeyr, Francisco Soares","doi":"10.1109/ECTC.2019.00165","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00165","url":null,"abstract":"In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding. The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm²) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer. Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55µm wavelength is integrated within the interposer to be used for routing and switching of the optical signals. Main fabrication and packaging steps are described here, together with some demonstrator evaluation results.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"78 1","pages":"1052-1059"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77516233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Material hybridization between organic and inorganic materials is crucially important for the development of IoT devices. Especially for wearable and flexible IoT electronics, which are commonly integrated by transfer printing process, organic-inorganic bonding is indispensable for the integration of diverse electronic components. Existing hybrid bonding technologies like laser-assisted bonding or friction stirring welding achieve organic-inorganic bonding using high temperatures as high as melting point of polymers; however, these causes severe material deterioration. Thus, hybrid bonding must be achieved at low temperatures. Here we report a novel hybrid bonding method at the solid-state level and under the atmospheric pressure. Inorganic materials like tin were bonded to polyimide via the ethanol-assisted vacuum ultraviolet (E-VUV) irradiation process, where specimen surface were exposed to a vacuum-ultraviolet (VUV)-irradiated ethanol vapor atmosphere before bonding. VUV-induced re-assembly of ethanol vapor molecules was used to develop hydroxyl-carrying alkyl chains through coordinatively-bonded carboxylate onto tin, whereas numerous hydroxyl-carrying alkyls were created on polyimide. Triggering dehydration via these hydroxyls by merely heating to 150 °C for a few minutes produced robust organic-inorganic reticulated complexes at the tin/polyimide interface. Interface observation via transmission electron microscopy (TEM) shows that the bonded tin/polyimide was extremely compact without readily visible voids. A great number of nano-grains of organic-inorganic complexes were observed in the polyimide side but located ca. 35 nm away from the initial interface, indicating that tin interdiffusion into the polyimide side occurred during hybrid bonding and thus enhanced bondability. The hybrid interface is believed robust due to the strong organic-inorganic nano-grains. Finally, the E-VUV process was experimentally proven to possess broad applicability to diverse inorganic materials, such as aluminum, iron, titanium, and silicon. Adhesion mechanism of E-VUV process was proposed in this study. The E-VUV bonding strategy is expected to be utilized in micro-assembly of flexible and wearable/implantable IoT electronics.
{"title":"A Single Bonding Process for Diverse Organic-Inorganic Integration in IoT Devices","authors":"Tilo H. Yang, Y. Chiu, H. Yu, A. Shigetou, C. Kao","doi":"10.1109/ECTC.2019.00042","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00042","url":null,"abstract":"Material hybridization between organic and inorganic materials is crucially important for the development of IoT devices. Especially for wearable and flexible IoT electronics, which are commonly integrated by transfer printing process, organic-inorganic bonding is indispensable for the integration of diverse electronic components. Existing hybrid bonding technologies like laser-assisted bonding or friction stirring welding achieve organic-inorganic bonding using high temperatures as high as melting point of polymers; however, these causes severe material deterioration. Thus, hybrid bonding must be achieved at low temperatures. Here we report a novel hybrid bonding method at the solid-state level and under the atmospheric pressure. Inorganic materials like tin were bonded to polyimide via the ethanol-assisted vacuum ultraviolet (E-VUV) irradiation process, where specimen surface were exposed to a vacuum-ultraviolet (VUV)-irradiated ethanol vapor atmosphere before bonding. VUV-induced re-assembly of ethanol vapor molecules was used to develop hydroxyl-carrying alkyl chains through coordinatively-bonded carboxylate onto tin, whereas numerous hydroxyl-carrying alkyls were created on polyimide. Triggering dehydration via these hydroxyls by merely heating to 150 °C for a few minutes produced robust organic-inorganic reticulated complexes at the tin/polyimide interface. Interface observation via transmission electron microscopy (TEM) shows that the bonded tin/polyimide was extremely compact without readily visible voids. A great number of nano-grains of organic-inorganic complexes were observed in the polyimide side but located ca. 35 nm away from the initial interface, indicating that tin interdiffusion into the polyimide side occurred during hybrid bonding and thus enhanced bondability. The hybrid interface is believed robust due to the strong organic-inorganic nano-grains. Finally, the E-VUV process was experimentally proven to possess broad applicability to diverse inorganic materials, such as aluminum, iron, titanium, and silicon. Adhesion mechanism of E-VUV process was proposed in this study. The E-VUV bonding strategy is expected to be utilized in micro-assembly of flexible and wearable/implantable IoT electronics.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"17 1","pages":"235-242"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77812717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Niloofar Shakoorzadeh, SivaChandra Jangam, K. Rahim, Pranav Ambhore, H. Chien, A. Hanna, S. Iyer
The silicon interconnect fabric (Si-IF) is a heterogeneous integration platform that allows fine pitch interconnect between dies and substrate (< 10 µm) through thermal compression bonding of pillars on the Si-IF to pads on die side. In this integration scheme, bare dies of different nodes are attached directly to a prewired Si substrate. No underfill or molding compound is used in Si-IF. In this paper, we describe a novel passivation technique comprised of two processes. The first process is based on having sidewall passivation on Cu pillars on the Si-IF prior to TCB by controlling the etch profile of PECVD deposited SiO2 inter layer dielectric (ILD). The second process is based on passivation of the assembled dies on Si-IF post die-to-wafer bonding. To achieve the second encapsulation, study was done on Parylene C with two different thicknesses of 1 and 3 µm. Humidity testing was done in accordance with "85/85" Steady-State Humidity Life Test standard on blanket Cu coupons. Xray powder diffraction (XRD) revealed the presence of copper oxide after 72 hours of humidity testing in samples passivated with 1 and 3 µm of Parylene C. Next, we studied barrier properties of a multilayer thin film consisting of an inorganic (SiNx) layer and an organic (Parylene C) layer. XRD scans of samples subjected to humidity testing for up to 168 hours showed no signs of Cu oxide peaks. Humidity testing was done on bonded samples with multilayer encapsulation. Shear strength was measured before and after 120 hours of humidity testing. Average shear force of the samples was 135 N and 134.58 N before and after 120 hours of humidity testing, respectively. Resistance of passivated Si-IF wafers didn't change during the same period of humidity testing.
{"title":"Reliability Studies of Silicon Interconnect Fabric","authors":"Niloofar Shakoorzadeh, SivaChandra Jangam, K. Rahim, Pranav Ambhore, H. Chien, A. Hanna, S. Iyer","doi":"10.1109/ECTC.2019.00126","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00126","url":null,"abstract":"The silicon interconnect fabric (Si-IF) is a heterogeneous integration platform that allows fine pitch interconnect between dies and substrate (< 10 µm) through thermal compression bonding of pillars on the Si-IF to pads on die side. In this integration scheme, bare dies of different nodes are attached directly to a prewired Si substrate. No underfill or molding compound is used in Si-IF. In this paper, we describe a novel passivation technique comprised of two processes. The first process is based on having sidewall passivation on Cu pillars on the Si-IF prior to TCB by controlling the etch profile of PECVD deposited SiO2 inter layer dielectric (ILD). The second process is based on passivation of the assembled dies on Si-IF post die-to-wafer bonding. To achieve the second encapsulation, study was done on Parylene C with two different thicknesses of 1 and 3 µm. Humidity testing was done in accordance with \"85/85\" Steady-State Humidity Life Test standard on blanket Cu coupons. Xray powder diffraction (XRD) revealed the presence of copper oxide after 72 hours of humidity testing in samples passivated with 1 and 3 µm of Parylene C. Next, we studied barrier properties of a multilayer thin film consisting of an inorganic (SiNx) layer and an organic (Parylene C) layer. XRD scans of samples subjected to humidity testing for up to 168 hours showed no signs of Cu oxide peaks. Humidity testing was done on bonded samples with multilayer encapsulation. Shear strength was measured before and after 120 hours of humidity testing. Average shear force of the samples was 135 N and 134.58 N before and after 120 hours of humidity testing, respectively. Resistance of passivated Si-IF wafers didn't change during the same period of humidity testing.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"57 1","pages":"800-805"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79367205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Juang, K. Shie, Po-Ning Hsu, Yu Jin Li, K. Tu, Chih Chen
In this study, we fabricated (111)-oriented nt-Cu microbumps with 30 µm in diameter, and bonded them together using chip-to-chip bonding scheme in N2 ambient, without vacuum. A well bonded interface in the Cu-to-Cu joint was identified by the microstructure observation. Scanning electron microscope (SEM) images showed a void-less bonding interface within the bonded Cu joint. In addition, a die shear test was conducted. The test results revealed that the shear strength is 124 MPa, which is nearly two times higher than the SnAg solder joint (64 MPa). It indicates that the Cu joint is more robust than the SnAg joint. In addition, fracture analysis showed that the joint fractured in a ductile manner. Besides, we also performed the resistance measurement by using Kelvin probes on the bonded chip-to-chip test vehicles. The resistance is 4.12 mΩ for a single joint and its contact resistivity is 4.26 × 10-8 Ω·cm2. More than 30% resistance reduction has been confirmed as compared to the SnAg solder joint (6.32 mΩ). Moreover, we can further reduce the joint resistance by the second annealing process. The resistance can be brought down to 3.27 mΩ with a resistivity of 3.14 × 10^-8 Ω·cm^2. There is a nearly 50% resistance reduction The resistance for second annealed Cu joint is close the ideal bulk Cu. In summary, the chip-to-chip copper direct bonding has been successfully achieved and low resistance Cu-to-Cu joints has been realized by using (111) oriented nt-Cu in no-vacuum ambient.
{"title":"Low-Resistance and high-Strength Copper Direct Bonding in no-Vacuum Ambient Using Highly (111)-Oriented Nano-Twinned Copper","authors":"J. Juang, K. Shie, Po-Ning Hsu, Yu Jin Li, K. Tu, Chih Chen","doi":"10.1109/ECTC.2019.00102","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00102","url":null,"abstract":"In this study, we fabricated (111)-oriented nt-Cu microbumps with 30 µm in diameter, and bonded them together using chip-to-chip bonding scheme in N2 ambient, without vacuum. A well bonded interface in the Cu-to-Cu joint was identified by the microstructure observation. Scanning electron microscope (SEM) images showed a void-less bonding interface within the bonded Cu joint. In addition, a die shear test was conducted. The test results revealed that the shear strength is 124 MPa, which is nearly two times higher than the SnAg solder joint (64 MPa). It indicates that the Cu joint is more robust than the SnAg joint. In addition, fracture analysis showed that the joint fractured in a ductile manner. Besides, we also performed the resistance measurement by using Kelvin probes on the bonded chip-to-chip test vehicles. The resistance is 4.12 mΩ for a single joint and its contact resistivity is 4.26 × 10-8 Ω·cm2. More than 30% resistance reduction has been confirmed as compared to the SnAg solder joint (6.32 mΩ). Moreover, we can further reduce the joint resistance by the second annealing process. The resistance can be brought down to 3.27 mΩ with a resistivity of 3.14 × 10^-8 Ω·cm^2. There is a nearly 50% resistance reduction The resistance for second annealed Cu joint is close the ideal bulk Cu. In summary, the chip-to-chip copper direct bonding has been successfully achieved and low resistance Cu-to-Cu joints has been realized by using (111) oriented nt-Cu in no-vacuum ambient.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"11 1","pages":"642-647"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74811467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seokho Kim, P. Kang, Taeyeong Kim, Kyuha Lee, Joohee Jang, Kwangjin Moon, Hoonjoo Na, S. Hyun, K. Hwang
The scaling of semiconductor device below 10nm has faced the higher process difficulty and longer development periods. Three-dimensional integrated circuits (3D IC) using chip partitioning and wafer-to-wafer bonding have been acknowledged as the next generation semiconductor stacking technology because of smaller form factor, higher density integration and higher performance compared to same-node devices. Wafer-to-wafer bonding is widely used in stacked CMOS image sensor, that is, the bonding between pixel and logic wafer, and this technology has the potential to apply other semiconductor devices. Cu-Cu hybrid bonding has achieved by simultaneous wafer bonding of metal (Cu-Cu) and dielectric materials. In this study, it is investigated on the microstructure of Cu pad for Cu-Cu bonding after post-electroplating and post-bonding annealing process. The Cu grain size distribution and orientation are analyzed with different anneal temperature, which is applied on electroplated Cu, and with additional heat treatment as post-bonding process. The effect of pad size as well as the position within pattern array on Cu microstructure is also studied as the bonding pad is required smaller and smaller size for high density bonding. After Cu-Cu bonding, the cross-section analysis of bonding interface is carried out to see inter-diffusion of Cu atoms across the opposite Cu pad. Cu-Cu hybrid bonding is applied to test vehicle having the daisy chain of 2.4 million. The electrical resistance is measured before and after thermal stress and the Cu-Cu bonding interface is confirmed as robust structure.
{"title":"Cu Microstructure of High Density Cu Hybrid Bonding Interconnection","authors":"Seokho Kim, P. Kang, Taeyeong Kim, Kyuha Lee, Joohee Jang, Kwangjin Moon, Hoonjoo Na, S. Hyun, K. Hwang","doi":"10.1109/ECTC.2019.00101","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00101","url":null,"abstract":"The scaling of semiconductor device below 10nm has faced the higher process difficulty and longer development periods. Three-dimensional integrated circuits (3D IC) using chip partitioning and wafer-to-wafer bonding have been acknowledged as the next generation semiconductor stacking technology because of smaller form factor, higher density integration and higher performance compared to same-node devices. Wafer-to-wafer bonding is widely used in stacked CMOS image sensor, that is, the bonding between pixel and logic wafer, and this technology has the potential to apply other semiconductor devices. Cu-Cu hybrid bonding has achieved by simultaneous wafer bonding of metal (Cu-Cu) and dielectric materials. In this study, it is investigated on the microstructure of Cu pad for Cu-Cu bonding after post-electroplating and post-bonding annealing process. The Cu grain size distribution and orientation are analyzed with different anneal temperature, which is applied on electroplated Cu, and with additional heat treatment as post-bonding process. The effect of pad size as well as the position within pattern array on Cu microstructure is also studied as the bonding pad is required smaller and smaller size for high density bonding. After Cu-Cu bonding, the cross-section analysis of bonding interface is carried out to see inter-diffusion of Cu atoms across the opposite Cu pad. Cu-Cu hybrid bonding is applied to test vehicle having the daisy chain of 2.4 million. The electrical resistance is measured before and after thermal stress and the Cu-Cu bonding interface is confirmed as robust structure.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"636-641"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91507202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Solder joint failure is a serious reliability concern in area array technologies, such as flip chip (FC), Plastic Ball Grid Array (PBGA), Fan-In and Fan-Out Wafer Level Packages (WLP) of advanced IC package. The selection of different substrate materials, solder material, molding compound, stacked dies structure, and laminate material could affect the solder joint stress-strain condition. It is therefore important to know the solder joint shape and standoff height accurately after the reflow process to estimate the reliability of solder joint assembly in three aspects: temperature cycling, mechanical shock, and vibration. A strategy for importing three-dimensional computed tomography (CT) data into a Finite Element based reliability evaluation is outlined. Three dimensional CT is a very fast, non-destructive automatic inspection machine. Moreover, with new version of CT scanning in high resolution, full solder geometry is reconstructed throughout the entire area array on printed circuit board assembly (PCBA). Finite Element Analysis (FEA) is used to calculate the accumulated plastic work per cycle for BGA packages on PCBA. The accumulated plastic work is then used to calculate the number of cycles to failure based on thermal fatigue life model of solder joints. FEA is also used to predict the damage index during shock and vibration event, and used to study mounting configurations and structural integrity of solder joints. The reliability results showed a good agreement with the experimental results based on two designs on new solid state drive (SSD) form factor. It was found that the cycles to failure and critical location among four corner joints match well with experimental results. From simulation results, it was also found that new design was much improved over old design. The methodology was extended to reliability evaluation for BGA packages such as FC controller, DDR SDRAM, and NAND packages on PCBA. Results demonstrate the excellent capability of the proposed integration tools for predicting the robustness of PCBA. The proposed approach greatly reduces reliability evaluation time, shortens the product life cycle development, and is more cost effective to address the reliability issues.
{"title":"Realistic Solder Joint Geometry Integration with Finite Element Analysis for Reliability Evaluation of Printed Circuit Board Assembly","authors":"C. Lau, Ning Ye, H. Takiar","doi":"10.1109/ECTC.2019.00214","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00214","url":null,"abstract":"Solder joint failure is a serious reliability concern in area array technologies, such as flip chip (FC), Plastic Ball Grid Array (PBGA), Fan-In and Fan-Out Wafer Level Packages (WLP) of advanced IC package. The selection of different substrate materials, solder material, molding compound, stacked dies structure, and laminate material could affect the solder joint stress-strain condition. It is therefore important to know the solder joint shape and standoff height accurately after the reflow process to estimate the reliability of solder joint assembly in three aspects: temperature cycling, mechanical shock, and vibration. A strategy for importing three-dimensional computed tomography (CT) data into a Finite Element based reliability evaluation is outlined. Three dimensional CT is a very fast, non-destructive automatic inspection machine. Moreover, with new version of CT scanning in high resolution, full solder geometry is reconstructed throughout the entire area array on printed circuit board assembly (PCBA). Finite Element Analysis (FEA) is used to calculate the accumulated plastic work per cycle for BGA packages on PCBA. The accumulated plastic work is then used to calculate the number of cycles to failure based on thermal fatigue life model of solder joints. FEA is also used to predict the damage index during shock and vibration event, and used to study mounting configurations and structural integrity of solder joints. The reliability results showed a good agreement with the experimental results based on two designs on new solid state drive (SSD) form factor. It was found that the cycles to failure and critical location among four corner joints match well with experimental results. From simulation results, it was also found that new design was much improved over old design. The methodology was extended to reliability evaluation for BGA packages such as FC controller, DDR SDRAM, and NAND packages on PCBA. Results demonstrate the excellent capability of the proposed integration tools for predicting the robustness of PCBA. The proposed approach greatly reduces reliability evaluation time, shortens the product life cycle development, and is more cost effective to address the reliability issues.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"7 1","pages":"1387-1395"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81173265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the clock frequency of SOC (system on a chip) including core circuits like CPU and GPU and various IOs like LPDDR4, LPDDR5, and SERDES, increases, the impact of SDN (signal delivery network) and PDN (power delivery network) on the functional stability and low power operation of corresponding circuit blocks becomes more and more important. However, there has been the challenge to the design and verification with co-simulation of SI (signal integrity) and PI (power integrity) considering the coupling between SDN and PDN due to a painful long simulation time, which is usually not allowed in the short design cycles required by modern electronics especially in mobile hand-held devices. This paper will provide a matrix formulation for SI-PI co-simulation in frequency-domain to reduce the simulation time and consider the coupling efficiently.
{"title":"A New SI-PI co-Simulation Approach for Efficient Consideration of Coupling Between PDN and SDN","authors":"Hee-Bum Lee, Jisoo Hwang, Hoi-Jin Lee, Youngmin Shin","doi":"10.1109/ECTC.2019.00108","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00108","url":null,"abstract":"As the clock frequency of SOC (system on a chip) including core circuits like CPU and GPU and various IOs like LPDDR4, LPDDR5, and SERDES, increases, the impact of SDN (signal delivery network) and PDN (power delivery network) on the functional stability and low power operation of corresponding circuit blocks becomes more and more important. However, there has been the challenge to the design and verification with co-simulation of SI (signal integrity) and PI (power integrity) considering the coupling between SDN and PDN due to a painful long simulation time, which is usually not allowed in the short design cycles required by modern electronics especially in mobile hand-held devices. This paper will provide a matrix formulation for SI-PI co-simulation in frequency-domain to reduce the simulation time and consider the coupling efficiently.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"682-687"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89454625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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