E. Sorensen, Boris Vaisband, SivaChandra Jangam, T. Shirley, S. Iyer
The silicon interconnect fabric (Si-IF) is a wafer-level packaging platform that enables heterogeneous integration of die at ultra-fine pitch (2 to 10 µm) directly onto a lithographically defined silicon wafer with no intermediate packaging hierarchy. The die are attached with an extremely tight inter-dielet spacing (< 100 µm). The small inter-dielet spacing is especially advantageous in high frequency applications due to reduced loss associated with the transmission line behavior of off-chip interconnects. Since indium phosphide (InP) is a popular technology choice for high frequency applications, the goal of this paper is to investigate the efficacy of direct Au-Au thermo-compression bonding (TCB) of InP die to the Si-IF platform for the first time. To evaluate this process, 84 InP die were successfully bonded to the Si-IF. The sheer strength of the integrated die ranges from 38 MPa to 238 MPa, for die that were attached using pressure ranging, respectively, from 100 MPa to 350 MPa. Daisy chain resistance of the bonded die was measured exhibiting good correlation with calculated theoretical values. After thermal cycling, it was found that 100% of the attached die withstood all thermal stressing despite the thermal mismatch of 2 ppm/K between the die and the Si-IF.
{"title":"Integration and Characterization of InP Die on Silicon Interconnect Fabric","authors":"E. Sorensen, Boris Vaisband, SivaChandra Jangam, T. Shirley, S. Iyer","doi":"10.1109/ECTC.2019.00088","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00088","url":null,"abstract":"The silicon interconnect fabric (Si-IF) is a wafer-level packaging platform that enables heterogeneous integration of die at ultra-fine pitch (2 to 10 µm) directly onto a lithographically defined silicon wafer with no intermediate packaging hierarchy. The die are attached with an extremely tight inter-dielet spacing (< 100 µm). The small inter-dielet spacing is especially advantageous in high frequency applications due to reduced loss associated with the transmission line behavior of off-chip interconnects. Since indium phosphide (InP) is a popular technology choice for high frequency applications, the goal of this paper is to investigate the efficacy of direct Au-Au thermo-compression bonding (TCB) of InP die to the Si-IF platform for the first time. To evaluate this process, 84 InP die were successfully bonded to the Si-IF. The sheer strength of the integrated die ranges from 38 MPa to 238 MPa, for die that were attached using pressure ranging, respectively, from 100 MPa to 350 MPa. Daisy chain resistance of the bonded die was measured exhibiting good correlation with calculated theoretical values. After thermal cycling, it was found that 100% of the attached die withstood all thermal stressing despite the thermal mismatch of 2 ppm/K between the die and the Si-IF.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"28 1","pages":"543-549"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80341226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Toshiki Iwai, T. Sakai, D. Mizutani, S. Sakuyama, Kenji Iida, T. Inaba, H. Fujisaki, A. Tamura, Yoshinori Miyazawa
Silicon interposer (Si-IP) technology has been used in accelerated processing units such as graphic processing units in high-performance computing because it can package a system-on-chip and high bandwidth memories. However, the conventional Si-IP has difficulty developing larger packages because of the mismatch in the coefficient thermal expansions (CTE) of the Si-IP and the organic substrate. Therefore, the Si-IP has limited capacity for improving computing performance by the application which requires more chips. We developed a multilayer glass substrate (Glass-ST) that features a stacked glass core and propose to apply this Glass-ST to a computer board. The proposed structure has no CTE mismatch and can use high density wiring. Thus, the Glass-ST enables the assembly of more large chips than is possible using the conventional Si-IP. In this study, we prepared a 100X100 mm Glass-ST with a 5/5 µm line/space and 20 µmΦ vias. We mounted nine 21X21 mm chips with 40 µm pitch micro bumps. The results revealed that conformal plated through glass vias and a fine wiring pattern had been fabricated in the Glass-ST, and that the nine chips and Glass-ST were connected by micro bumps. The maximum warpage of the nine chips was 23 µm between temperatures of 30°C and 250°C. This means that the Glass-ST can mount chips with micro bumps due to the very slight resulting warpage. In addition, we performed thermomechanical simulation to investigate the stress experienced by the micro bumps. The results show that the maximum stresses of micro bumps with pitches ranging between 10 µm and 55 um are very similar to that of 40 µm pitch micro bumps with which the real sample was packaged. We believe the improvements in the computing performance are significant by the Glass-ST technology compared to that of the conventional Si-IP technology.
{"title":"Multilayer Glass Substrate with High Density Via Structure for All Inorganic Multi-chip Module","authors":"Toshiki Iwai, T. Sakai, D. Mizutani, S. Sakuyama, Kenji Iida, T. Inaba, H. Fujisaki, A. Tamura, Yoshinori Miyazawa","doi":"10.1109/ECTC.2019.00301","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00301","url":null,"abstract":"Silicon interposer (Si-IP) technology has been used in accelerated processing units such as graphic processing units in high-performance computing because it can package a system-on-chip and high bandwidth memories. However, the conventional Si-IP has difficulty developing larger packages because of the mismatch in the coefficient thermal expansions (CTE) of the Si-IP and the organic substrate. Therefore, the Si-IP has limited capacity for improving computing performance by the application which requires more chips. We developed a multilayer glass substrate (Glass-ST) that features a stacked glass core and propose to apply this Glass-ST to a computer board. The proposed structure has no CTE mismatch and can use high density wiring. Thus, the Glass-ST enables the assembly of more large chips than is possible using the conventional Si-IP. In this study, we prepared a 100X100 mm Glass-ST with a 5/5 µm line/space and 20 µmΦ vias. We mounted nine 21X21 mm chips with 40 µm pitch micro bumps. The results revealed that conformal plated through glass vias and a fine wiring pattern had been fabricated in the Glass-ST, and that the nine chips and Glass-ST were connected by micro bumps. The maximum warpage of the nine chips was 23 µm between temperatures of 30°C and 250°C. This means that the Glass-ST can mount chips with micro bumps due to the very slight resulting warpage. In addition, we performed thermomechanical simulation to investigate the stress experienced by the micro bumps. The results show that the maximum stresses of micro bumps with pitches ranging between 10 µm and 55 um are very similar to that of 40 µm pitch micro bumps with which the real sample was packaged. We believe the improvements in the computing performance are significant by the Glass-ST technology compared to that of the conventional Si-IP technology.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"1952-1957"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73914954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thermocompression bonding (TCB) process is now being adopted for high density interconnections but the necessity of applying force and heat causes a lot of problems, such as warpage-induced defects, cracking of delicate chips and thermal drift. To address the above issues, we proposed a novel bonding technique called microfluidic electroless interconnection (MELI) process to directly fabricate interconnection between Cu pillars at the temperature below 80°C and without applying any pressure on the chips. It has been shown in our previous researches that the MELI process using electroless Ni and electroless Au could bond vertical interconnection under controlled flow. In order to extend the application range of the MELI to fine pitch, in this study we analyze the feasibility of selective electroless deposition in microchannel by adding stabilizers into electroless Ni and electroless Au solution. Electroless plating can provide a uniform conformal coating on all parts of the surface that have been catalytically activated. However, the extended coating from the sides of the Cu pillar bump shortens the interconnect pitch, which may cause the risk of bridging. In this paper, we successfully achieve selective electroless Ni plating in microchannel by adding 1.5 ppm of lead acetate into the plating bath. As for electroless Au plating, selective deposition in the microchannel can be accomplished by narrowing the gap. In summary, the innovative MELI process provides a low-temperature and pressureless fine pitch bonding technique.
{"title":"Low Temperature and Pressureless Microfluidic Electroless Bonding Process for Vertical Interconnections","authors":"H. Hung, Sean Yang, I. Weng, Yan-Hao Chen, C. Kao","doi":"10.1109/ECTC.2019.00265","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00265","url":null,"abstract":"Thermocompression bonding (TCB) process is now being adopted for high density interconnections but the necessity of applying force and heat causes a lot of problems, such as warpage-induced defects, cracking of delicate chips and thermal drift. To address the above issues, we proposed a novel bonding technique called microfluidic electroless interconnection (MELI) process to directly fabricate interconnection between Cu pillars at the temperature below 80°C and without applying any pressure on the chips. It has been shown in our previous researches that the MELI process using electroless Ni and electroless Au could bond vertical interconnection under controlled flow. In order to extend the application range of the MELI to fine pitch, in this study we analyze the feasibility of selective electroless deposition in microchannel by adding stabilizers into electroless Ni and electroless Au solution. Electroless plating can provide a uniform conformal coating on all parts of the surface that have been catalytically activated. However, the extended coating from the sides of the Cu pillar bump shortens the interconnect pitch, which may cause the risk of bridging. In this paper, we successfully achieve selective electroless Ni plating in microchannel by adding 1.5 ppm of lead acetate into the plating bath. As for electroless Au plating, selective deposition in the microchannel can be accomplished by narrowing the gap. In summary, the innovative MELI process provides a low-temperature and pressureless fine pitch bonding technique.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"363 1","pages":"1729-1734"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76560486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ag wire-bonded packages have gained a lot of interest as a low-cost substitute material in lieu of Au wire-bonded packages. However, selective decapsulation still remains as challenges due to a corrosion on Ag wires, where Ag has a strong tendency to form a water-soluble Ag salt upon reaction with a conventional nitric acid etchant. This paper serves to present a chemical solution that can reduce corrosion on Ag wires during decapsulation process of the Ag wire-bonded packages. Also, our method is applicable for industry standard needs such as for decapsulation at high temperature.
{"title":"Reduction of Ag Corrosion Rate During Decapsulation of Ag Wire Bond Packages","authors":"Young-Ja Kim, Jinho Hah, K. Moon, C. Wong","doi":"10.1109/ECTC.2019.00325","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00325","url":null,"abstract":"Ag wire-bonded packages have gained a lot of interest as a low-cost substitute material in lieu of Au wire-bonded packages. However, selective decapsulation still remains as challenges due to a corrosion on Ag wires, where Ag has a strong tendency to form a water-soluble Ag salt upon reaction with a conventional nitric acid etchant. This paper serves to present a chemical solution that can reduce corrosion on Ag wires during decapsulation process of the Ag wire-bonded packages. Also, our method is applicable for industry standard needs such as for decapsulation at high temperature.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"65 1","pages":"2359-2364"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85775044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Pantano, G. van der Plas, P. Bex, P. Nolmans, D. Velenis, M. Verhelst, E. Beyne
Memory bandwidth is the main bottleneck to improve the performance of today's computing systems, and the demand for bandwidth is expected to grow exponentially in the coming years. The development of advanced packaging solutions making use of a silicon bridge such as Embedded Multi-Die Interconnect Bridge (EMIB) and Fan-Out Wafer Level Package (FO-WLP) are promising solutions to achieve high bandwidth density and to bring more memory closer to the computing units. This work demonstrates a 0.3V-swing 7mm long link over a silicon bridge, running at a bitrate of 9Gbps. It achieves 48fJ/bit/mm power efficiency on 3.5um pitch wires, resulting in a bandwidth density of 2.57Tbps/mm.
{"title":"A High-Bandwidth Fine-Pitch 2.57Tbps/mm In-package Communication Link Achieving 48fJ/bit/mm Efficiency","authors":"N. Pantano, G. van der Plas, P. Bex, P. Nolmans, D. Velenis, M. Verhelst, E. Beyne","doi":"10.1109/ECTC.2019.00107","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00107","url":null,"abstract":"Memory bandwidth is the main bottleneck to improve the performance of today's computing systems, and the demand for bandwidth is expected to grow exponentially in the coming years. The development of advanced packaging solutions making use of a silicon bridge such as Embedded Multi-Die Interconnect Bridge (EMIB) and Fan-Out Wafer Level Package (FO-WLP) are promising solutions to achieve high bandwidth density and to bring more memory closer to the computing units. This work demonstrates a 0.3V-swing 7mm long link over a silicon bridge, running at a bitrate of 9Gbps. It achieves 48fJ/bit/mm power efficiency on 3.5um pitch wires, resulting in a bandwidth density of 2.57Tbps/mm.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"674-681"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84912881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiefeng Xu, S. McCann, Huayan Wang, Jing Wang, Van-Lai Pham, S. Cain, G. Refai-Ahmed, S.B. Park
In this study, an accelerated Electromigration (EM) test was performed. The test vehicle has four types of common interconnect structure. The first one is a classic Ball Grid Array (BGA), short for BGA; the second one is a solder ball with a copper via on top, short for BGA-Via; the third one is an individual copper via in the substrate, short for Via; the last one is an individual copper Plated Through Hole (PTH), short for PTH in the substrate. The built-in serpentine copper fine lines around each structure were designed to monitor the local temperature in-situ. All test vehicles were stressed at 150oC temperature with 12A current. The voltage of each test structure and the resistance of the serpentine line were recorded in-situ. The results show that different micro-electrical structures have great effects on EM behavior, especially the time to failure (TTF). In BGA test structure, the failure occurred on the substrate side of solder ball; in BGA-Via, the failure was the depletion of the copper via. No failure was observed in Via and PTH test structures, even after an extremely long testing, although they have higher package temperature. The TTF of BGA-Via is about 2 times shorter than BGA. A finite element simulation based on Atom Flux Divergence (AFD) was performed to understand the failure mechanism and predict the TTF. The results show that via on top of solder ball will cause 10% higher current density than solder ball only. When the void underneath of the via in solder ball was nucleated, the current density will start to redistribute and reduce. In short, Via is the riskiest point for EM when it located near the solder ball.
{"title":"An Assessment of Electromigration in 2.5D Packaging","authors":"Jiefeng Xu, S. McCann, Huayan Wang, Jing Wang, Van-Lai Pham, S. Cain, G. Refai-Ahmed, S.B. Park","doi":"10.1109/ECTC.2019.00-25","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-25","url":null,"abstract":"In this study, an accelerated Electromigration (EM) test was performed. The test vehicle has four types of common interconnect structure. The first one is a classic Ball Grid Array (BGA), short for BGA; the second one is a solder ball with a copper via on top, short for BGA-Via; the third one is an individual copper via in the substrate, short for Via; the last one is an individual copper Plated Through Hole (PTH), short for PTH in the substrate. The built-in serpentine copper fine lines around each structure were designed to monitor the local temperature in-situ. All test vehicles were stressed at 150oC temperature with 12A current. The voltage of each test structure and the resistance of the serpentine line were recorded in-situ. The results show that different micro-electrical structures have great effects on EM behavior, especially the time to failure (TTF). In BGA test structure, the failure occurred on the substrate side of solder ball; in BGA-Via, the failure was the depletion of the copper via. No failure was observed in Via and PTH test structures, even after an extremely long testing, although they have higher package temperature. The TTF of BGA-Via is about 2 times shorter than BGA. A finite element simulation based on Atom Flux Divergence (AFD) was performed to understand the failure mechanism and predict the TTF. The results show that via on top of solder ball will cause 10% higher current density than solder ball only. When the void underneath of the via in solder ball was nucleated, the current density will start to redistribute and reduce. In short, Via is the riskiest point for EM when it located near the solder ball.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"2150-2155"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87681776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Alam, A. Hanna, R. Irwin, G. Ezhilarasu, Hyunpil Boo, Yuan Hu, C. Wong, T. Fisher, S. Iyer
We describe a Fan-Out Wafer-Level Packaging (FOWLP) integration process that is used to build an extremely flexible heterogeneous integration platform called "FlexTrateTM". We integrated a daisy chain connected 10×20 array of 1 mm2 Si dies over a 35 mm × 18 mm area using vertically corrugated Cu interconnects of 40 µm pitch and ~5 µm thickness. The system is reliable even upon bending to 1 mm bending radius for over 1000 bending cycles. We demonstrate a 37 mm × 52 mm foldable display with 1 mm2 InGaN LEDs using this technology. Cyclic mechanical bending (1 mm bending radius), optical, and thermal reliability of integrated display are investigated.
{"title":"Heterogeneous Integration of a Fan-Out Wafer-Level Packaging Based Foldable Display on Elastomeric Substrate","authors":"A. Alam, A. Hanna, R. Irwin, G. Ezhilarasu, Hyunpil Boo, Yuan Hu, C. Wong, T. Fisher, S. Iyer","doi":"10.1109/ECTC.2019.00048","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00048","url":null,"abstract":"We describe a Fan-Out Wafer-Level Packaging (FOWLP) integration process that is used to build an extremely flexible heterogeneous integration platform called \"FlexTrateTM\". We integrated a daisy chain connected 10×20 array of 1 mm2 Si dies over a 35 mm × 18 mm area using vertically corrugated Cu interconnects of 40 µm pitch and ~5 µm thickness. The system is reliable even upon bending to 1 mm bending radius for over 1000 bending cycles. We demonstrate a 37 mm × 52 mm foldable display with 1 mm2 InGaN LEDs using this technology. Cyclic mechanical bending (1 mm bending radius), optical, and thermal reliability of integrated display are investigated.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"5 1","pages":"277-282"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83663474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xuan Hong, Qizhuo Zhuo, Xinpei Cao, D. Maslyk, Noah Ekstrom, Juliet Sanchez, Selene Hernandez, Jinu Choi
Device miniaturization continues using System-on-Chip (SoC), System-in-Package (SiP), multichip module (MCM), and heterogeneous integration to deliver a wider range of functionalities without sacrificing valuable space on a substrate. With multiple integrated circuits and MEMS sensors integrated into a thin single module to perform as a full electronic system, the need for more compact and effective electromagnetic interference (EMI) protection between various baseband and wireless, RF, analog, and power management components is greater than ever before. Fortunately, as device miniaturization has accelerated, so has the development of novel shielding technologies to accommodate for the higher density package structures. Jet-dispensed compartment shielding is an integrated package-level solution that allows for much smaller semiconductor form factors and is achieved using a fully automatic assembly process with high performance.
{"title":"Compartmental EMI Shielding with Jet-Dispensed Material Technology","authors":"Xuan Hong, Qizhuo Zhuo, Xinpei Cao, D. Maslyk, Noah Ekstrom, Juliet Sanchez, Selene Hernandez, Jinu Choi","doi":"10.1109/ECTC.2019.00119","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00119","url":null,"abstract":"Device miniaturization continues using System-on-Chip (SoC), System-in-Package (SiP), multichip module (MCM), and heterogeneous integration to deliver a wider range of functionalities without sacrificing valuable space on a substrate. With multiple integrated circuits and MEMS sensors integrated into a thin single module to perform as a full electronic system, the need for more compact and effective electromagnetic interference (EMI) protection between various baseband and wireless, RF, analog, and power management components is greater than ever before. Fortunately, as device miniaturization has accelerated, so has the development of novel shielding technologies to accommodate for the higher density package structures. Jet-dispensed compartment shielding is an integrated package-level solution that allows for much smaller semiconductor form factors and is achieved using a fully automatic assembly process with high performance.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"753-757"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78775398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Combination of an integrated-optic chip launching a light beam from variable position on a waveguide surface and a Fourier transform lens will provide a microoptic beam-steering device. An array of switching grating couplers in a channel waveguide is a possible candidate for varying the beam launching position with miniaturized size. Utilization of a cavity-resonator-integrated grating coupler is discussed theoretically. A resonator waveguide with a grating coupler is stacked on a bus waveguide. Vertical directional coupling between the two waveguides occurs only when a resonance wavelength coincides with that of an incident guided wave. Vertically transferred optical wave in the resonator is coupled out by the grating coupler. The vertical directional coupling can be electrically tuned by utilizing electrooptic or thermooptic effects. A design model was developed on the basis of the coupled mode analysis. Coupling characteristic of design examples using silicon waveguides were discussed. Selective coupling was predicted with the radiation efficiency of 30% and the FWHM of 1.4 x 10-3 in the effective refractive index of the cavity waveguide. Difference between neighboring peaks of radiation efficiency was predicted to be 5.2 x 10-2 indicating the resolution power of 37 for cavity length of 15 microns. These characteristics show good agreement with simulation results by the finite-difference time-domain method.
将从波导表面可变位置发射光束的集成光学芯片与傅里叶变换透镜相结合，将提供一种微光束导向装置。通道波导中的开关光栅耦合器阵列是改变光束发射位置和小型化尺寸的可能选择。从理论上讨论了腔-谐振腔-集成光栅耦合器的应用。带光栅耦合器的谐振腔波导堆叠在母线波导上。两个波导之间的垂直方向耦合只有在共振波长与入射导波的波长一致时才会发生。在谐振腔内垂直传递的光波通过光栅耦合器耦合出来。垂直方向耦合可以利用电光或热光效应进行电调谐。在耦合模态分析的基础上建立了设计模型。讨论了硅波导设计实例的耦合特性。在腔波导有效折射率为1.4 x 10-3的情况下，预测了腔波导的辐射效率为30%，FWHM为1.4 x 10-3。相邻辐射效率峰之间的差值预测为5.2 x 10-2，表明对于15微米的腔长，分辨能力为37。这些特性与时域有限差分法的仿真结果吻合较好。
{"title":"Vertically Stacked and Directionally Coupled Cavity-Resonator-Integrated Grating Couplers for Integrated-Optic Beam Steering","authors":"S. Ura, J. Inoue, K. Kintaka","doi":"10.1109/ECTC.2019.00090","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00090","url":null,"abstract":"Combination of an integrated-optic chip launching a light beam from variable position on a waveguide surface and a Fourier transform lens will provide a microoptic beam-steering device. An array of switching grating couplers in a channel waveguide is a possible candidate for varying the beam launching position with miniaturized size. Utilization of a cavity-resonator-integrated grating coupler is discussed theoretically. A resonator waveguide with a grating coupler is stacked on a bus waveguide. Vertical directional coupling between the two waveguides occurs only when a resonance wavelength coincides with that of an incident guided wave. Vertically transferred optical wave in the resonator is coupled out by the grating coupler. The vertical directional coupling can be electrically tuned by utilizing electrooptic or thermooptic effects. A design model was developed on the basis of the coupled mode analysis. Coupling characteristic of design examples using silicon waveguides were discussed. Selective coupling was predicted with the radiation efficiency of 30% and the FWHM of 1.4 x 10-3 in the effective refractive index of the cavity waveguide. Difference between neighboring peaks of radiation efficiency was predicted to be 5.2 x 10-2 indicating the resolution power of 37 for cavity length of 15 microns. These characteristics show good agreement with simulation results by the finite-difference time-domain method.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"43 1","pages":"556-562"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75586714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Phommahaxay, S. Suhard, P. Bex, S. Iacovo, J. Slabbekoorn, F. Inoue, Lan Peng, K. Kennes, E. Sleeckx, G. Beyer, E. Beyne
The recent developments of wafer-to-wafer bonding technology based on direct assembly of inorganic dielectric materials is offering a path for the continuous need for higher integration density and lower interconnect pitches. However, numerous applications could benefit of a higher degree of design flexibility offered by a die-to-wafer approach. The achievement of high yielding die-to-wafer bonding with micron range die overlay is an essential element to unlock the potential of heterogeneous integration.
{"title":"Enabling Ultra-Thin Die to Wafer Hybrid Bonding for Future Heterogeneous Integrated Systems","authors":"A. Phommahaxay, S. Suhard, P. Bex, S. Iacovo, J. Slabbekoorn, F. Inoue, Lan Peng, K. Kennes, E. Sleeckx, G. Beyer, E. Beyne","doi":"10.1109/ECTC.2019.00097","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00097","url":null,"abstract":"The recent developments of wafer-to-wafer bonding technology based on direct assembly of inorganic dielectric materials is offering a path for the continuous need for higher integration density and lower interconnect pitches. However, numerous applications could benefit of a higher degree of design flexibility offered by a die-to-wafer approach. The achievement of high yielding die-to-wafer bonding with micron range die overlay is an essential element to unlock the potential of heterogeneous integration.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"AES-15 1","pages":"607-613"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84551027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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