T. Thai, S. Dalmia, Josef Hagn, Pouya Talebbeydokhti, Yossi Tsfati
5G millimeter wave (mmWave) communications that enables Gbps data channels often require broadband operation with dual polarization in multi frequency ranges (27-30, and 37-40GHz). Additionally, access points and base stations need large high gain antenna arrays and consistent radiation patterns across operation frequencies for ease of beam scanning control. Many stacked patch antennas were proposed as the solution. However, broadband patch antennas require thick substrate and multiple layers. For high volume production in standard substrate technology with acceptable yield, such solution targeting the consumer market has not been attempted previously. In this work, we present a novel multicore packaging approach to realize a unique and cost effective solution based on standard PCB/ Substrate technology. We demonstrate this with a complete mmWave RF module board with dimensions of 30mm x 50mm x 1.5mm. It consists of a large area dual polarization dual frequency (28GHz and 39GHz) stacked patch antenna array of 4x8 elements and fully integrated Systems-In-Package (SIPs) along with all the thermal and mechanical functions. This solution achieves a very high cross polarization discrimination ratio (>25dB), which is critical in the MIMO operation of the dual polarization network. The work includes measurements to validate the design and the packaging concept suitable for low cost mmWave 5G CPE (Customer Premises Equipment) and base station applications.
实现Gbps数据通道的5G毫米波(mmWave)通信通常需要在多频率范围(27- 30ghz和37-40GHz)内采用双极化的宽带操作。此外，接入点和基站需要大型高增益天线阵列和跨工作频率的一致辐射模式，以便于波束扫描控制。提出了采用叠置贴片天线作为解决方案。然而，宽带贴片天线需要厚衬底和多层。对于标准基板技术的大批量生产和可接受的良率，这种针对消费市场的解决方案以前没有尝试过。在这项工作中，我们提出了一种新颖的多核封装方法，以实现基于标准PCB/基板技术的独特且具有成本效益的解决方案。我们用一个尺寸为30mm x 50mm x 1.5mm的完整毫米波射频模块板来演示这一点。它由4 × 8单元的大面积双极化双频(28GHz和39GHz)堆叠贴片天线阵列和完全集成的系统级封装(sip)以及所有热学和机械功能组成。该方案实现了非常高的交叉极化鉴别比(>25dB)，这对双极化网络的MIMO操作至关重要。该工作包括验证适合低成本毫米波5G CPE(客户端设备)和基站应用的设计和封装概念的测量。
{"title":"Novel Multicore PCB and Substrate Solutions for Ultra Broadband Dual Polarized Antennas for 5G Millimeter Wave Covering 28GHz & 39GHz Range","authors":"T. Thai, S. Dalmia, Josef Hagn, Pouya Talebbeydokhti, Yossi Tsfati","doi":"10.1109/ECTC.2019.00149","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00149","url":null,"abstract":"5G millimeter wave (mmWave) communications that enables Gbps data channels often require broadband operation with dual polarization in multi frequency ranges (27-30, and 37-40GHz). Additionally, access points and base stations need large high gain antenna arrays and consistent radiation patterns across operation frequencies for ease of beam scanning control. Many stacked patch antennas were proposed as the solution. However, broadband patch antennas require thick substrate and multiple layers. For high volume production in standard substrate technology with acceptable yield, such solution targeting the consumer market has not been attempted previously. In this work, we present a novel multicore packaging approach to realize a unique and cost effective solution based on standard PCB/ Substrate technology. We demonstrate this with a complete mmWave RF module board with dimensions of 30mm x 50mm x 1.5mm. It consists of a large area dual polarization dual frequency (28GHz and 39GHz) stacked patch antenna array of 4x8 elements and fully integrated Systems-In-Package (SIPs) along with all the thermal and mechanical functions. This solution achieves a very high cross polarization discrimination ratio (>25dB), which is critical in the MIMO operation of the dual polarization network. The work includes measurements to validate the design and the packaging concept suitable for low cost mmWave 5G CPE (Customer Premises Equipment) and base station applications.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"45 1","pages":"954-959"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84767785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Sivasubramony, A. Zachariah, M. Alhendi, M. Yadav, P. Borgesen, M. Poliks, N. Stoffel, D. Shaddock, L. Yin
Highly stretchable, bio-compatible interconnects are of particular interest for medical and military applications as Wearable Performance Monitors (WPMs) and sensors. Screen printed trace interconnects on highly compliant Thermoplastic Polyurethanes (TPU) provides a low cost, viable option. But these stretchability has high ramification on the reliability aspects of WPM construction. In this paper, we perform the reliability testing of two screen printed inks under repeated mechanical loads 'as-printed' and after exposure to temperature and humidity.
{"title":"Assessing the Reliability of Highly Stretchable Interconnects for Flexible Hybrid Electronics","authors":"R. Sivasubramony, A. Zachariah, M. Alhendi, M. Yadav, P. Borgesen, M. Poliks, N. Stoffel, D. Shaddock, L. Yin","doi":"10.1109/ECTC.2019.00122","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00122","url":null,"abstract":"Highly stretchable, bio-compatible interconnects are of particular interest for medical and military applications as Wearable Performance Monitors (WPMs) and sensors. Screen printed trace interconnects on highly compliant Thermoplastic Polyurethanes (TPU) provides a low cost, viable option. But these stretchability has high ramification on the reliability aspects of WPM construction. In this paper, we perform the reliability testing of two screen printed inks under repeated mechanical loads 'as-printed' and after exposure to temperature and humidity.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"42 1","pages":"768-776"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90612286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pranav Ambhore, U. Mogera, Boris Vaisband, Ujash Shah, T. Fisher, M. Goorsky, S. Iyer
High-density placement of dies on the Silicon Interconnect Fabric (Si-IF) demands high power delivery (1 W/mm2) which in turn generates intense heat (~0.5-0.7 W/mm2). To meet this power requirement and manage its thermal dissipation, we have introduced a novel architecture called PowerTherm which involves the attachment of electrically isolated copper terminal blocks to the back side of the Si-IF. The terminal blocks perform a dual function: they deliver high current at mission voltage and cool the Si-IF either passively or actively. This paper deals with PowerTherm bonding process and its characterization. The terminal blocks were attached to electrodeposited Cu on Si using thermocompression bonding in atmospheric conditions, however with confined air flow. Shear strength of ~ 17 MPa was achieved when the bonding was performed at the optimized conditions.
{"title":"PowerTherm Attach Process for Power Delivery and Heat Extraction in the Silicon-Interconnect Fabric Using Thermocompression Bonding","authors":"Pranav Ambhore, U. Mogera, Boris Vaisband, Ujash Shah, T. Fisher, M. Goorsky, S. Iyer","doi":"10.1109/ECTC.2019.00247","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00247","url":null,"abstract":"High-density placement of dies on the Silicon Interconnect Fabric (Si-IF) demands high power delivery (1 W/mm2) which in turn generates intense heat (~0.5-0.7 W/mm2). To meet this power requirement and manage its thermal dissipation, we have introduced a novel architecture called PowerTherm which involves the attachment of electrically isolated copper terminal blocks to the back side of the Si-IF. The terminal blocks perform a dual function: they deliver high current at mission voltage and cool the Si-IF either passively or actively. This paper deals with PowerTherm bonding process and its characterization. The terminal blocks were attached to electrodeposited Cu on Si using thermocompression bonding in atmospheric conditions, however with confined air flow. Shear strength of ~ 17 MPa was achieved when the bonding was performed at the optimized conditions.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"30 1","pages":"1605-1610"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78146332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chuei-Tang Wang, J. Hsieh, V. Chang, Shih-Ya Huang, T. Ko, H. Pu, Douglas C. H. Yu
Heterogeneous integration has attracted much attention for high performance computing (HPC) since artificial intelligence (AI) accelerators surged. The technologies for heterogeneous integration, such as silicon interposer (2.5D), fan-out wafer-level-packaging (FOWLP), and organic substrate, have been proposed to integrate logic-logic or logic-HBM chips in the AI system for performance and cost benefits. However, the tremendous data flow in 5G era requires higher data rate and bandwidth for the extensive die-to-die communication. Therefore, a BEOL-scale re-distributed layer (RDL) technology should be developed to satisfy the requirements. In this paper, a novel ultra-high-density InFO (InFO_UHD) technology with submicron RDL is developed to provide high interconnect density and bandwidth for logic-logic system. The bandwidth density can achieve record high 10 Tbps/mm at line width and spacing (L/S) of 0.8/0.8 um and length of 500 um, for a logic-logic system using simplified IO driver. Using the technology in logic-memory system, we found that the scaling of RDL thickness, L/S, and dielectric thickness can mitigate ring-back problems in the eye diagram of organic substrate. Given HBM2 specification, the bandwidth density can achieve more than 0.4 Tbps/mm from dramatically improved signal integrity. Finally, power efficiency, in the metric of energy per bit, of the interconnect technology under simplified IO driver and HBM2 driver condition was calculated and compared with other technology, respectively.
{"title":"Signal Integrity of Submicron InFO Heterogeneous Integration for High Performance Computing Applications","authors":"Chuei-Tang Wang, J. Hsieh, V. Chang, Shih-Ya Huang, T. Ko, H. Pu, Douglas C. H. Yu","doi":"10.1109/ECTC.2019.00109","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00109","url":null,"abstract":"Heterogeneous integration has attracted much attention for high performance computing (HPC) since artificial intelligence (AI) accelerators surged. The technologies for heterogeneous integration, such as silicon interposer (2.5D), fan-out wafer-level-packaging (FOWLP), and organic substrate, have been proposed to integrate logic-logic or logic-HBM chips in the AI system for performance and cost benefits. However, the tremendous data flow in 5G era requires higher data rate and bandwidth for the extensive die-to-die communication. Therefore, a BEOL-scale re-distributed layer (RDL) technology should be developed to satisfy the requirements. In this paper, a novel ultra-high-density InFO (InFO_UHD) technology with submicron RDL is developed to provide high interconnect density and bandwidth for logic-logic system. The bandwidth density can achieve record high 10 Tbps/mm at line width and spacing (L/S) of 0.8/0.8 um and length of 500 um, for a logic-logic system using simplified IO driver. Using the technology in logic-memory system, we found that the scaling of RDL thickness, L/S, and dielectric thickness can mitigate ring-back problems in the eye diagram of organic substrate. Given HBM2 specification, the bandwidth density can achieve more than 0.4 Tbps/mm from dramatically improved signal integrity. Finally, power efficiency, in the metric of energy per bit, of the interconnect technology under simplified IO driver and HBM2 driver condition was calculated and compared with other technology, respectively.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"103 1","pages":"688-694"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72892954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Huayan Wang, Jing Wang, Jiefeng Xu, Van-Lai Pham, K. Pan, Seungbae Park, Hohyun Lee, G. Refai-Ahmed
The conversion from using tin-lead solder joint to lead-free solder joint has raised many pad cratering failures for electronics manufacturing. This phenomenon has become more severe to the 2.5D package which has a large heatsink attached on the top. The pad cratering issue has been found during testing, handling or transport due to a single overload. The package qualification process requires that it passes the board level drop test before shipping, however, this doesn't always guarantee that the package will survive from product level drop, especially for a complicated design product. Many types of research have been conducted to improve the package's board-level pad cratering reliability, few emphases were put on the product design. The aim of the present study is to evaluate several product design parameters with respect to PCB stress, using numerical methods. Several different design variables, such as reinforcement structure, heatsink size, pad design, were studied. Data are presented to show the effects of the above factors and to highlight the main factor to cause the pad cratering failure.
{"title":"Product Level Design Optimization for 2.5D Package Pad Cratering Reliability During Drop Impact","authors":"Huayan Wang, Jing Wang, Jiefeng Xu, Van-Lai Pham, K. Pan, Seungbae Park, Hohyun Lee, G. Refai-Ahmed","doi":"10.1109/ECTC.2019.00323","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00323","url":null,"abstract":"The conversion from using tin-lead solder joint to lead-free solder joint has raised many pad cratering failures for electronics manufacturing. This phenomenon has become more severe to the 2.5D package which has a large heatsink attached on the top. The pad cratering issue has been found during testing, handling or transport due to a single overload. The package qualification process requires that it passes the board level drop test before shipping, however, this doesn't always guarantee that the package will survive from product level drop, especially for a complicated design product. Many types of research have been conducted to improve the package's board-level pad cratering reliability, few emphases were put on the product design. The aim of the present study is to evaluate several product design parameters with respect to PCB stress, using numerical methods. Several different design variables, such as reinforcement structure, heatsink size, pad design, were studied. Data are presented to show the effects of the above factors and to highlight the main factor to cause the pad cratering failure.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"37 1","pages":"2343-2348"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82537957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper explores polylithic integration of heterogeneous dice (chiplets) for high-density electronic systems. In this approach, stitch-chips are used to enable 2.5D integration by providing dense signal pathways between assembled 'anchor chips,' while surface-embedded chips provide 3D face-to-face electrical interconnection with corresponding anchor chips. Multi-height Compressible MicroInterconnects (CMIs) are used to enable low-loss and mechanically robust interfaces between the anchor chips and the stitch-chips as well as the surface-embedded chips. Fabrication and assembly of a testbed is reported and demonstrates robust interconnection. In an effort to characterize the CMIs and stitch-chip channels at high-frequency, electromagnetic simulations are carried out and demonstrate less than 0.6 dB insertion loss for 90 µm tall CMIs and 500 µm long channels on a fused silica stitch-chip.
{"title":"Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching","authors":"Paul K. Jo, Ting Zheng, M. Bakir","doi":"10.1109/ECTC.2019.00278","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00278","url":null,"abstract":"This paper explores polylithic integration of heterogeneous dice (chiplets) for high-density electronic systems. In this approach, stitch-chips are used to enable 2.5D integration by providing dense signal pathways between assembled 'anchor chips,' while surface-embedded chips provide 3D face-to-face electrical interconnection with corresponding anchor chips. Multi-height Compressible MicroInterconnects (CMIs) are used to enable low-loss and mechanically robust interfaces between the anchor chips and the stitch-chips as well as the surface-embedded chips. Fabrication and assembly of a testbed is reported and demonstrates robust interconnection. In an effort to characterize the CMIs and stitch-chip channels at high-frequency, electromagnetic simulations are carried out and demonstrate less than 0.6 dB insertion loss for 90 µm tall CMIs and 500 µm long channels on a fused silica stitch-chip.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"21 2 1","pages":"1803-1808"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82912148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Toshiki Iwai, T. Sakai, D. Mizutani, S. Sakuyama, Kenji Iida, T. Inaba, H. Fujisaki, A. Tamura, Yoshinori Miyazawa
Silicon interposer (Si-IP) technology has been used in accelerated processing units such as graphic processing units in high-performance computing because it can package a system-on-chip and high bandwidth memories. However, the conventional Si-IP has difficulty developing larger packages because of the mismatch in the coefficient thermal expansions (CTE) of the Si-IP and the organic substrate. Therefore, the Si-IP has limited capacity for improving computing performance by the application which requires more chips. We developed a multilayer glass substrate (Glass-ST) that features a stacked glass core and propose to apply this Glass-ST to a computer board. The proposed structure has no CTE mismatch and can use high density wiring. Thus, the Glass-ST enables the assembly of more large chips than is possible using the conventional Si-IP. In this study, we prepared a 100X100 mm Glass-ST with a 5/5 µm line/space and 20 µmΦ vias. We mounted nine 21X21 mm chips with 40 µm pitch micro bumps. The results revealed that conformal plated through glass vias and a fine wiring pattern had been fabricated in the Glass-ST, and that the nine chips and Glass-ST were connected by micro bumps. The maximum warpage of the nine chips was 23 µm between temperatures of 30°C and 250°C. This means that the Glass-ST can mount chips with micro bumps due to the very slight resulting warpage. In addition, we performed thermomechanical simulation to investigate the stress experienced by the micro bumps. The results show that the maximum stresses of micro bumps with pitches ranging between 10 µm and 55 um are very similar to that of 40 µm pitch micro bumps with which the real sample was packaged. We believe the improvements in the computing performance are significant by the Glass-ST technology compared to that of the conventional Si-IP technology.
{"title":"Multilayer Glass Substrate with High Density Via Structure for All Inorganic Multi-chip Module","authors":"Toshiki Iwai, T. Sakai, D. Mizutani, S. Sakuyama, Kenji Iida, T. Inaba, H. Fujisaki, A. Tamura, Yoshinori Miyazawa","doi":"10.1109/ECTC.2019.00301","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00301","url":null,"abstract":"Silicon interposer (Si-IP) technology has been used in accelerated processing units such as graphic processing units in high-performance computing because it can package a system-on-chip and high bandwidth memories. However, the conventional Si-IP has difficulty developing larger packages because of the mismatch in the coefficient thermal expansions (CTE) of the Si-IP and the organic substrate. Therefore, the Si-IP has limited capacity for improving computing performance by the application which requires more chips. We developed a multilayer glass substrate (Glass-ST) that features a stacked glass core and propose to apply this Glass-ST to a computer board. The proposed structure has no CTE mismatch and can use high density wiring. Thus, the Glass-ST enables the assembly of more large chips than is possible using the conventional Si-IP. In this study, we prepared a 100X100 mm Glass-ST with a 5/5 µm line/space and 20 µmΦ vias. We mounted nine 21X21 mm chips with 40 µm pitch micro bumps. The results revealed that conformal plated through glass vias and a fine wiring pattern had been fabricated in the Glass-ST, and that the nine chips and Glass-ST were connected by micro bumps. The maximum warpage of the nine chips was 23 µm between temperatures of 30°C and 250°C. This means that the Glass-ST can mount chips with micro bumps due to the very slight resulting warpage. In addition, we performed thermomechanical simulation to investigate the stress experienced by the micro bumps. The results show that the maximum stresses of micro bumps with pitches ranging between 10 µm and 55 um are very similar to that of 40 µm pitch micro bumps with which the real sample was packaged. We believe the improvements in the computing performance are significant by the Glass-ST technology compared to that of the conventional Si-IP technology.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"26 1","pages":"1952-1957"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73914954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thermocompression bonding (TCB) process is now being adopted for high density interconnections but the necessity of applying force and heat causes a lot of problems, such as warpage-induced defects, cracking of delicate chips and thermal drift. To address the above issues, we proposed a novel bonding technique called microfluidic electroless interconnection (MELI) process to directly fabricate interconnection between Cu pillars at the temperature below 80°C and without applying any pressure on the chips. It has been shown in our previous researches that the MELI process using electroless Ni and electroless Au could bond vertical interconnection under controlled flow. In order to extend the application range of the MELI to fine pitch, in this study we analyze the feasibility of selective electroless deposition in microchannel by adding stabilizers into electroless Ni and electroless Au solution. Electroless plating can provide a uniform conformal coating on all parts of the surface that have been catalytically activated. However, the extended coating from the sides of the Cu pillar bump shortens the interconnect pitch, which may cause the risk of bridging. In this paper, we successfully achieve selective electroless Ni plating in microchannel by adding 1.5 ppm of lead acetate into the plating bath. As for electroless Au plating, selective deposition in the microchannel can be accomplished by narrowing the gap. In summary, the innovative MELI process provides a low-temperature and pressureless fine pitch bonding technique.
{"title":"Low Temperature and Pressureless Microfluidic Electroless Bonding Process for Vertical Interconnections","authors":"H. Hung, Sean Yang, I. Weng, Yan-Hao Chen, C. Kao","doi":"10.1109/ECTC.2019.00265","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00265","url":null,"abstract":"Thermocompression bonding (TCB) process is now being adopted for high density interconnections but the necessity of applying force and heat causes a lot of problems, such as warpage-induced defects, cracking of delicate chips and thermal drift. To address the above issues, we proposed a novel bonding technique called microfluidic electroless interconnection (MELI) process to directly fabricate interconnection between Cu pillars at the temperature below 80°C and without applying any pressure on the chips. It has been shown in our previous researches that the MELI process using electroless Ni and electroless Au could bond vertical interconnection under controlled flow. In order to extend the application range of the MELI to fine pitch, in this study we analyze the feasibility of selective electroless deposition in microchannel by adding stabilizers into electroless Ni and electroless Au solution. Electroless plating can provide a uniform conformal coating on all parts of the surface that have been catalytically activated. However, the extended coating from the sides of the Cu pillar bump shortens the interconnect pitch, which may cause the risk of bridging. In this paper, we successfully achieve selective electroless Ni plating in microchannel by adding 1.5 ppm of lead acetate into the plating bath. As for electroless Au plating, selective deposition in the microchannel can be accomplished by narrowing the gap. In summary, the innovative MELI process provides a low-temperature and pressureless fine pitch bonding technique.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"363 1","pages":"1729-1734"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76560486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kwang-Seong Choi, Y. Eom, Seok-Hwan Moon, Jiho Joo, leeseul Jeong, Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim, G. Yoon, Kwang-Hee Lee, Chul-Hee Lee, Geun-Sik Ahn, Moo-Sup Shim
A LABC (Laser-Assisted Bonding with Compression) bonder and NCF (Non-Conductive Film) were developed to increase the productivity of the bonding process for the advanced microelectronic packaging technology. The design features of a LABC make its UPH above 1,000. The NCF was applied to both of LAB and TCB (Thermal Compression Bonding Technology). The 780µm-thick daisy chain top and bottom chips with the minimum pitch of 30µm and bump number of about 27,000 were prepared and tested to verify the LABC and NCF technology. The effects of the laser power on the joints quality after the LABC bonding process were investigated and compared with the joints formed by the TCB technology. Finally, the SAT (Scanning Acoustic Tomography) images of the test vehicles before and after the TCO (Pressurized oven) were observed to check the voids in the NCF after the LABC bonding process.
{"title":"Enhanced Performance of Laser-Assisted Bonding with Compression (LABC) Compared with Thermal Compression Bonding (TCB) Technology","authors":"Kwang-Seong Choi, Y. Eom, Seok-Hwan Moon, Jiho Joo, leeseul Jeong, Kwangjoo Lee, Jung Hak Kim, Ju Hyeon Kim, G. Yoon, Kwang-Hee Lee, Chul-Hee Lee, Geun-Sik Ahn, Moo-Sup Shim","doi":"10.1109/ECTC.2019.00037","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00037","url":null,"abstract":"A LABC (Laser-Assisted Bonding with Compression) bonder and NCF (Non-Conductive Film) were developed to increase the productivity of the bonding process for the advanced microelectronic packaging technology. The design features of a LABC make its UPH above 1,000. The NCF was applied to both of LAB and TCB (Thermal Compression Bonding Technology). The 780µm-thick daisy chain top and bottom chips with the minimum pitch of 30µm and bump number of about 27,000 were prepared and tested to verify the LABC and NCF technology. The effects of the laser power on the joints quality after the LABC bonding process were investigated and compared with the joints formed by the TCB technology. Finally, the SAT (Scanning Acoustic Tomography) images of the test vehicles before and after the TCO (Pressurized oven) were observed to check the voids in the NCF after the LABC bonding process.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"68 1","pages":"197-203"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89083138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
John P. Mudrick, Jonatan A. Sierra-Suarez, M. Jordan, T. Friedmann, R. Jarecki, M. Henry
Direct bond interconnect (DBI) processes enable chip to chip, low resistivity electrical connections for 2.5-D scaling of electrical circuits and heterogenous integration. This work describes SiO2/Cu DBI technology with Cu interconnect performance investigated over a range of inter-die Cu gap heights and post-bond annealing temperatures. Chemical mechanical polishing (CMP) generates wafers with a controlled Cu recess relative to the SiO2 surface, yielding die pairs with inter-die Cu gap heights ranging between 9 and 47 nm. Bonded die with different gap heights show similar per-connection resistance after annealing at 400 degrees Celsius but annealing at lower temperatures between 250 and 350 degrees Celsius results in failing or high-resistance interconnects with intermediate gaps showing lowest resistance. Cross-section scanning electron microscope (SEM) image analysis shows that the microstructure is largely independent of post-bond annealing temperature, suggesting that the temperature behavior is due to nanoscale scale interfacial effects not observable by SEM. The bond strength is affirmed by successful step-wise mechanical and chemical removal of the handle silicon layer to reveal metal from both die. This work demonstrates a 2.5-D integration method using a 3 micron Cu DBI process on a 7.5 micron pitch with electrical contacts ranging between 3.8 and 4.8 Ohms per contact plug.
{"title":"Sub-10µm Pitch Hybrid Direct Bond Interconnect Development for Die-to-Die Hybridization","authors":"John P. Mudrick, Jonatan A. Sierra-Suarez, M. Jordan, T. Friedmann, R. Jarecki, M. Henry","doi":"10.1109/ECTC.2019.00103","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00103","url":null,"abstract":"Direct bond interconnect (DBI) processes enable chip to chip, low resistivity electrical connections for 2.5-D scaling of electrical circuits and heterogenous integration. This work describes SiO2/Cu DBI technology with Cu interconnect performance investigated over a range of inter-die Cu gap heights and post-bond annealing temperatures. Chemical mechanical polishing (CMP) generates wafers with a controlled Cu recess relative to the SiO2 surface, yielding die pairs with inter-die Cu gap heights ranging between 9 and 47 nm. Bonded die with different gap heights show similar per-connection resistance after annealing at 400 degrees Celsius but annealing at lower temperatures between 250 and 350 degrees Celsius results in failing or high-resistance interconnects with intermediate gaps showing lowest resistance. Cross-section scanning electron microscope (SEM) image analysis shows that the microstructure is largely independent of post-bond annealing temperature, suggesting that the temperature behavior is due to nanoscale scale interfacial effects not observable by SEM. The bond strength is affirmed by successful step-wise mechanical and chemical removal of the handle silicon layer to reveal metal from both die. This work demonstrates a 2.5-D integration method using a 3 micron Cu DBI process on a 7.5 micron pitch with electrical contacts ranging between 3.8 and 4.8 Ohms per contact plug.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"648-654"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90061349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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