Teng Sun, R. Spurney, A. Watanabe, P. R. Pulugurtha, H. Sharma, R. Tummala, Furukawa Yoshihiro
Highly-integrated 3D voltage regulators (IVRs) for high-power applications are developed for emerging applications such as AI computing and server. With this 3D process integration, passive components such as inductors and capacitors are embedded into substrates and placed close to the chips, resulting in short power delivery networks (PNDs) and high power efficiency. High-density tantalum capacitors are integrated with high-density magnetic-core inductors to realize IVRs with module thickness around 0.7 mm. By incorporating high-permeability magnetic materials as the cores, the inductors achieved 20X improvement in inductance as compared to air-core inductors. The high inductance allows inductors to be designed with less number of windings, resulting in low component resistance of 5 mΩ. The integrated components have package-compatible terminals that are compatible with electrolytic plating process. The terminals allow them to be connected with low-resistance vias to further reduce parasitic losses and improve the power efficiency. Short PDNs and low-resistance interconnections and low-resistance components make the demonstrated IVRs ideal for high-power density computing applications with high efficiency low-impedance power delivery networks.
{"title":"3D Packaging with Embedded High-Power-Density Passives for Integrated Voltage Regulators","authors":"Teng Sun, R. Spurney, A. Watanabe, P. R. Pulugurtha, H. Sharma, R. Tummala, Furukawa Yoshihiro","doi":"10.1109/ECTC.2019.00201","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00201","url":null,"abstract":"Highly-integrated 3D voltage regulators (IVRs) for high-power applications are developed for emerging applications such as AI computing and server. With this 3D process integration, passive components such as inductors and capacitors are embedded into substrates and placed close to the chips, resulting in short power delivery networks (PNDs) and high power efficiency. High-density tantalum capacitors are integrated with high-density magnetic-core inductors to realize IVRs with module thickness around 0.7 mm. By incorporating high-permeability magnetic materials as the cores, the inductors achieved 20X improvement in inductance as compared to air-core inductors. The high inductance allows inductors to be designed with less number of windings, resulting in low component resistance of 5 mΩ. The integrated components have package-compatible terminals that are compatible with electrolytic plating process. The terminals allow them to be connected with low-resistance vias to further reduce parasitic losses and improve the power efficiency. Short PDNs and low-resistance interconnections and low-resistance components make the demonstrated IVRs ideal for high-power density computing applications with high efficiency low-impedance power delivery networks.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"34 1","pages":"1300-1305"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75061815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reports advanced pre treatment method before seed layer sputtering for Fan Out Panel Level Packaging (FOPLP). To realize high performance semiconductor devices, not only miniaturization of semiconductor chip but also minimizing packaging wiring length is also important. Fan out technology can take more I/O numbers than Fan In technology, so it is one of solution for short distance wiring, low power consumption and high density packaging. This technology originally started with wafer level process, but now its technology is going to spread to larger substrate like over 600mm square[1][2]. Enlarging substrate size is good way to suppress cost of ownership of manufacturing semiconductor devices. FOPLP is a kind of collaboration with front end technology which has fine pitch line and space and back end technology of packaging to realize high density and low cost semiconductor devices. In this technology, seed layer formation for re-distribution layer (RDL) is important to product fine pitch line and space wiring. Dielectric layer between top and bottom wiring is mainly polyimide called photosensitive imageable dielectric (PID) which can make pattern without photoresist. And to form good seed layer on polyimide with sputtering, pre treatment of polyimide is critical. We modified pre treatment for seed layer with sputtering in terms of productivity, adhesion and contact resistance.
{"title":"High Rate and Low Damage Etching Method as Pre Treatment of Seed Layer Sputtering for Fan out Panel Level Packaging","authors":"Tetsushi Fujinaga","doi":"10.1109/ECTC.2019.00062","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00062","url":null,"abstract":"This paper reports advanced pre treatment method before seed layer sputtering for Fan Out Panel Level Packaging (FOPLP). To realize high performance semiconductor devices, not only miniaturization of semiconductor chip but also minimizing packaging wiring length is also important. Fan out technology can take more I/O numbers than Fan In technology, so it is one of solution for short distance wiring, low power consumption and high density packaging. This technology originally started with wafer level process, but now its technology is going to spread to larger substrate like over 600mm square[1][2]. Enlarging substrate size is good way to suppress cost of ownership of manufacturing semiconductor devices. FOPLP is a kind of collaboration with front end technology which has fine pitch line and space and back end technology of packaging to realize high density and low cost semiconductor devices. In this technology, seed layer formation for re-distribution layer (RDL) is important to product fine pitch line and space wiring. Dielectric layer between top and bottom wiring is mainly polyimide called photosensitive imageable dielectric (PID) which can make pattern without photoresist. And to form good seed layer on polyimide with sputtering, pre treatment of polyimide is critical. We modified pre treatment for seed layer with sputtering in terms of productivity, adhesion and contact resistance.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"95 1","pages":"358-362"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74978133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Yakabe, Takuro Watanabe, T. Shimazu, R. Hokari, K. Kurihara
Plastic lenses are utilized for optical communication devices such as AOC (Active Optical Cable), transceivers and connectors in order to improve coupling efficiency. In order to reduce the optical loss of the communication device one must also, reduce the Fresnel loss due to the refractive index of the transparent thermoplastic resin, the typical solution is, use of an Anti-reflection (AR) coating. Although it is possible to greatly lower the reflectance at the end face of the lens by this AR coating, the cost of the device is increased. To solve this problem we propose, reduction of reflectance in the near infrared wavelength band without AR coating by transferring the nanoscale concavo-convex structure through injection molding alone. Furthermore, to achieve low reflectance in various transparent thermoplastic resin, we propose a new method to drastically improve the transferability of the surface shape during injection molding. Utilizing this both methods, we successfully developed surface structure with a concavo-convex of 0.3 µm or more and a 2% or less reflectance at over 1 µm wavelength.
{"title":"Low Surface Reflectance Structure at Near Infrared Wavelength by Injection Molding","authors":"S. Yakabe, Takuro Watanabe, T. Shimazu, R. Hokari, K. Kurihara","doi":"10.1109/ECTC.2019.00270","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00270","url":null,"abstract":"Plastic lenses are utilized for optical communication devices such as AOC (Active Optical Cable), transceivers and connectors in order to improve coupling efficiency. In order to reduce the optical loss of the communication device one must also, reduce the Fresnel loss due to the refractive index of the transparent thermoplastic resin, the typical solution is, use of an Anti-reflection (AR) coating. Although it is possible to greatly lower the reflectance at the end face of the lens by this AR coating, the cost of the device is increased. To solve this problem we propose, reduction of reflectance in the near infrared wavelength band without AR coating by transferring the nanoscale concavo-convex structure through injection molding alone. Furthermore, to achieve low reflectance in various transparent thermoplastic resin, we propose a new method to drastically improve the transferability of the surface shape during injection molding. Utilizing this both methods, we successfully developed surface structure with a concavo-convex of 0.3 µm or more and a 2% or less reflectance at over 1 µm wavelength.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"31 1","pages":"1764-1769"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76088972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The drive for multi-chip module (MCM) packaging technology essentially stems from the ever-increasing demand for miniaturization of power electronics. While promising, MCM packaging technologies present considerable design challenges (viz. electrical, thermal, reliability and manufacturing/assembly) if system co-design techniques are not adopted early in the design process. In this paper we present the electrical system co-design and measurement validation results of a high-efficiency, single channel, integrated FET, synchronous buck converter packaged in a 40-pin 7.00mm × 5.00mm MCM-in-LQFN-type innovative package. Due to the complex 3D level of integration of the monolithic control, drive circuitry, and the two discrete N-channel NexFETTM power MOSFETs, electromagnetic interactions, between die, package, and PCB, are exacerbated with potential impact to system-level performance. We detail here how optimization of the system, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation methodology. Laboratory measurements on an integrated high current (40A) synchronous step-down converter are presented that validate the integrity of the co-design modeling and simulation methodology.
多芯片模块(MCM)封装技术的发展主要源于对电力电子器件小型化日益增长的需求。虽然MCM封装技术很有前途，但如果在设计过程的早期不采用系统协同设计技术，那么MCM封装技术将面临相当大的设计挑战(即电气、热、可靠性和制造/组装)。本文介绍了一种高效、单通道、集成FET、同步降压转换器的电气系统协同设计和测量验证结果，该转换器封装在40引脚7.00mm × 5.00mm mcm - In - lqfn型创新封装中。由于单片控制、驱动电路和两个分立n通道NexFETTM功率mosfet的复杂3D级集成，加剧了芯片、封装和PCB之间的电磁相互作用，并对系统级性能产生潜在影响。我们在这里详细介绍了如何通过耦合电路-电磁协同设计建模和仿真方法来实现系统的优化。对集成大电流(40A)同步降压转换器进行了实验室测量，验证了协同设计建模和仿真方法的完整性。
{"title":"System Co-Design of a High Current (40A) Synchronous Step-Down Converter in an Innovative Multi-chip Module (MCM) LQFN-Type Packaging Technology","authors":"T. Harrison, Jie Chen, R. Murugan","doi":"10.1109/ECTC.2019.00254","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00254","url":null,"abstract":"The drive for multi-chip module (MCM) packaging technology essentially stems from the ever-increasing demand for miniaturization of power electronics. While promising, MCM packaging technologies present considerable design challenges (viz. electrical, thermal, reliability and manufacturing/assembly) if system co-design techniques are not adopted early in the design process. In this paper we present the electrical system co-design and measurement validation results of a high-efficiency, single channel, integrated FET, synchronous buck converter packaged in a 40-pin 7.00mm × 5.00mm MCM-in-LQFN-type innovative package. Due to the complex 3D level of integration of the monolithic control, drive circuitry, and the two discrete N-channel NexFETTM power MOSFETs, electromagnetic interactions, between die, package, and PCB, are exacerbated with potential impact to system-level performance. We detail here how optimization of the system, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation methodology. Laboratory measurements on an integrated high current (40A) synchronous step-down converter are presented that validate the integrity of the co-design modeling and simulation methodology.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"245 1","pages":"1653-1659"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72867274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mike Tsai, Ryan Chiu, D. Huang, F. Kao, Eric He, J. Chen, Simon Chen, Jensen Tsai, Yu-Po Wang
Recently, based on next generation wireless connectivity system evolution, there are more and more components combined into smartphone of Radio Frequency (RF) and Front-End Module (FEM) for up-coming 5G application. Also, the Internet of Things (IoT) continue to grow up due to the electronics industry is moved maturely on the mobile computing market for now. Both of IoT and 5G connectivity devices are required small form factor and high thermal performance. A 3D System in Package (3D SiP) including different approach, such as the double side molding technology and antenna in package (AiP) which is a combination solutions for these requirements. In this paper, the 3D SiP package platform will use dual side Surface Mount Technology (SMT) technology and 3D structure of double side molding to shrink overall package size of 3D SiP module. The calculation of package size can be shrunk around 60% area, package size can be reduced from 8 x 8mm to 6 x 6mm. From warpage and thermal performance are proceed simulation and measurement. And experiment including the DOE (Design of Experiment) study for molding process with different high thermal epoxy molding compound (EMC) selection to verify warpage performance. By utilizing advanced package structure solutions such as high speed SMT placement, Cu substrate with thermal pad for high thermal, double side molding, a 3D double side SiP module can provide a unique opportunity to address cost, performance, and time-to-market. Considering the limitations of power consumption and form factor, smart phone front end module will become the major requirements for SiP platforms. The characterization analysis will utilize simulation methodology and measurement correction for warpage and thermal performance comparison. Also, will proceed the typical reliability testing (Temperature Cycle Test, High Temperature Storage Test, un-bias HAST) results as a verification for 3D double side SiP structure. Finally, this paper will find out the suitable 3D SiP structure and feasibility data for future IoT and 5G devices application.
{"title":"Innovative Packaging Solutions of 3D Double Side Molding with System in Package for IoT and 5G Application","authors":"Mike Tsai, Ryan Chiu, D. Huang, F. Kao, Eric He, J. Chen, Simon Chen, Jensen Tsai, Yu-Po Wang","doi":"10.1109/ECTC.2019.00111","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00111","url":null,"abstract":"Recently, based on next generation wireless connectivity system evolution, there are more and more components combined into smartphone of Radio Frequency (RF) and Front-End Module (FEM) for up-coming 5G application. Also, the Internet of Things (IoT) continue to grow up due to the electronics industry is moved maturely on the mobile computing market for now. Both of IoT and 5G connectivity devices are required small form factor and high thermal performance. A 3D System in Package (3D SiP) including different approach, such as the double side molding technology and antenna in package (AiP) which is a combination solutions for these requirements. In this paper, the 3D SiP package platform will use dual side Surface Mount Technology (SMT) technology and 3D structure of double side molding to shrink overall package size of 3D SiP module. The calculation of package size can be shrunk around 60% area, package size can be reduced from 8 x 8mm to 6 x 6mm. From warpage and thermal performance are proceed simulation and measurement. And experiment including the DOE (Design of Experiment) study for molding process with different high thermal epoxy molding compound (EMC) selection to verify warpage performance. By utilizing advanced package structure solutions such as high speed SMT placement, Cu substrate with thermal pad for high thermal, double side molding, a 3D double side SiP module can provide a unique opportunity to address cost, performance, and time-to-market. Considering the limitations of power consumption and form factor, smart phone front end module will become the major requirements for SiP platforms. The characterization analysis will utilize simulation methodology and measurement correction for warpage and thermal performance comparison. Also, will proceed the typical reliability testing (Temperature Cycle Test, High Temperature Storage Test, un-bias HAST) results as a verification for 3D double side SiP structure. Finally, this paper will find out the suitable 3D SiP structure and feasibility data for future IoT and 5G devices application.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"73 1","pages":"700-706"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84268315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Madanipour, Y. Kim, C. Kim, N. Shahane, D. Mishra, L. Nguyen
This paper describes the kinetic and microstructural mechanism of electromigration (EM) failure found in low-profile solder joints where EM and intermetallic phase formation compete for the same volume of Sn. The low-profile solder joint used in our study was made of 20-25um thick solder situated in between a Cu pillar and a Ni coated Cu lead frame (LF). The samples were EM tested in a temperature range of 140-170oC with the current densities varying between 35-45 KA/cm2 in an oil bath to induce failure without Joule Heat induced artifacts. Our studies on EM failure kinetics and microstructural mechanism have produced two key findings. The first finding suggests that the EM diffusivity (Z*D) of diffusing species (Sn, Ni, Cu) in the solder matrix can be uniquely ranked from microstructural analysis, and it is estimated to be (Z*D) Cu> (Z*D) Sn>(Z*D) Ni. This difference in EM diffusivity causes Cu-Sn and Ni-Sn intermetallic compounds (IMC) to develop in distinctively different manners under EM, leading to different EM failure mechanisms. The second finding is that EM in low-profile solder joints consists of multiple failure stages: a) with EM-related voiding in Sn dominating at lower temperatures; while b) thermally-induced IMC growth and invasion competes with EM-induced Sn voiding at high temperatures leading to the complete failure of each joint.
{"title":"Effect of Intermetallic Compound Growth on Electromigration Failure Mechanism in Low-Profile Solder Joints","authors":"H. Madanipour, Y. Kim, C. Kim, N. Shahane, D. Mishra, L. Nguyen","doi":"10.1109/ECTC.2019.00204","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00204","url":null,"abstract":"This paper describes the kinetic and microstructural mechanism of electromigration (EM) failure found in low-profile solder joints where EM and intermetallic phase formation compete for the same volume of Sn. The low-profile solder joint used in our study was made of 20-25um thick solder situated in between a Cu pillar and a Ni coated Cu lead frame (LF). The samples were EM tested in a temperature range of 140-170oC with the current densities varying between 35-45 KA/cm2 in an oil bath to induce failure without Joule Heat induced artifacts. Our studies on EM failure kinetics and microstructural mechanism have produced two key findings. The first finding suggests that the EM diffusivity (Z*D) of diffusing species (Sn, Ni, Cu) in the solder matrix can be uniquely ranked from microstructural analysis, and it is estimated to be (Z*D) Cu> (Z*D) Sn>(Z*D) Ni. This difference in EM diffusivity causes Cu-Sn and Ni-Sn intermetallic compounds (IMC) to develop in distinctively different manners under EM, leading to different EM failure mechanisms. The second finding is that EM in low-profile solder joints consists of multiple failure stages: a) with EM-related voiding in Sn dominating at lower temperatures; while b) thermally-induced IMC growth and invasion competes with EM-induced Sn voiding at high temperatures leading to the complete failure of each joint.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"22 1","pages":"1316-1323"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84330232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Structural optimization is a necessary procedure to make progress toward mass production for a new device. Both of structural robustness and superior performance are targets for structural optimization. In this study the structural weakness of a complementary metal oxide semiconductor (CMOS) - microelectromechanical systems (MEMS) microphone chip with 4 by 3 microphone cells by TSMC 0.18 µm CMOS process during thermal loading was identified first by thermal cycling test and thermal stress analysis; then, the optimal structures of the microphone were discussed from viewpoints of thermal stress and sensitivity by Taguchi method. Therein, the finite element (FE) method was adopted for thermal stress analysis and capacitive sensitivity of the microphone was obtained from the equation of sensing capacitance. Moreover, the weakness spots at bottom of the diaphragm in the microphone chip from simulation were verified by the images of scanning electron microscope (SEM) for the chip after 500 cycles of thermal loading in experiment. The results of structural optimization by Taguchi method showed that the microphone with thicker metal and thinner SiO2, wider anchor, and larger diaphragm could reduce the thermal stress in the diaphragm up to 68% than that of the original design. However, for the capacitive sensitivity of microphone chip, the results indicated that the microphone with thicker metal and SiO2, narrower anchor, and larger diaphragm had 5.8 times increase of microphone capacitive sensitivity than that of the original design. This study could provide helpful suggestions for the design and structural robustness of MEMS microphone.
{"title":"Structural Enhancement for a CMOS-MEMS Microphone Under Thermal Loading by Taguchi Method","authors":"Chun-Lin Lu, M. Yeh","doi":"10.1109/ECTC.2019.00260","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00260","url":null,"abstract":"Structural optimization is a necessary procedure to make progress toward mass production for a new device. Both of structural robustness and superior performance are targets for structural optimization. In this study the structural weakness of a complementary metal oxide semiconductor (CMOS) - microelectromechanical systems (MEMS) microphone chip with 4 by 3 microphone cells by TSMC 0.18 µm CMOS process during thermal loading was identified first by thermal cycling test and thermal stress analysis; then, the optimal structures of the microphone were discussed from viewpoints of thermal stress and sensitivity by Taguchi method. Therein, the finite element (FE) method was adopted for thermal stress analysis and capacitive sensitivity of the microphone was obtained from the equation of sensing capacitance. Moreover, the weakness spots at bottom of the diaphragm in the microphone chip from simulation were verified by the images of scanning electron microscope (SEM) for the chip after 500 cycles of thermal loading in experiment. The results of structural optimization by Taguchi method showed that the microphone with thicker metal and thinner SiO2, wider anchor, and larger diaphragm could reduce the thermal stress in the diaphragm up to 68% than that of the original design. However, for the capacitive sensitivity of microphone chip, the results indicated that the microphone with thicker metal and SiO2, narrower anchor, and larger diaphragm had 5.8 times increase of microphone capacitive sensitivity than that of the original design. This study could provide helpful suggestions for the design and structural robustness of MEMS microphone.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"30 1","pages":"1697-1703"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80576159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Watanabe, Yiteng Wang, N. Ogura, P. Raj, V. Smet, M. Tentzeris, R. Tummala
High-bandwidth 5G and 6G communication systems will inevitably migrate to 3D package architectures with backside or embedded dies and antenna-integrated packages for ultra-low losses and smaller footprints. With the trend to such 3D millimeter-wave (mm-wave) packages, the losses from the assembly and through-vias tend to dominate the overall losses. Traditional wirebond and thick solder interconnections lead to large mm-wave interconnect losses that are not acceptable for emerging 5G and 6G communications. This paper focuses on the material syntheses and process development of nanocopper interconnections with ultra-low interconnect losses for chip-last or flip-chip assembly in packages. The first part of the paper introduces the material synthesis of an innovative copper paste with shorter sintering times and temperatures. Optimized conditions are obtained to attain a conductivity of 1.4x10^7 S/m. This is equivalent to 82% increase in conductivity compared to that of solder. The surface roughness is also measured through atomic-force microscopy. Results suggest that the copper paste features higher roughness than that of solders. The second part of this paper discusses the potential of novel nanocopper paste to replace solders as a package assembly material, focusing on the effect of the conductivity and surface roughness with regard to the insertion loss in interconnection bumps. Based on the improved material properties of nanocopper paste, the model shows a 53% reduction in the dB scale at 28 GHz, by employing nanocopper paste. Die shear test for copper paste is also performed to show a high potential to replace solders as a flip-chip assembly material in both printed-circuit-board and mm-wave packaging technologies.
{"title":"Low-Loss Additively-Deposited Ultra-Short Copper-Paste Interconnections in 3D Antenna-Integrated Packages for 5G and IoT Applications","authors":"A. Watanabe, Yiteng Wang, N. Ogura, P. Raj, V. Smet, M. Tentzeris, R. Tummala","doi":"10.1109/ECTC.2019.00152","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00152","url":null,"abstract":"High-bandwidth 5G and 6G communication systems will inevitably migrate to 3D package architectures with backside or embedded dies and antenna-integrated packages for ultra-low losses and smaller footprints. With the trend to such 3D millimeter-wave (mm-wave) packages, the losses from the assembly and through-vias tend to dominate the overall losses. Traditional wirebond and thick solder interconnections lead to large mm-wave interconnect losses that are not acceptable for emerging 5G and 6G communications. This paper focuses on the material syntheses and process development of nanocopper interconnections with ultra-low interconnect losses for chip-last or flip-chip assembly in packages. The first part of the paper introduces the material synthesis of an innovative copper paste with shorter sintering times and temperatures. Optimized conditions are obtained to attain a conductivity of 1.4x10^7 S/m. This is equivalent to 82% increase in conductivity compared to that of solder. The surface roughness is also measured through atomic-force microscopy. Results suggest that the copper paste features higher roughness than that of solders. The second part of this paper discusses the potential of novel nanocopper paste to replace solders as a package assembly material, focusing on the effect of the conductivity and surface roughness with regard to the insertion loss in interconnection bumps. Based on the improved material properties of nanocopper paste, the model shows a 53% reduction in the dB scale at 28 GHz, by employing nanocopper paste. Die shear test for copper paste is also performed to show a high potential to replace solders as a flip-chip assembly material in both printed-circuit-board and mm-wave packaging technologies.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"37 1","pages":"972-976"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81176508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hanmin Lee, Seyong Lee, Sangmyung Shin, Taejin Choi, SooIn Park, K. Paik
In this study, solder bump flip chip assembly using NCFs was evaluated for Sn-Ag solder bumps. Flip chip bonding was performed using an isothermal Thermo-Compression (TC) bonding method for 5 seconds. Solder bump joints were evaluated by adjusting the curing properties such as curing onset, peak temperature, and degree of curing and viscosities of NCFs using curing agents and silica contents. And then, the degree of cure and viscosity approximations were conducted to define the precise viscosity of NCFs at the solder melting temperature using measured degree of cures at various bonding temperatures and viscosities. Finally, high temperature and humidity test (85RH%/85°C test) and temperature cycling (T/C) test were performed to evaluate the thermo-mechanical reliability performance depending on solder joint.
{"title":"Effects of the Curing Properties and Viscosities of Non-Conductive Films (NCFs) on the Sn-Ag Solder Bump Joint Morphology and Reliability","authors":"Hanmin Lee, Seyong Lee, Sangmyung Shin, Taejin Choi, SooIn Park, K. Paik","doi":"10.1109/ECTC.2019.000-5","DOIUrl":"https://doi.org/10.1109/ECTC.2019.000-5","url":null,"abstract":"In this study, solder bump flip chip assembly using NCFs was evaluated for Sn-Ag solder bumps. Flip chip bonding was performed using an isothermal Thermo-Compression (TC) bonding method for 5 seconds. Solder bump joints were evaluated by adjusting the curing properties such as curing onset, peak temperature, and degree of curing and viscosities of NCFs using curing agents and silica contents. And then, the degree of cure and viscosity approximations were conducted to define the precise viscosity of NCFs at the solder melting temperature using measured degree of cures at various bonding temperatures and viscosities. Finally, high temperature and humidity test (85RH%/85°C test) and temperature cycling (T/C) test were performed to evaluate the thermo-mechanical reliability performance depending on solder joint.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"45 1","pages":"2278-2283"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81495168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work examines the effect of a metallic cap layer in controlling via extrusion and explores the underlying mechanisms. Ta was deposited as the cap material, which was very effective in reducing the statistical spread of via extrusion. The correlation between extrusion and microstructure of the vias was investigated and compared for the reference uncoated vias and the Ta-capped vias. Thermo-mechanical characterization as well as TEM characterization of the Ta cap/via interface were also carried out. Void formation at grain junctures were observed. The results suggest that mass transport through grain boundaries plays an important role in causing the statistical variation of extrusion, which can be effectively suppressed by the Ta cap. Void formation was also reduced by the cap layer. Additional factors affecting extrusion, including interfacial diffusion and dislocation glide, were also discussed.
{"title":"Study of the Effect and Mechanism of a Cap Layer in Controlling the Statistical Variation of Via Extrusion","authors":"Golareh Jalilvand, Tengfei Jiang","doi":"10.1109/ECTC.2019.00294","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00294","url":null,"abstract":"This work examines the effect of a metallic cap layer in controlling via extrusion and explores the underlying mechanisms. Ta was deposited as the cap material, which was very effective in reducing the statistical spread of via extrusion. The correlation between extrusion and microstructure of the vias was investigated and compared for the reference uncoated vias and the Ta-capped vias. Thermo-mechanical characterization as well as TEM characterization of the Ta cap/via interface were also carried out. Void formation at grain junctures were observed. The results suggest that mass transport through grain boundaries plays an important role in causing the statistical variation of extrusion, which can be effectively suppressed by the Ta cap. Void formation was also reduced by the cap layer. Additional factors affecting extrusion, including interfacial diffusion and dislocation glide, were also discussed.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"1909-1915"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81535924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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