Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185391
T. Budri, J. Klatt
Doped oxide films with phosphorus and boron (PSG/BPSG) are widely used in the semiconductor processing on the first dielectric above FEOL films, to protect transistors from failures due to mobile ionic contamination (Na, Li, K, Mg & Ca). Fluorine doped films are utilized as alternatives to un-doped SiO2 films for lower capacitance at the BEOL for smaller geometry aluminum back end technologies. Several in-line metrology techniques such as XRF and FTIR are utilized to characterize and monitor the integrity of those films but only provide limited information about the films and the dopant distribution. DSIMS/TOFSIMS depth profiles of the entire film stack do provide a clear understanding of dopants distribution and highlight any variations that have been proven to be the cause of failures and eliminate defective device deployment in the field, especially devices utilized in automotive industries.
{"title":"Characterization of Doped Oxide Films PSG/BPSG/FSG via DSIMS in Order to Eliminate Nonzero Kilometer Failures from Semiconductors Used in Automotive Industry : Topic/category: Yield Enhancment/Advanced Metrology","authors":"T. Budri, J. Klatt","doi":"10.1109/ASMC49169.2020.9185391","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185391","url":null,"abstract":"Doped oxide films with phosphorus and boron (PSG/BPSG) are widely used in the semiconductor processing on the first dielectric above FEOL films, to protect transistors from failures due to mobile ionic contamination (Na, Li, K, Mg & Ca). Fluorine doped films are utilized as alternatives to un-doped SiO2 films for lower capacitance at the BEOL for smaller geometry aluminum back end technologies. Several in-line metrology techniques such as XRF and FTIR are utilized to characterize and monitor the integrity of those films but only provide limited information about the films and the dopant distribution. DSIMS/TOFSIMS depth profiles of the entire film stack do provide a clear understanding of dopants distribution and highlight any variations that have been proven to be the cause of failures and eliminate defective device deployment in the field, especially devices utilized in automotive industries.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"46 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89535600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185293
Doug Suerich, Terry Young
Semiconductor cluster tools add an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric-vacuum-atmospheric cycle. These highly automated tools present a complex scheduling challenge where process-specific requirements are balanced against a need to achieve maximum wafer throughput in a fault tolerant manner. Previous work demonstrated that a reinforcement learning algorithm would be suitable for automated generation of efficient planners for simple tools. This investigation looked at how these same techniques could be extended to operate on more complex equipment.
{"title":"Reinforcement Learning for Efficient Scheduling in Complex Semiconductor Equipment","authors":"Doug Suerich, Terry Young","doi":"10.1109/ASMC49169.2020.9185293","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185293","url":null,"abstract":"Semiconductor cluster tools add an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric-vacuum-atmospheric cycle. These highly automated tools present a complex scheduling challenge where process-specific requirements are balanced against a need to achieve maximum wafer throughput in a fault tolerant manner. Previous work demonstrated that a reinforcement learning algorithm would be suitable for automated generation of efficient planners for simple tools. This investigation looked at how these same techniques could be extended to operate on more complex equipment.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86126644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185194
K. Kippes, P. Dunaway, J. Biggs, Ryan Parrot, David Young, Charlie Hill
This poster abstract will focus on environmentally friendly media and packaging solutions engineered by the Transport Materials and Media Engineering (TMME) group within Intel’s Logistics Division. The TMME group has made many improvements that have reduced the environmental impact of our shipping media and packaging materials for our factories thereby reducing our material and freight cost while also reducing our total carbon footprint.
{"title":"Environmental improvements through media packaging","authors":"K. Kippes, P. Dunaway, J. Biggs, Ryan Parrot, David Young, Charlie Hill","doi":"10.1109/ASMC49169.2020.9185194","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185194","url":null,"abstract":"This poster abstract will focus on environmentally friendly media and packaging solutions engineered by the Transport Materials and Media Engineering (TMME) group within Intel’s Logistics Division. The TMME group has made many improvements that have reduced the environmental impact of our shipping media and packaging materials for our factories thereby reducing our material and freight cost while also reducing our total carbon footprint.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"19 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88928402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185385
S. Chowdhury, YiFeng Wu, Likun Shen, L. McCarthy, P. Parikh, D. Rhodes, T. Hosoda, Y. Kotani, K. Imanishi, Y. Asai, T. Ogino, K. Kiuchi
Manufacturing readiness of the world’s first highly reliable 650V GaN HEMT is demonstrated with high process capability (CpK >1.6) for leakage and on resistance. This reliable manufacturing process was developed in a Si-CMOS compatible 6-inch foundry and has been demonstrated with over five thousand wafers worth of data, and spread over four generations of technology nodes. The analysis covers multiple device products and packages collected during industrialization of a JEDEC qualified process over a four year period. Silicon manufacturing processes are employed including a gold-free metallurgy that avoids the use of evaporation/liftoff processes, traditional in compound semiconductors. GaN wafer breakage data from the AFSW Foundry based on four years of manufacturing is presented. Backside contamination acceptance testing results from our foundry is also presented in this paper. These data sets show the flexibility of Transphorm’s GaN Epi and power GaN HEMT process to be compatible to any Si Foundry making the solution scalable. Wide bandgap high frequency and high voltage GaN devices significantly reduce the system size and improve energy efficiency of power conversion in all areas of electricity conversion, ranging from PV inverters to electric vehicles making the above results significant and making GaN high volume production a reality.
世界上第一个高可靠的650V GaN HEMT的制造准备就绪，具有高泄漏和导通电阻的工艺能力(CpK >1.6)。这种可靠的制造工艺是在Si-CMOS兼容的6英寸铸造厂开发的，已经用超过5000片晶圆的数据进行了演示，并在四代技术节点上传播。该分析涵盖了在四年期间JEDEC合格工艺工业化期间收集的多种设备产品和包装。采用硅制造工艺，包括无金冶金，避免使用蒸发/提升工艺，传统的化合物半导体。介绍了AFSW铸造厂4年生产过程中氮化镓晶圆破碎数据。本文还介绍了我方铸造厂的背面污染验收测试结果。这些数据集显示了Transphorm的GaN Epi和功率GaN HEMT工艺的灵活性，可以与任何硅铸造厂兼容，使解决方案具有可扩展性。从光伏逆变器到电动汽车，宽带隙高频高压GaN器件显著减小了系统尺寸，提高了所有电力转换领域的能量转换效率，使上述结果具有重要意义，并使GaN的大批量生产成为现实。
{"title":"5000+ Wafers of 650 V Highly Reliable GaN HEMTs on Si Substrates: Wafer Breakage and Backside Contamination Results","authors":"S. Chowdhury, YiFeng Wu, Likun Shen, L. McCarthy, P. Parikh, D. Rhodes, T. Hosoda, Y. Kotani, K. Imanishi, Y. Asai, T. Ogino, K. Kiuchi","doi":"10.1109/ASMC49169.2020.9185385","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185385","url":null,"abstract":"Manufacturing readiness of the world’s first highly reliable 650V GaN HEMT is demonstrated with high process capability (CpK >1.6) for leakage and on resistance. This reliable manufacturing process was developed in a Si-CMOS compatible 6-inch foundry and has been demonstrated with over five thousand wafers worth of data, and spread over four generations of technology nodes. The analysis covers multiple device products and packages collected during industrialization of a JEDEC qualified process over a four year period. Silicon manufacturing processes are employed including a gold-free metallurgy that avoids the use of evaporation/liftoff processes, traditional in compound semiconductors. GaN wafer breakage data from the AFSW Foundry based on four years of manufacturing is presented. Backside contamination acceptance testing results from our foundry is also presented in this paper. These data sets show the flexibility of Transphorm’s GaN Epi and power GaN HEMT process to be compatible to any Si Foundry making the solution scalable. Wide bandgap high frequency and high voltage GaN devices significantly reduce the system size and improve energy efficiency of power conversion in all areas of electricity conversion, ranging from PV inverters to electric vehicles making the above results significant and making GaN high volume production a reality.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"37 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90136045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185362
Kunal Raghuwansi, John Leclair, D. Zhernokletov
Variations in etch rates during plasma etching can occur due to differences in the conditioning of the inside surfaces of a plasma reactor. Passivation of the surfaces of the reactor wall by plasma generated species can change the composition of the radicals in plasma and ion fluxes (J) to the wafer and thereby cause variations in etch processes on a wafer-to-wafer basis. Furthermore, ion bombardment of the walls during plasma-on will influence the processes through activation of surface sites. In order to maintain a clean reactor condition, a dry clean method called Wafer-less Auto Clean (WAC) is introduced to clean out any by-products that are re-deposited on the surfaces to achieve steady particle performance during full MTBC (mean time between clean). However, this dry cleaning method can change the condition of the reactor and can cause wafer-towafer process variation. To mitigate process drifts at gate hard mask layer, an innovative method of seasoning etch reactors using simulated covered wafer-less auto clean (S-CWAC) was tested and implemented. The highest variation seen on the 1st wafer to process was reduced by running S-CWAC prior to processing the wafer to pre-coat the reactor walls with films that would otherwise be deposited after etching the production wafer.
{"title":"Simulated Covered Wafer Auto Clean (CWAC) to Eliminate First Wafer Effect and Improve Process Capability","authors":"Kunal Raghuwansi, John Leclair, D. Zhernokletov","doi":"10.1109/ASMC49169.2020.9185362","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185362","url":null,"abstract":"Variations in etch rates during plasma etching can occur due to differences in the conditioning of the inside surfaces of a plasma reactor. Passivation of the surfaces of the reactor wall by plasma generated species can change the composition of the radicals in plasma and ion fluxes (J) to the wafer and thereby cause variations in etch processes on a wafer-to-wafer basis. Furthermore, ion bombardment of the walls during plasma-on will influence the processes through activation of surface sites. In order to maintain a clean reactor condition, a dry clean method called Wafer-less Auto Clean (WAC) is introduced to clean out any by-products that are re-deposited on the surfaces to achieve steady particle performance during full MTBC (mean time between clean). However, this dry cleaning method can change the condition of the reactor and can cause wafer-towafer process variation. To mitigate process drifts at gate hard mask layer, an innovative method of seasoning etch reactors using simulated covered wafer-less auto clean (S-CWAC) was tested and implemented. The highest variation seen on the 1st wafer to process was reduced by running S-CWAC prior to processing the wafer to pre-coat the reactor walls with films that would otherwise be deposited after etching the production wafer.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"45 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85962204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185392
T. Esposito, S. Jen, Qian Xie, D. Acharya, Julie Lee, F. Levitov
As the complexity of both design and processing increase for advanced FinFET technology, defect metrology will continue to provide the best strategies for Defect Review Scanning Electron Microscopy (DR-SEM) and Automatic Defect Classification (ADC). The precise defect location navigation, and the accuracy of random and systematic defect classification can be improved by introducing Computer-Aided Design (CAD) into DR-SEM and ADC processes. The Design Based ADC (DBA) not only differentiates systematic and random defect on CAD for yield control but also determines the precise defect locations for weak point analysis. We will present a method for the implementation of weak point CAD for DR-SEM review and ADC through a case study of a BEOL CMP layer of an advanced FinFET process demonstrating its benefit to defect analysis and control.
{"title":"Analysis of Systematic Weak Point Structures using Design Based Automatic Defect Classification and Defect Review SEM Platform","authors":"T. Esposito, S. Jen, Qian Xie, D. Acharya, Julie Lee, F. Levitov","doi":"10.1109/ASMC49169.2020.9185392","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185392","url":null,"abstract":"As the complexity of both design and processing increase for advanced FinFET technology, defect metrology will continue to provide the best strategies for Defect Review Scanning Electron Microscopy (DR-SEM) and Automatic Defect Classification (ADC). The precise defect location navigation, and the accuracy of random and systematic defect classification can be improved by introducing Computer-Aided Design (CAD) into DR-SEM and ADC processes. The Design Based ADC (DBA) not only differentiates systematic and random defect on CAD for yield control but also determines the precise defect locations for weak point analysis. We will present a method for the implementation of weak point CAD for DR-SEM review and ADC through a case study of a BEOL CMP layer of an advanced FinFET process demonstrating its benefit to defect analysis and control.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"50 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90975777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185380
Thomas S. Reger, Gary Reichl
High temperature sealing performance is a need in semiconductor manufacturing processes. There can be significant performance differences even among perfluoroelastomers (FFKM) that are the most advanced class of rubber materials. The goal of this publication is to relate the temperature capability of four different FFKM materials to their underlying cross-link chemistry. This paper describes the long-term compression set method used to establish a material service temperature. Isothermal thermogravimetric analysis (TGA) is also explored as a method to establish material use temperature. The nature of the elastomer cross-link also has implications for plasma resistance and wet chemical compatibility and, taken together with thermal stability, represents a critical factor in choosing the appropriate elastomer sealing material.
{"title":"Science of Sealing: Advanced Materials for High-Temperature Applications","authors":"Thomas S. Reger, Gary Reichl","doi":"10.1109/ASMC49169.2020.9185380","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185380","url":null,"abstract":"High temperature sealing performance is a need in semiconductor manufacturing processes. There can be significant performance differences even among perfluoroelastomers (FFKM) that are the most advanced class of rubber materials. The goal of this publication is to relate the temperature capability of four different FFKM materials to their underlying cross-link chemistry. This paper describes the long-term compression set method used to establish a material service temperature. Isothermal thermogravimetric analysis (TGA) is also explored as a method to establish material use temperature. The nature of the elastomer cross-link also has implications for plasma resistance and wet chemical compatibility and, taken together with thermal stability, represents a critical factor in choosing the appropriate elastomer sealing material.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"40 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84228935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185252
R. Mahadevapuram, V. Kaushal, A. Raviswaran
Developed a novel multi-layered eSiGe film on FINFET architecture to increase PMOS performance by optimizing within wafer (WiW) uniformity for lateral growth and Boron concentration. The new process reduced growth related defect issues on large die products and excess abnormal growth defects to improve yield and reliability of latest semiconductor chips.
{"title":"A high throughput PMOS Source-Drain process optimized within FINFET architecture for high volume chip manufacturing","authors":"R. Mahadevapuram, V. Kaushal, A. Raviswaran","doi":"10.1109/ASMC49169.2020.9185252","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185252","url":null,"abstract":"Developed a novel multi-layered eSiGe film on FINFET architecture to increase PMOS performance by optimizing within wafer (WiW) uniformity for lateral growth and Boron concentration. The new process reduced growth related defect issues on large die products and excess abnormal growth defects to improve yield and reliability of latest semiconductor chips.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"18 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82168007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185267
Xingdi Zhang, Hungling Chen, Yin Long, Kai Wang
Process window limiting structures (PWLS) evaluated with process window discovery methodology (PWD) was studied on 28nm and beyond technology node wafers. Process window discovery methodology was innovated basing on process window qualification (PWQ) methodology. And the impacted factors, including focus energy matrix (FEM) wafer conditions, defects inspection conditions and defects filtering and sampling methods, were also investigated. With the innovated methodology, process window limiting structures were detected on 28nm wafers. Then the more reasonable process window target and spec, including lithography and etch process, were redefined. Furthermore, the process window limiting structures were enhanced monitored with Nano-point function of bright-field inspection system. Instead of end of line (EoL) chip probe (CP) test, inline process window discovery methodology has much time advantage for process window evaluation and process window limiting structures definition even monitoring.
{"title":"Study of Process Window Discovery Methodology for 28nm and Beyond Technology Node Process Window Limiting Structures","authors":"Xingdi Zhang, Hungling Chen, Yin Long, Kai Wang","doi":"10.1109/ASMC49169.2020.9185267","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185267","url":null,"abstract":"Process window limiting structures (PWLS) evaluated with process window discovery methodology (PWD) was studied on 28nm and beyond technology node wafers. Process window discovery methodology was innovated basing on process window qualification (PWQ) methodology. And the impacted factors, including focus energy matrix (FEM) wafer conditions, defects inspection conditions and defects filtering and sampling methods, were also investigated. With the innovated methodology, process window limiting structures were detected on 28nm wafers. Then the more reasonable process window target and spec, including lithography and etch process, were redefined. Furthermore, the process window limiting structures were enhanced monitored with Nano-point function of bright-field inspection system. Instead of end of line (EoL) chip probe (CP) test, inline process window discovery methodology has much time advantage for process window evaluation and process window limiting structures definition even monitoring.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"35 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82408853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185288
J. Fakhoury, M. Lawliss, T. Faure, A. Zweber, Yurong Ying, C. Magg, B. Morgenfeld
In this paper, we demonstrate the use of Aerial Imaging Metrology System (AIMS™) during mask fabrication to deliver duplicate photomasks with matching iso-dense bias (IDB) to a reference photomask. The photomask IDB trend based on AIMS™ feedback showed a direct correlation to on-wafer IDB performance. We also show that the AIMS™ threshold energy is correlated to the photomask critical dimension (CD) mean to target (MTT), and correlates to the on-wafer exposure dose for both line/space and via mask levels in the 14nm technology node. This technique will enable improved photomask matching taking into account 2D and 3D mask effects comparable to wafer processing on lithography exposure tools. With AIMS™ metrology, corrections can then be applied to photomask rebuilds prior to shipment to Wafer Manufacturing Sites.
{"title":"Improved Duplicate Photomask Matching using AIMS™ Metrology for 14nm and smaller","authors":"J. Fakhoury, M. Lawliss, T. Faure, A. Zweber, Yurong Ying, C. Magg, B. Morgenfeld","doi":"10.1109/ASMC49169.2020.9185288","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185288","url":null,"abstract":"In this paper, we demonstrate the use of Aerial Imaging Metrology System (AIMS™) during mask fabrication to deliver duplicate photomasks with matching iso-dense bias (IDB) to a reference photomask. The photomask IDB trend based on AIMS™ feedback showed a direct correlation to on-wafer IDB performance. We also show that the AIMS™ threshold energy is correlated to the photomask critical dimension (CD) mean to target (MTT), and correlates to the on-wafer exposure dose for both line/space and via mask levels in the 14nm technology node. This technique will enable improved photomask matching taking into account 2D and 3D mask effects comparable to wafer processing on lithography exposure tools. With AIMS™ metrology, corrections can then be applied to photomask rebuilds prior to shipment to Wafer Manufacturing Sites.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"4 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85231044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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