Analog Integrated Circuits and Signal Processing最新文献

The Electroencephalogram (EEG) signals have very small amplitudes, which allow for the data to be readily contaminated by numerous artifacts. When it comes to clinical assessment, the presence of artifacts makes the study of EEG more complex. Power Line noise, eye movements, Electromyogram (EMG), and Electrocardiogram (ECG) are the most often seen artifacts that impact the EEG. Various researchers have developed a variety of strategies and procedures to deal with these artifacts. We provide a method for denoising the EEG signal in this work. The suggested method is implemented using a combined approach of wavelet total variation denoising method (WATV) and Independent Component Analysis (ICA). ICA technique entails running ICA algorithm on independent components to derive the components. In the case of artifactual events, just the wavelet-ICA components related to that event are used and then eliminated. To create artifact-free EEG, the artifact-free wavelet components are reconstructed. The complete approach may be confirmed for simulated signals and may be utilized for processing biological data, which may include EEG signal measurements, and for images, such as MRIs, contaminated by additional random noise. Signal to Noise Ratio (SNR) and Root Mean Square Error (RMSE) will be used to evaluate the algorithm’s performance. The WATV-ICA framework improves SNR more than the other techniques, according to simulation results.

Time-effective and accurate characterization of the dielectric constant of the fruit sample is important to gauge its quality. For this purpose, the present work aims design and simulation of a radio frequency probe structure. For testing of the structures, apple and pear fruits are selected. Initially, their sugar content level is measured with the Brix meter. The novelty in the design is added with the radiation structure at another end. Further, a design and fabrication of single port planar sensor has been performed. The novel simulated sensor is fabricated and used in array structure to test quality of the fruit sample kept in-between them, and results of S₁₁ and S₂₁ is obtained. Additional arrangements are made to rotate the fruit sample from 0 to 360° with the increment of 5° using microcontroller set up and stepper motor controller unit. The proposed novel sensor structure has applications in microwave-assisted sensing of quality parameters fruit for maintaining quality and safety and as protection against insects.

To improve the received signal strength beams are formed by multi-element arrays. These beams are focused on the direction of arriving signals, with an intention of maximizing the received signal power. The signals with noise and interference arrived from a distinct direction will be estimated by Uniform Linear Array (ULA) with 10 antenna elements. The earlier signal will be phase-shifted with the help of phase shift beamformer. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used compute the vector angle in signal cluster. The CORDIC algorithm is employed determint the phase shift and frequency offset. The beamformer assumes that incoming signal are narrow banded, a phase shift can estimate the required delay and preserve the incoming signal strength. The beamformer circuit is designed in Xilinx Vivado for simulation and synthesized using both Virtex-7 device and their results are compared with exisiting methods, which is evidence that the proposed design is formidable pertaining to power and delay. This design can operate at 100 MHZ with total on-chip power consumption of 725 mW.

This paper presents a novel Single Inductor Double Output (SIDO) Hysteretic Buck converter which balances one output with respect to the other by continously monitoring the load demands of both outputs and then aligning the outputs such that each output regulates its load with minimal disturbance to the other. Load balancing prioritizes the inductor current delivery in the case of a large load current request. The controller aims to finalize the ongoing regulation of the recent output in a prompt manner and then directs the inductor current to the steep load demand output and afterwards returns to the initial output regulation in an iterative way. In conjunction with iterative duty cycle adjustment of outputs, a frequency counter is utilized to accelerate the iteration process to enhance the transient response further. In addition, a delay locked loop fine tunes the duty cycle further to reduce the steady state cross regulation and also limits the switching frequency spectrum. Consequently, both static cross regulation and transient cross regulation performance are further improved compared to previous SIDO architectures. Post-layout simulation results indicate that this architecture has a static cross regulation of 0.0009 mV/mA and transient cross regulation of 0.0063 mV/mA. This SIDO buck converter outperforms the previous studies with a total power delivery capability by supplying 3A load current at each output and 10 W of total power with a peak efficiency of 93.7%.

The studies on Nonlinear Phenomena have been carried out in buck converter controlled by three different types of modulation technique—Peak current, Peak V² and Enhanced V². These three modulation methods are rippled based control methods as inductor current ripple is used in Peak current modulation (PCM) method and output ripple voltage used in both Peak V² and Enhanced V² modulation methods and due to that all three modulation methods provide fast dynamic response. Here three modulation techniques have been explained in details and simulation results have been provided. For designing the modulators—we consider two loops i.e. inner loop or fast feedback path (FFBP) and outer loop or slow feedback path (SFBP). The outer loop of all these three modulation methods contains same information, the difference between reference voltage and output voltage. Mathematical model has been developed with the help of state space equation in continuous conduction mode (CCM). Bifurcation diagrams are obtained with load resistance, input voltage and reference voltage as bifurcation parameter. To validate the bifurcation pattern, time plot and phase plane trajectory at each transition have been shown for these three types of modulated system. A comparative study has been made. Experiments are conducted on an enhanced V² modulated buck converter to validate the nature of the nonlinearities. To check the dependency of the system on ESR value, parameter space plots are developed and compared for all these three types of control technique.

In recent years Quantum Cellular Automata (QCA) technology has emerged as an ideal option to substitute the current CMOS technology. QCA offers operation in the terahertz range, small area, and low power in nano-scale circuit design. This paper explores the application of quantum dot cellular automata(QCA) technology in efficient floorplanning of digital code converters using the tile based architecture of QCA XOR gate. The proposed code converter circuits exhibits the benefits of low cell count, area, cost and low energy dissipation. The suggested layouts have achieved the 11.42% reduction in cell count, 29.53% reduction in total occupational area,30.93% reduction in cost and 11.52% increase in area utilization factor in comparison to similar counterparts. The functional validity of the suggested designs were validated using QCADesigner 2.0.3 tool. In addition, the energy dissipation analysis were calculated using the QCAPro tool at standard tunelling energy levels o 0.5E_K, 1.0E_K, 1.5E_K.

This paper presents an investigation on the impact of temperature variations (150 –400 K) on the DC, analog/RF performance such as total gate capacitance (C_gg), transconductance (g_m), output conductance (g_d), intrinsic gain, transconductance efficiency, cut-off frequency (f_T), and transconductance frequency product (TFP) of the negative capacitance quad-FinFET (NCQ-FinFET). A comparative evaluation of the analog/RF performance of the NCQ-FinFET and SOI NC-FinFET is carried out. Additionally, the influence of temperature on the linearity figures of merit in the NCQ-FinFET is analysed for a wide range of temperature, including higher order harmonics, higher order voltage intercept points, third-orders power-intercept points and intermodulation distortion, and 1-dB compression point. Furthermore, the harmonic distortion (HD) metrics such as second and third order harmonic distortion (HD2 and HD3), as well as total harmonic distortion (THD) are presented for different temperature range. The analog/RF, linearity and HD metrics are observed to be significantly impacted by temperature variation. According to the analysis, when temperature increases from 150 K to 400 K, the analog/RF characteristics deteriorates while the linearity and HD metrics are improved.

A new microstrip patch antenna design with a Defected Ground Structure (DGS) is described in this research for 5G V2V and V2I communication in the 25 GHz to 35 GHz frequency band. The proposed antenna improves performance and bandwidth enhancement by combining back propagation model ANN, fractal geometry, and DGS. ANN optimizes antenna size and an enhancement in bandwidth is noticed. Fractal geometry reduces antenna size and improves radiation and bandwidth through self-similarity at various scales. Additionally, this fractal-based method reduces unnecessary side lobes, enhancing performance. DGS prevent surface wave propagation, reduce cross-coupling, and boost gain. Periodic ground plane slots or patches control radiation patterns and facilitate element mutual interaction in the DGS. DGS microstrip patch antennas provide a high gain of 9 dB, a massive simulation bandwidth of 4900 MHz and measured bandwidth of 4600MHz, and a lack of mutual coupling. It’s a great 5G V2V and V2I solution for reliable communication.

The rise of mobile technologies and cloud computing has increased the importance of efficient energy consumption. Due to parallelism, high voltage conversion ratios, and large supply currents, power losses are rapidly increasing. This issue can be managed by on-package voltage stacking, where the current is recycled between multiple cores. Current mismatch between serially connected cores however produces a noise voltage between the cores. Differential power processing (DPP) converters are a potential solution to this issue. In the current work, a power efficient, load-to-load synchronous buck converter operating within a voltage stacked system is examined. The buck converter is evaluated under very high current demand, where the core currents in a voltage stacked system reach a tenfold difference. A compact model to characterize the voltage drop in serially stacked systems is also described. Furthermore, a circuit topology to increase the power efficiency of this converter is proposed. By using an interleaved system with different active phases, the inductance in the converter can be changed, which produces variable frequency operation, resulting in increased power efficiency due to lower switching losses. The power efficiency of the converter is increased by up to 8% as compared to constant frequency operation, achieving a range between 89% to 99%.

In this paper, a monopole-based flower-shaped 4-element multiple-input multiple-output antenna is designed for 4G Long-term evolution bands, 5G sub-6 GHz bands, Wifi-5 and Wifi-6 bands applications. The proposed model is designed and fabricated on low cost FR4 material with a dielectric constant of 4.4 and compactness of 54 × 54 mm² (0.51 λ₀ × 0.51 λ₀, where λ₀ measured at the lower band) size, having the height of 1.6 mm. The single radiating patch of size 26 × 20 mm², and it works in the frequency range of 3.34 to 6.32 GHz. Later, four single radiators are placed in an orthogonal manner for isolation enhancement. The working band of the proposed model is 2.88 to 6.12 GHz with isolation more than 15 dB for adjacent elements and better than 20 dB for diagonal elements. The stable radiation patterns and high radiation efficiency values above 90% are achieved in the entire working region. A minimum gain of 2.75 dBi and maximum gain of 5.25 dBi is attained. The diversity characteristics of the proposed model are checked with low Envelope correlation coefficient, high Diversity gain, low Channel capacity loss, good Mean effective gain, and acceptable Total active reflection coefficient values. The proposed model is developed and validated with simulated results, which are in good agreement.