Analog Integrated Circuits and Signal Processing最新文献

Anaglyph 3D technology has recently developed and become more widely available. This has led to an increase in demand, which is only reasonable given the market’s fast expansion and the high need for electronic media. The majority of films made nowadays are in 3D format. Here, we provide a straightforward way for creating anaglyph 3D images using VLSI technology. This method takes less time and money, is suited for any real-world video sequence, and yields smooth results .In this study, we employ novelty-based three-operand multiplications to multiply the image layers of right eye, left eye, and depth. This study introduces a novel three-operand multiplier based on Wallace tree architecture in order to be faster and more dependable. This proposed multiplier uses a 3 input AND gate approach to generate partial product, which is then compressed using 7:2 compressor, 5:2 compressor, 4:2 compressor, and full adders. The final addition was carried out using five separate 24-bit versions of a parallel prefix three operand adder. As to create anaglyph 3D images, image multiplication was performed using a resolution of 640 × 480 pixels, and PSNR and SSIM values were calculated as evaluation criteria. The results of all parameters were compared for this proposed implementation, which was created using Xilinx Vertex-5 FPGA and Verilog HDL. The Wallace Tree Multiplier designed for three operand multiplication is proven to produce lesser delay and power compared to all other designs.

The standard of healthcare services is now being improved via biomedical applications, which are the focus of most technology progress. Since most biomedical equipment is rechargeable and portable, energy-efficient execution is required for all designs. Since analogue signals are the foundation of all communication, digital advancements can only occur when analog signals can be converted into digital ones. In most biomedical devices, the analog-to-digital converter (ADC) is an essential component. Therefore, this review presents an analog front-end design (AFE) for biomedical sensor applications, and the design includes several modules, namely, amplifiers, filters, and ADC modules. This review highlights delta-sigma modulator (DSM) based ADC designs and Successive approximation registers (SAR) based ADC designs for biomedical sensor applications. Additionally, schematic views are provided for the three main ADC design building blocks: the comparator, the digital-to-analog converter (DAC), and the sample and hold (S/H) circuit. In addition to this, the review undergoes several AFE designs, namely, Low-Noise Amplifier (LNA), Programmable Gain Amplifier (PGA), and Variable Gain Amplifier (VGA), for biomedical applications with diagrammatic representations. Moreover, different types of electrodes used in the signal acquisition are discussed by means of different parameters. Numerous ADC designs, amplifiers and filters are eventually addressed in tabular form for improved comprehension. In addition to this, the challenges and future directions are discussed.

Nanowire-based technology is the leading candidate for future generations of applications. Nanowires are suitable channel materials because of their high electron mobility, low subthreshold leakage current, and one-dimensional conduction. Ferroelectric materials have been used as the gate oxide in this work, which compares two different band gap materials: Silicon and compound materials like InAs. The ferroelectric material is considered a gate oxide due to its better properties that stifle short channel effects (SCEs) like DIBL and subthreshold leakage. Compound material has a higher I_ON current than silicon material due to its high mobility and better subthreshold swing (SS) when the gate length varies from 30 to 50 nm. Because carriers are effectively mobilised, compound material has 100 times better drive current. By changing the gate/channel length from 30 to 50 nm, the device performance metrics, SS, I_ON/I_OFF ratio, transconductance, output characteristics, etc., are analysed. This work also calibrates the simulated results using published and experimental studies using Zirconium-doped Hafnium oxide (Zr: HfO₂) ferroelectric material for a gate length of 30 nm.

Adaptive filters provide a dynamic and efficient way to process signals in real-time, making them indispensable in numerous applications where adaptation to changing conditions is critical. The Normalized Least Mean Square (NLMS) is one among the most commonly used filters due to its adaptive step size with high convergence speed. In this paper, Delayed NLMS (DNLMS) and Delayed ErrorNLMS (DENLMS) adaptive filter structure variants are tested using Xilinx Spartan 6 series deviceandits performance are analysed.To deplete the clock period and path delay in a combinational circuit, cut-set Retiming technique is proposed in the adaptive filters to achieve higher throughput and lower critical path delay.The performance analysis of conventional NLMS with Retimed DNLMS (RDNLMS) and Retimed DENLMS (RDENLMS)along with the direct form (DF), transposed form (TF) and hybrid forms (TDF) are obtained and tabulated. Further the Signal to Noise Ratio (SNR) and Mean Square Error (MSE) of the different adaptive filters are analysed. The results show that, the proposed TF-RDENLMS adaptive filter implementation has achieved clock period of 13.39ns whereas the conventional un-retimed NLMS adaptive filter structure has 29.96ns, thereby resulting in minimization of 55.3%critical path delay.Xilinx Spartan 6 FPGA series implementation of retimed adaptive filter achieves maximum operating frequency of 74.67 MHz as compared to conventional un-retimed structure with 33.37 MHz. Hence the speedup factor is approximately 2.24, which means that the proposed retimed adaptive filter operates at about 2.24 times the speed of the conventional un-retimed structure. For the first time in audio processing, cut-set retiming is used in this work’s innovative FPGA implementation of the Delayed Error Normalized Least Mean Square (DENLMS) adaptive filter. The Transposed Form Retimed DENLMS (TF-RDENLMS), which runs on a Xilinx Spartan-6, works at a speed of 74.67 MHz, is 2.24 times faster, and has a delay of 13.39 ns. With an SNR of 89.79 dB, it also provides excellent noise reduction. This method balances performance with low power and area overhead, providing a high-speed, effective solution for real-time voice and communication systems. In addition, theproposed filter RDENLMS produces minimum noise with an SNR value of 89.79dB and very low MSE, which indicates that the filter can adapt to fluctuations and instabilities in signal environment.

In this paper, a photonic crystal intersection with a germanium-antimony-telluride (GST) phase change material rod is introduced and analyzed for tuneable changes in the optical properties of intersection waveguides. The device can alter the optical properties of the waveguides through a control signal applied to the phase-change material rod. Numerical simulation using the finite difference time domain (FDTD) method has shown that the proposed structure can create a single-mode waveguide with a transmission coefficient and quality factor of 94% and 248, respectively. Also, the simulation has exhibited an insertion loss of 0.28 dB with a low cross-talk level of -49 dB in the proposed intersection waveguide. By adjusting the phase state of the GST rod, the transmission of the output waveguide can be independently controlled. The remarkable feature of this structure is the ability to transmit two different wavelengths independent of the crossing path of the two waveguides. The small footprint of the proposed photonic crystal synaptic cell is reduced to less than 14.8 µm², overcoming the limited space challenge for optical neuromorphic networks. The time domain response of the applied signal has been investigated in both states of the amorphous and crystalline PCM rod, revealing a steady state time less than 10 ps. The objective of this structure is to integrate optical neuromorphic circuits and reduce the architectural footprint, considering features such as minimal interference and independently adjustable wavelength passbands. The novelty of this research lies in the design of a 3 × 3 photonic crystal structure with intersecting waveguides, enabling independent control of transmitted power in each waveguide path. The design achieves very low cross-talk, compact dimensions, and tunable transmission via phase transitions, offering a distinct advantage over conventional silicon photonic devices. These features demonstrate its strong potential for all-optical neuromorphic synapses and advanced optical communication systems.

Quantum computing (QCG) is advancing toward higher-dimensional systems that offer greater efficiency and scalability, moving beyond traditional binary qubit-based architectures. This work presents a novel quaternary (radix-4) quantum full adder (QFA) based on native qudit logic, implemented within the QuTiP framework. The design employs three modular permutation-based gates: SUM1(A, B), SUM2(B, Cin), and Carry-out (A, B, Cin), each realized as a unitary operation on a three-qudit system. The proposed circuit achieves a quantum cost (QC) of only three, representing minimal logic depth when executed on a native qudit processor. In a qubit-equivalent cost model, where each qudit gate is approximately equivalent to three Toffoli gates, the corresponding QC is approximately 9. This is lower than that of standard binary full adders, which typically require 10 to 15 gates under the same model. Building on this efficient adder, we present the first complete implementations of qudit-based quantum multipliers in radix-4, using Wallace, Dadda, and Array architectures. Full simulations were performed using standard benchmarks. Among the three, the Qudit Wallace Multiplier delivers the best performance, achieving a gate count of 38, a quantum cost of 148, and 44 garbage outputs. The array multiplier is more resource-intensive, with a QC of 256 and 80 garbage outputs, while the Dadda variant offers a balanced trade-off, with a QC of 184. All architectures produce fully accurate results. Error detection via a Z-type stabilizer demonstrates the feasibility of fault-aware operation in these systems. The proposed architectures are compatible with emerging multi-level control platforms, including quantum-dot devices, photonic systems, superconducting circuits, and trapped ions. These findings establish qudit-based arithmetic as a practical and effective strategy for scalable quantum processors and advanced Very Large-Scale Integration (VLSI) systems. By leveraging higher-dimensional qudit states, this approach enhances energy efficiency through reduced circuit depth and lower resource requirements.

Recording the electrical activity of the heart is done using an electrocardiogram (ECG). Compressed sensing's classification skills have recently been used to cardiovascular disease monitoring, allowing for more efficient patient monitoring using compressed physiological data. The quantity of data produced by the sensor depends on how long it has been monitoring the signal. Reducing storage space is possible with the use of an efficient lossless ECG compression technique. A hardware design for a multiple channels lossless ECG compression method is shown in this short. The algorithm that forms the basis of the system incorporates both adaptive linear prediction (ALP) and multi-channel linear prediction (MLP). For entropy coding, the Golomb rice coder (GRC) is also used. Optimal hardware resources were used in the design of the hardware implementation, which aimed to minimize hardware complexity utilization. To top it all off, the design allows for great throughput by processing several channels simultaneously. Therefore, instead of processing individual heartbeats, arrhythmia categorization from compressed ECG data must be done in segments of predetermined length. Following this, we provide a deep learning (DL) model that, with the benefits of a high compression ratio (CR) and a low processing cost, can directly identify various forms of arrhythmia using compressed ECG segments of a set length. Our suggested strategy achieves an exact match rate of 97.03% at CR(Compression Ratio), according to experimental findings on the MITBIH arrhythmias database.

This paper presents a race-free cascaded dynamic current mode logic (DyCML) derived from NORA-based CMOS dynamic circuits. Cascading two stages of DyCML gates poses the challenge of erroneous evaluation between stages. To address this, two traditional cascading mechanisms, one using a clock delay scheme and the other employing a self-timing scheme, both require intermediary circuits, such as inverters or buffers, between stages. This paper proposes a new complementary DyCML for the NORA-based cascaded technique, which is completely race-free, regardless of the overlap period of the two complementary clock signals. The proposed technique eliminates the need for intermediary circuitry, thereby resolving the issue of erroneous evaluation. The new NORA-based technique enhances performance, including reductions in delay, power consumption, and area. The proposed NORA-based DyCML circuit was optimized using a combination of Taguchi and ANOVA statistical techniques. Following this optimization process, the circuit achieved a delay of 121.8 ps, a power consumption of 6.11 µW, and a power-delay product (PDP) of 0.744 fJ. Simulations conducted in Cadence Virtuoso using GPDK 45 nm CMOS technology at a 1 V supply voltage demonstrate improvements of 69.55%, 17.85%, 74.97%, and 27.90% in delay, power consumption, power-delay product, and area, respectively, compared to the existing design. Post-layout simulations further validate the performance parameters, while Monte Carlo simulations and process, voltage, and temperature (PVT) variations confirm the robustness of the proposed circuit. Overall, the proposed NORA-based DyCML technique offers significant advantages in performance and area efficiency, making it a viable solution for low-power, high-performance logic circuits.

This paper presents a tri-band metamaterial unit cell based on a compact split-ring resonator and developed using an original continuously variable impedance line approach. With reduced electrical dimensions of 0.05λg × 0.06λg at 2.45 GHz, the cell exhibits three distinct resonances at 2.45 GHz, 5.35 GHz, and 8.95 GHz. The results demonstrate its ability to generate different metamaterial behaviors, namely negative epsilon (ENG), negative mu (MNG), and double negative (DNG). An effective medium ratio (EMR) of 12.25 at 2.45 GHz highlights its exceptional compactness, while high quality factors (approximately 144, 105, and 149) at the resonant frequencies confirm its efficiency. An equivalent circuit model was also developed, demonstrating good agreement with numerical simulations. The structure was evaluated using 1 × 2 and 2 × 2 arrays, producing results which showed sufficient agreement for consideration in S-, C-, and X-band wireless communications. These remarkable characteristics, combined with the simplicity of its design, make this cell a promising element for multi-band RF and microwave applications.

Junctionless Tunnel Field Effect Transistors (JL-TFETs) represent a significant shift in transistor design, attracting attention for their ability to achieve a steep subthreshold swing (SS) and operate at ultra-low power. Unlike conventional design, the junctionless design simplifies manufacturing, improves scalability, and reduces variations in threshold voltage. This paper analyzes different JL-TFET structures such as nanotube, pocket-doped, double-gate, and hetero-gate structures and focuses on their unique operational principles like carrier transport, band alignment, tunneling mechanisms, and performance trade-offs. Special emphasis is placed on the detrimental impact of quantum confinement (QC) and interface trap charges (ITCs), which degrade ON-current, increase leakage, and limit subthreshold swing is also discussed in this paper. Additionally, the fabrication of JL-TFETs remains highly challenging, requiring ultra-high uniform doping, nanometer-scale control of channel thickness, high-quality gate dielectrics, and abrupt band alignment—all of which critically affect device performance and are discussed in detail. Furthermore, a comparative analysis of state-of-the-art JL-TFET designs is presented, highlighting key metrics such as DC and RF performance. The study underscores the potential of JL-TFETs as next-generation transistors while identifying key material, structure, and fabrication challenges that must be addressed for their practical realization.