Analog Integrated Circuits and Signal Processing最新文献

The adoption of Variable Frequency Clock (VFC) in different application-specific integrated circuits (ASICs) has gained popularity over the decades because of its flexibility and adaptability across domains in contrast to any conventional clocking system. This paper presents a detailed study of VFCs, exploring their classifications, operating principles, and performance metrics. Various architectures are discussed in terms of fundamental principles of programmable frequency synthesizers which are the core of VFC generation. After highlighting the advantages, limitations and design challenges of each architecture, this survey extensively explores the broader area of applications of VFC spanning to Supply Noise Management, Temperature Management, Power Management, Data Rate synchronization, and electromagnetic interference (EMI) reduction etc. Additionally, the survey provides insights into the future potential applications of VFC. By presenting a comprehensive understanding, this paper seeks to guide researchers to develop innovative, more adaptable and high-performance architectures of VFC to meet the need of evolving technological landscapes. To our knowledge, this is the first survey to unify scattered, application-specific VFC architectures into a comparative study and assess their cross-domain applicability.

In real-time applications, some communication technology requires variable attenuation for the acquired signal without compromising distortion levels. It is easier to achieve low signal distortion when performing step attenuation. However, complexity remains high when an application requires different levels of energy without degrading its strength. The paper presents the use of a PIN diode variable attenuator for applications with different frequency ranges. The relationship between DC bias variations and the power levels of the application in use is also presented. The fixed attenuation level for a varied frequency range of the mmWave application is studied. According to the study, variable attenuators are utilized in high-frequency applications, including 6G and ultra-wideband, to achieve significant improvements, such as reduced distortion in signal transmission.

Bootstrap networks are widely used to power the floating high-side of high-voltage gate drivers, yet discrete fast-recovery diodes incur forward-drop loss, reverse-recovery stress, and PCB overhead. This work presents a 600-V gate-driver IC that integrates the bootstrap path by combining a 600-V laterally diffused MOS (LDMOS) pass device, a compact on-chip charge pump, and timing logic. The logic enables the LDMOS only while the low-side switch is on, transferring the supply (VCC) to the bootstrap capacitor without diode drop or recovery-induced overshoot. Fabricated in a qualified 600-V bipolar-CMOS-DMOS (BCD) technology that employs a deep-N-well high-voltage island with P-well/buried-P guard-ring isolation, the proposed driver places the bootstrap devices along the island periphery within the standard 600-V junction-termination region, thereby preserving the rated isolation without an appreciable die-area penalty. System-level evaluation in an air-conditioner intelligent power module (IPM) full-bridge shows that with VCC = 15 V the bootstrap node (VBS) rises to nearly 15 V within 20 ms; at 0.1-V forward bias the charging current reaches 2.5 A (versus 0.25 A at 0.9 V for a conventional scheme). Compared with discrete bootstrap designs, the proposed approach removes the external high-voltage fast-recovery diode, increases attainable VBS, reduces bill-of-materials and PCB area, and improves cost relative to silicon-on-insulator solutions—suiting high-voltage motor drives, especially three-phase full bridges.

A novel 16T 4:2 compressor is designed using workfunction engineering (WFE), whereby variation of WF in gate contacts is applied to independently biased compact sub 10 nm ambipolar Schottky-barrier (SB) FinFETs. The SB-FinFET utilises metal-semiconductor junctions, commonly referred to as Schottky barriers. This paper uses the gate voltage to control the barrier height and width, which regulates the current through the tunnelling when the device is ON and minimises leakages when it is OFF. The FinFET offers reasonable electrostatic control and the potential for high-energy-efficient logic circuits, as well as reduced parasitic resistance and improved switching speed. The performance of the compressor circuit is enhanced by using a 3T-XOR gate with non-inverting inputs, as verified through industry-standard TCAD simulation. The device simulations were performed using Synopsys Sentaurus TCAD, which accurately models Schottky barrier contacts and ambipolar conduction characteristics. The reduction rate for area improvement of the proposed circuit is 52%, whereas the improvement in power delay product is up to 7 times. The proposed 16T ambipolar FinFET design achieves an EDAP of 228,672, orders of magnitude smaller than all conventional designs. With only 16 transistors, the circuit saves 52% area compared to traditional 4:2 compressors (36–68 transistors). Low power (1.518 µW) and moderate delay (97 ns) yield a very low energy-delay product, confirming high energy efficiency. The switching characteristics of an ambipolar-based compressor circuit demonstrate that WFE in independent-biased SB-FinFETs can simultaneously direct sub-10 nm logic design to an optimised data path system without degradation in energy performance, saving area, and power.

This work introduces a novel quad-tail-cell-based Dynamic Current Mode Logic (DyCML) architecture to implement three-input logic function. Existing quad-tail-cell-based MOS Current Mode Logic (MCML) designs rely on a static current source, resulting in continuous static power dissipation. In contrast, the proposed DyCML approach eliminates the static current source and offers the advantages of dynamic logic, leading to reduced power consumption, lower delay, and minimized switching current, while supporting high-speed performance at lower supply voltages. To demonstrate the approach, a three-input XOR gate, an essential building block in digital systems, is designed and optimized using Taguchi’s design of experiments (DoE) method and ANOVA statistical analysis. The optimized design achieves 26.29 µW power dissipation, 185.5 ps propagation delay, and a power-delay product (PDP) of 4.87 fJ. The circuit is implemented and simulated in Cadence Virtuoso using GPDK 45 nm CMOS technology at a 1.1 V supply voltage. Compared to the existing quad-tail-cell-based MCML XOR gate, the proposed design delivers 34.45% lower delay, 88.26% lower power, and a 92.31% improvement in PDP. Post-layout simulations show an area of 208.98 μm², while robustness is confirmed through Monte Carlo and PVT variation analyses. The methodology is further extended to a generic gate architecture for realizing larger logic functions, such as a full adder and a 4 × 1 multiplexer.

This paper presents OptGM, an optimized gate merging method designed to mitigate negative bias temperature instability (NBTI) in digital circuits. First, the proposed approach effectively identifies NBTI-critical internal nodes—those with a signal probability exceeding a predefined threshold. Next, based on the proposed optimized algorithm, the sensitizer gate—which drives the critical node—and the sensitive gate, which is fed by it, are merged into a new complex gate. This complex gate preserves the original logic while eliminating NBTI-critical nodes. Finally, to evaluate the effectiveness of OptGM, we assess it on several combinational and sequential benchmark circuits. Simulation results demonstrate that, on average, the number of NBTI-critical transistors (i.e., PMOS transistors connected to critical nodes), NBTI-induced delay degradation, and the total transistor count are reduced by 89.3%, 24%, and 7%, respectively. Furthermore, OptGM enhances performance per cost (PPC) by 12.8% on average, with minimal area overhead.

In this work a detailed comprehensive study of single charge trap (SCT) induced random telegraph noise (RTN) in homo-junction, and hetero-junction single-gate (SG) and L_shaped tunnel field-effect-transistor (LTFET) are reported. Using TCAD simulations, relative RTN amplitude of SCT located at three different locations i.e. at oxide-channel interface, channel, and in source region is performed for all the structures. In hetero-junction TFET, the presence of more charge carriers reduces the impact of SCT on device characteristics as compared to homo-junction TFET. Also, it has been found that on reducing the gate length, the drain-current reduces as a results of the rapid reduction in electron band-to-band (BTB) generation rate at the tunneling junction. Furthermore, the relative RTN amplitude dependence on different parameters like doping variation, temperature variation, work function variation, and gate tunneling was carried out and the study states that the SCT located at interface and channel shows maximum impact on device characteristics followed by the SCT located in source. The SCT located at tunneling junction shows maximum RTN amplitude because of the exponential dependence of tunneling current on critical tunneling path. The proposed hetero-junction LTFET shows good performance like high I_ON of 1.39 × 10^− 4 A/µm, low I_OFF of 7.56 × 10^–12 A/µm, and high I_ON/I_OFF ratio of 10⁸. Furthermore, the presence of more number of carriers in LTFET screens the trap charges more effectively, and hence relative RTN amplitude is also less.

In this reported manuscript an extensive simulated study of LTFET (L-shaped Tunneling-Field-Effect-Transistor) using sentaurus TCAD simulator is presented. The reported LTFET device with 20 nm of channel length exhibits a high ION and low IOFF of 1.08 × 10–4 A/µm and of 1.57 × 10–14 A/µm respectively, with the high ION/IOFF ratio of 1010. The SS (sub-threshold slope) for the device is observed as 25 mV/dec at the room temperature. The range of temperature considered for analyzed the Gaussian traps effect between channel and oxide layer is from 250 K to 350 K. The various device analysis has been performed such as DC & AC analysis, noise analysis and linearity analysis while varying the temperature. The results exhibit the small variation on all electrical parameters on which figure of merits depends with the variation of temperature from 250 K to 350 K. The current and voltage noise spectral density also has been reported for the proposed device with variation of temperature and the change is observed from 2.12 × 10–26 A2/Hz to 2.42 × 10–20 A2/Hz for noise spectral density and from 1.79 × 10–11 V2/Hz to 1.97 × 10− 5 V2/Hz for voltage noise spectral density. The device reliability observation for LTFET device suggested that the small variation in all the device parameters in the temperature range of 250 K to 350 K.

Approximate computing has appeared as a good solution to limited energy, error-tolerant applications like image processing with a trade-off between efficiency and accuracy. This paper introduces three new approximate full adder (AFA) circuits—prop_AFA1, prop_AFA2, and prop_AFA3 based on carbon nanotube field-effect transistor (CNTFET) technology and the gate diffusion input (GDI) method, incorporating dynamic-threshold (DT) control to enhance stability and performance. The designs realise impressive reductions in transistor count (6–8 per cell), leading to considerable improvements in power, delay, power-delay product (PDP), and power-delay-area product (PDAP) over the currently known AFAs. Prop_AFA1 gives the overall best performance with 22 nW power, 2.64 aJ PDP, and 126.7 PDAP units in 8-bit RCAs with 96.44% PDAP improvement over GDI_AFA. Prop_AFA3 has 68.5% reduced power and 92.8% reduced PDAP compared to NxFA. The NMED values are 0.243, 0.167, and 0.272 for prop_AFA1, prop_AFA2, and prop_AFA3, respectively, of which prop_AFA2 gives maximum output accuracy. Upon incorporation into 8-bit and 16-bit RCAs and tested in image smoothness filters, the proposed architectures demonstrate higher PDP, with prop_AFA1 being superior to prop_AFA2 by 50% and prop_AFA2 performing better than prop_AFA3 by 78.6%. These findings identify the proposed AFAs as viable contenders for next-generation low-power, high-efficiency VLSI systems for approximate arithmetic and image processing computations.

Speaker recognition (SR) refers to the means of personification through voice distinctiveness and it has been studied over many decades. Recently, owing to new advancements, SR has become a popular domain for study. The paper introduces the Self-Attention Augmented Wasserstein Generative Adversarial Network (SAA-WGAN) model along with the Hybrid Frilled Lizard Humboldt Squid Optimizer to be used on SR. It aims to recognize a speaker by extracting audio signals of voiceprints from a public dataset, followed by a model called Multi-Layer Adaptive Guided Side Window Box Filtering, applied for noise elimination in audio samples. After which, relevant features are extracted from the input signal using Fast Discrete Curvelet Transform (FDCT). In addition, the Fennec Fox optimization (FFO) model selects the most beneficial features. Then, the selected features are used by SAA-WGAN to perform SR based on speaker ID identification corresponding to each input voiceprint. To enhance the weight parameters of the SAA-WGAN model, a Hybrid Frilled Lizard Humboldt Squid Optimization Model (Hyb-FL-HSO) is proposed, combining optimization models such as FLO and HSOA. The suggested technique is implemented in Python. The strategy’s efficacy is comprehensively evaluated using evaluation metrics like accuracy, Matthew’s correlation coefficient (MCC), recall, kappa coefficient (KC), positive predictive value (PPV), and computation time (CT) and it is compared with other conventional methods. The overall accuracy of 98.9%, MCC of 96.9%, recall of 98.5%, and CT of 190.21s on enhancing the performance of SR.