Analog Integrated Circuits and Signal Processing最新文献

The rise of mobile technologies and cloud computing has increased the importance of efficient energy consumption. Due to parallelism, high voltage conversion ratios, and large supply currents, power losses are rapidly increasing. This issue can be managed by on-package voltage stacking, where the current is recycled between multiple cores. Current mismatch between serially connected cores however produces a noise voltage between the cores. Differential power processing (DPP) converters are a potential solution to this issue. In the current work, a power efficient, load-to-load synchronous buck converter operating within a voltage stacked system is examined. The buck converter is evaluated under very high current demand, where the core currents in a voltage stacked system reach a tenfold difference. A compact model to characterize the voltage drop in serially stacked systems is also described. Furthermore, a circuit topology to increase the power efficiency of this converter is proposed. By using an interleaved system with different active phases, the inductance in the converter can be changed, which produces variable frequency operation, resulting in increased power efficiency due to lower switching losses. The power efficiency of the converter is increased by up to 8% as compared to constant frequency operation, achieving a range between 89% to 99%.

In this paper, a monopole-based flower-shaped 4-element multiple-input multiple-output antenna is designed for 4G Long-term evolution bands, 5G sub-6 GHz bands, Wifi-5 and Wifi-6 bands applications. The proposed model is designed and fabricated on low cost FR4 material with a dielectric constant of 4.4 and compactness of 54 × 54 mm² (0.51 λ₀ × 0.51 λ₀, where λ₀ measured at the lower band) size, having the height of 1.6 mm. The single radiating patch of size 26 × 20 mm², and it works in the frequency range of 3.34 to 6.32 GHz. Later, four single radiators are placed in an orthogonal manner for isolation enhancement. The working band of the proposed model is 2.88 to 6.12 GHz with isolation more than 15 dB for adjacent elements and better than 20 dB for diagonal elements. The stable radiation patterns and high radiation efficiency values above 90% are achieved in the entire working region. A minimum gain of 2.75 dBi and maximum gain of 5.25 dBi is attained. The diversity characteristics of the proposed model are checked with low Envelope correlation coefficient, high Diversity gain, low Channel capacity loss, good Mean effective gain, and acceptable Total active reflection coefficient values. The proposed model is developed and validated with simulated results, which are in good agreement.

Modern telecommunication systems require high-efficiency modulations with high PAPR. To have high efficiency while being linear, a linearization technique must be implemented. One of the efficient methods for linearization is the digital pre-distortion method. In this paper, a digital pre-distortion method using different types of neural networks is used to linearize PA. A six-port receiver in the digital pre-distortion loop is used to demodulate the output of the PA to the baseband and linearize the PA in the baseband. Using this receiver has reduced the cost, noise, and complexity of the demodulator used in the pre-distortion circuit. Adjacent channel power ratio (ACPR) has been used as a performance metric. According to the results, the BiLSTM network used in this paper is associated with a severe reduction in complexity and a significant improvement in the ACPR parameter compared to the other types of BiLSTM network previously used for linearization. It is observed that for the three input signals 16QAM, 64QAM, and OFDM with 600 MHz bandwidth, the maximum improvement in ACPR parameter using BiLSTM network is 25.2dB, 23.1dB, and 22.5dB in X-Band, respectively.

This paper presents a mixed-mode on-chip automatic frequency tuning technique to achieve a process-invariant lowpass cut-off frequency for biopotential amplifiers. It comprises of a sine-like test signal generation circuit, a digital scheme to minimize the deviations in the frequency of the test signal, a programmable switched capacitor array acting as the load of the biopotential amplifier, and a peak detector based digital capacitor selection logic. Results obtained show that the proposed technique curtails the deviation of the cut-off frequency across process (and temperature) variations. The complete scheme implemented in UMC 0.18 (upmu)m CMOS technology consumes only 1.02 (upmu)W average power approximately with 1.8 V supply. Moreover the complete tuning mechanism lasts for less than half a minute only. Its low power consumption and implementation on analog platform makes it integrable with the standard portable biomedical systems intended for remote monitoring.

This article presents a comprehensive examination of the design, implementation, as well as analysis of a true random number generator (TRNG). The TRNG utilizes an all-digital phase-locked loop (ADPLL) that incorporates a finite impulse response (FIR) filter as the digital loop filter. The TRNG is implemented on the Artix 7 (XC7A35T-CPG236-1) FPGA board, leveraging the Xilinx Vivado v.2015.2 design suite. The computation of the coefficients for a third-order broadcast low pass digital FIR filter is performed via the Keiser window technique. The MATLAB filter design and analysis tool is utilized for the computation of filter coefficients. Following the application of the XOR-corrector post-processing method to mitigate bias in the sequence, the proposed designs of ADPLL-based TRNGs successfully generated an unbiased stochastic random number. These designs achieved an overall throughput of 200 Mbps for both configurations. The initial proposed design for a TRNG based on a Finite Impulse response-all-digital phase-locked loop (FIR-ADPLL), referred to as FAT-1, exhibits a power consumption of 0.072 W. In contrast, the subsequent proposed TRNG design, also based on a FIR-ADPLL, known as FAT-2, demonstrates a slightly higher power consumption of 0.074 W. The bitstream that is obtained is assessed for randomness through the application of the NIST test, which is conducted after post-processing. The Artrix-7 field-programmable gate array board is utilized to establish a connection with the DSO for the purpose of capturing the waveforms produced by the TRNG. Both of the suggested designs for FIR-based all-digital phase-locked loop true random number generators successfully underwent testing according to the NIST SP 800-22 standard. This indicates that these designs exhibit strong compatibility with a wide range of industrial applications, such as network security, cybersecurity, banking security, smart cards, RFID tags, the internet of things, and industrial internet of things.

This paper reports, the enhanced electrical parameters of sub-10 nm High-k SOI GaN FinFET by implementing fin optimization approach using TCAD simulation. The results show that as the fin aspect ratio (AR) increases, keeping the channel cross-sectional area constant, the static and analog performance of the suggested device enhances. On current of 0.15 mA, higher switching ratio (I_ON/I_OFF) ratio (1.74 × 10⁹), reduced subthreshold swing (by 20%), and higher intrinsic gain has achieved for High-k SOI GaN FinFET having a higher fin AR (3.75) as compared to the lower fin aspect ratio (1.67) owing to the significant reduction in short channel effects. For more insight into the static/analog performances of the device; some other parameters such as transconductance (g_m), energy band profile, surface potential, output conductance (g_d), output resistance (R_o), and early voltage have also been investigated under fin optimization approach (fin aspect ratio modulation). Thus, the enhanced static/analog performances of the High-k SOI GaN FinFET clear the way for RFIC design.

To quickly and accurately locate the fault location and fault parameter deviation of analog circuits, a novel incipient fault diagnosis method based on multi-channel one-dimensional residual networks (MC-1D-ResNet) and wavelet packet transform(WPT) is proposed in this paper. The WPT is employed to preprocess the time-domain response signals of analog circuit, and the proposed MC-1D-ResNet is utilized for feature mining and fault classification.The two-level WPT is first carried out on the time-domain response signal to generate one approximate signal and three detailed signals. Secondly, MC-1D-ResNet further performs feature mining on approximate signals and three detailed signals, and realizes fault diagnosis. Through simulation analysis, the proposed method is fully evaluated with the Sallen-Key bandpass filter circuit and the four-op-amp biquad high-pass filter circuit. Even in complex Four-op-amp biquad high-pass filtering circuits, the diagnostic accuracy can reach 99.74%. This article also designs a hardware testing platform based on FPGA, and conduct actual fault diagnosis tests on the four-op-amp biquad high-pass filter circuit. The results show that the average accuracy of 50 actual diagnoses for each type of fault in the circuit was 97.80%.

Networks on Chip (NoCs) are a crucial component in modern System on Chips (SoCs), which provide the communication infrastructure for various processing elements such as CPUs, GPUs, DSPs, and other IPs. As a result, security is a critical aspect of NoCs, and it is essential to protect them from various security threats such as information leakage, denial of service attacks, and unauthorized access. The communication over NoCs carries sensitive and confidential information, which needs to be protected from unauthorized access, interception, or tampering. A Hybrid Secure technique is proposed in this research paper to protect the data during NoC transmission. The Noekeon and RSA algorithms are combined to create the hybrid secure algorithm for NoC architecture. The Noekeon algorithm provides a high level of security, efficiency, flexibility, and resistance to side-channel attacks, making it an ideal choice for securing communication in NoC and other applications. The RSA encryption algorithm is modified to minimize the number of calculations. The proposed hybrid secure algorithm is tested on 4 × 4 2D mesh NoC architecture. The average throughput of the proposed algorithm is increased to 64% and 51% latency is reduced when compared to existing research work.

Microstrip antennas are in high demand because of their low profile and lightweight, leading to a recent surge in the need for low-profile antennas for wireless communications. Due to the growing significance of wireless communication in recent years, very inventive research has been conducted. By extending current trends, microstrip antennas provide solutions for various problems. A heart-shaped microstrip patch antenna was introduced in this proposed methodology. The shape of the microstrip patch antenna dimensions are 29 mm × 32 mm × 1.6 mm. The FR-4 substrate material is used in a heart-shaped antenna with a tangent loss is 0.02 and a dielectric constant is 4.4. the high-frequency structure simulator software is used to design and implement a heart-shaped microstrip patch antenna. The patch features four inverted L-shaped slots and one S-shaped slot to provide multiple resonant frequencies for satellite and WI-FI connectivity. At 0.9 GHz, 1.4 GHz, and 2.45 GHz, the antenna is in use. Its two lower working frequency bands show good symmetry in its radiation patterns. The antenna covers a range of frequencies, including WLAN (5.15–5.35 GHz), 5G (5.725–5.825 GHz), TD-LTE (B-TrunC) (1.447–1.467 GHz), LTE42/43 (3.4–3.8 GHz), WiMAX (3.3–3.8 GHz), 5G band n78 (3.4–3.8 GHz), and more bands. Furthermore, the measurement and construction of the prototype are finished. The results show that its gains at 0.9 GHz, 1.4 GHz, and 2.45 GHz are − 32.2 dBi, − 18.8 dBi, and − 19.1 dBi.

Content Addressable Memory (CAM) is utilized in Artificial Neural Networks, data compression, IP packet filtering, and network routers due to its high performance in the microprocessor. However, the use of CAM is limited because of its increased power consumption, especially in high capacitive Match-Lines (ML). The activation of every comparison circuit on every clock cycle is primarily responsible for the significant power dissipation, which leads to increased recharge activity and multiple transition occurrences in the ML. In order to overcome this issue, a novel Common Match Line Scheme (CMS) with a Pull Up/Pull Down (PUPD) Circuit is proposed. The new design of the CMS CAM architecture leverages by utilizing these technique, the mismatched tagline entries are kept in the pre-discharged phases, and only the matching tagline entry gets charged. Consequently, these approaches effectively reduce pre-charge activity and mitigate evaluate-power, thereby alleviating power dissipation concerns associated with CAM 13–45% and reducing delay 3–16% while comparing to the existing architectures without significant impact on the performance of the processor. Proposed CMS CAM outperforms the existing architectures in terms of noise also with minimal area overhead and it is a technology independent one which can be used in high performance microprocessor systems.