Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629815
Chen-Yang Pan, K. Cheng, S. Gupta
In this paper, a comprehensive macromodel for transistor level faults in an operational amplifier is developed. With the observation that faulty behavior at output may result from interfacing error in addition to the faulty component, parameters associated with input and output characteristics are incorporated. Test generation and fault classification are addressed for stand-alone opamps. A high fault coverage is achieved by a proposed testing strategy. Transistor level short/bridging faults are analyzed and classified into catastrophic faults and parametric faults. Based on the macromodels for parametric faults, faults simulation is performed for an active filter. We found many parametric faults in the active filter cannot be detected by traditional functional testing. A DFT scheme alone with a current testing strategy to improve fault coverage is proposed.
{"title":"A Comprehensive Fault Macromodel For Opamps","authors":"Chen-Yang Pan, K. Cheng, S. Gupta","doi":"10.1109/ICCAD.1994.629815","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629815","url":null,"abstract":"In this paper, a comprehensive macromodel for transistor level faults in an operational amplifier is developed. With the observation that faulty behavior at output may result from interfacing error in addition to the faulty component, parameters associated with input and output characteristics are incorporated. Test generation and fault classification are addressed for stand-alone opamps. A high fault coverage is achieved by a proposed testing strategy. Transistor level short/bridging faults are analyzed and classified into catastrophic faults and parametric faults. Based on the macromodels for parametric faults, faults simulation is performed for an active filter. We found many parametric faults in the active filter cannot be detected by traditional functional testing. A DFT scheme alone with a current testing strategy to improve fault coverage is proposed.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76736868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629786
Smita Bakshi, D. Gajski
Exploration plays an important role in the design of high-performance pipelines. We propose an exploration strategy for varying three design parameters by using a performance-constrained component selection and pipelining algorithm on different “architectures”. The architecture is specified manually by using a mix of behavioral and structural constructs, while the component selection and pipelining is performed automatically using our algorithms. Results on two industrial-strength DSP systems, indicate the effectiveness of our strategy in exploring a large design space within a matter of seconds.
{"title":"Design Exploration For High-performance Pipelines","authors":"Smita Bakshi, D. Gajski","doi":"10.1109/ICCAD.1994.629786","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629786","url":null,"abstract":"Exploration plays an important role in the design of high-performance pipelines. We propose an exploration strategy for varying three design parameters by using a performance-constrained component selection and pipelining algorithm on different “architectures”. The architecture is specified manually by using a mix of behavioral and structural constructs, while the component selection and pipelining is performed automatically using our algorithms. Results on two industrial-strength DSP systems, indicate the effectiveness of our strategy in exploring a large design space within a matter of seconds.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77987853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629752
S. Hellebrand, H. Wunderlich
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the overall number of flipflops can be reduced, and the fault coverage and system speed can be enhanced. The presented algorithm constructs realizations of a given finite state machine specification which can be trivially implemented by a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space of suitable realizations, which avoids the computational overhead of previously published algorithms.
{"title":"An Efficient Procedure For The Synthesis Of Fast Self-testable Controller Structures","authors":"S. Hellebrand, H. Wunderlich","doi":"10.1109/ICCAD.1994.629752","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629752","url":null,"abstract":"The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the overall number of flipflops can be reduced, and the fault coverage and system speed can be enhanced. The presented algorithm constructs realizations of a given finite state machine specification which can be trivially implemented by a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space of suitable realizations, which avoids the computational overhead of previously published algorithms.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73410743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629774
M. Linderman, M. Leeser
Current extended value set dynamic timing analyzers are not sophisticated enough to detect the subtle timing relationships upon which timing-critical systems depend, and exhaustive simulation achieves very accurate results but at tremendous computational cost. MTV is a simulator that strikes a balance between accuracy and efficiency. MTV is more accurate than other extended value set simulators because it respects the ordering of events. It is more efficient than exhaustive simulators because it efficiently simulates overlapping events and requires only a single waveform to represent a signal. Features of MTV include: elimination of common ambiguity, symbolic delays, correlated delays, and sophisticated algorithms to detect ordered events. This paper concludes with simulation results from the ISCAS85 benchmark suite.
{"title":"Simulation Of Digital Circuits In The Presence of Uncertainty","authors":"M. Linderman, M. Leeser","doi":"10.1109/ICCAD.1994.629774","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629774","url":null,"abstract":"Current extended value set dynamic timing analyzers are not sophisticated enough to detect the subtle timing relationships upon which timing-critical systems depend, and exhaustive simulation achieves very accurate results but at tremendous computational cost. MTV is a simulator that strikes a balance between accuracy and efficiency.\u0000MTV is more accurate than other extended value set simulators because it respects the ordering of events. It is more efficient than exhaustive simulators because it efficiently simulates overlapping events and requires only a single waveform to represent a signal. Features of MTV include: elimination of common ambiguity, symbolic delays, correlated delays, and sophisticated algorithms to detect ordered events. This paper concludes with simulation results from the ISCAS85 benchmark suite.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79274146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629780
J. Chung, Chung-Kuan Cheng
Given a topology of clock tree and a library of buffers, we propose an efficient skew sensitivity minimization algorithm using dynamic programming approach. Our algorithm finds the optimum buffer sizes, its insertion levels in the clock tree, and optimum wire widths to minimize the skew sensitivity under manufacturing variations. Careful fine tuning by shifting buffer locations at the last stage preserves the minimum skew sensitivity property and reduces the interconnect length. For a given clock tree of n points and a library of s different buffer sizes, the run time of the presented algorithm is O(log3n•s2). Experimental results show a significant reduction of clock skews ranging from 87 times to 144 times compared to the clock skews before applying the proposed algorithm. We also observe a further reduction of the propagation delay of clock signals as a result of applying the proposed skew sensitivity algorithm.
{"title":"Skew Sensitivity Minimization Of Buffered Clock Tree","authors":"J. Chung, Chung-Kuan Cheng","doi":"10.1109/ICCAD.1994.629780","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629780","url":null,"abstract":"Given a topology of clock tree and a library of buffers, we propose an efficient skew sensitivity minimization algorithm using dynamic programming approach. Our algorithm finds the optimum buffer sizes, its insertion levels in the clock tree, and optimum wire widths to minimize the skew sensitivity under manufacturing variations. Careful fine tuning by shifting buffer locations at the last stage preserves the minimum skew sensitivity property and reduces the interconnect length. For a given clock tree of <italic>n</italic> points and a library of <italic>s</italic> different buffer sizes, the run time of the presented algorithm is <italic>O</italic>(log<supscrpt>3</supscrpt><italic>n</italic>•<italic>s</italic><supscrpt>2</supscrpt>).\u0000Experimental results show a significant reduction of clock skews ranging from 87 times to 144 times compared to the clock skews before applying the proposed algorithm. We also observe a further reduction of the propagation delay of clock signals as a result of applying the proposed skew sensitivity algorithm.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84555797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629749
M. Potkonjak, J. Rabaey
Given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalent algorithms. We demonstrate an extraordinary potential of algorithm selection for achieving high throughput, low cost, and low power implementations. We introduce an efficient technique for low-bound evaluation of the throughput and cost during algorithm selection and propose a relaxation-based heuristic for throughput optimization. We also present an algorithm for cost optimization using algorithm selection. The effectiveness of methodology and algorithms is illustrated using examples.
{"title":"Algorithm Selection: A Quantitative Computation-intensive Optimization Approach","authors":"M. Potkonjak, J. Rabaey","doi":"10.1109/ICCAD.1994.629749","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629749","url":null,"abstract":"Given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalent algorithms. We demonstrate an extraordinary potential of algorithm selection for achieving high throughput, low cost, and low power implementations.\u0000We introduce an efficient technique for low-bound evaluation of the throughput and cost during algorithm selection and propose a relaxation-based heuristic for throughput optimization. We also present an algorithm for cost optimization using algorithm selection. The effectiveness of methodology and algorithms is illustrated using examples.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81788913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629890
Toshinobu Ono
This paper presents a new method of selecting scan flip-flops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned into many small subcircuits which can be dealt with separately by a test pattern generator. This permits easy automatic test pattern generation for arbitrarily large sequential circuits. Algorithms of selecting scan FFs to allow such partitioning and of scheduling tests for subcircuits are given. Experimental results show that the proposed method makes it possible to generate test patterns for extra large sequential circuits which previous approaches cannot deal with.
{"title":"Selecting Partial Scan Flip-flops For Circuit Partitioning","authors":"Toshinobu Ono","doi":"10.1109/ICCAD.1994.629890","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629890","url":null,"abstract":"This paper presents a new method of selecting scan flip-flops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned into many small subcircuits which can be dealt with separately by a test pattern generator. This permits easy automatic test pattern generation for arbitrarily large sequential circuits. Algorithms of selecting scan FFs to allow such partitioning and of scheduling tests for subcircuits are given. Experimental results show that the proposed method makes it possible to generate test patterns for extra large sequential circuits which previous approaches cannot deal with.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77732639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629747
M. Alidina, J. Monteiro, S. Devadas, Abhijit Ghosh, M. Papaefthymiou
We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation. We present an automatic method of synthesizing precomputational logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay.
{"title":"Precomputation-based Sequential Logic Optimization For Low Power","authors":"M. Alidina, J. Monteiro, S. Devadas, Abhijit Ghosh, M. Papaefthymiou","doi":"10.1109/ICCAD.1994.629747","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629747","url":null,"abstract":"We address the problem of optimizing logic-level sequential circuits for low power. We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle. We present two different precomputation architectures which exploit this observation.\u0000We present an automatic method of synthesizing precomputational logic so as to achieve maximal reductions in power dissipation. We present experimental results on various sequential circuits. Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89314042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629760
Chih-Chang Lin, M. Marek-Sadowska, Duane Gatlin
In this paper the problem of selecting an appropriate programmable cell structure for FPGA architecture design is addressed. The cells studied here can be configured to the desired functionality by applying input permutation, negation, bridging or constant assignment, or output negation. A general methodology to determine logic description of such cells, which are capable of being configured to a given set of functions is described. Experimental results suggest that the new cell behaves as well as the Actel 2 cell in terms of logic power but requires substantially less area and wiring overhead.
{"title":"Universal logic gate for FPGA design","authors":"Chih-Chang Lin, M. Marek-Sadowska, Duane Gatlin","doi":"10.1109/ICCAD.1994.629760","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629760","url":null,"abstract":"In this paper the problem of selecting an appropriate programmable cell structure for FPGA architecture design is addressed. The cells studied here can be configured to the desired functionality by applying input permutation, negation, bridging or constant assignment, or output negation. A general methodology to determine logic description of such cells, which are capable of being configured to a given set of functions is described.\u0000Experimental results suggest that the new cell behaves as well as the Actel 2 cell in terms of logic power but requires substantially less area and wiring overhead.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86666608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-11-06DOI: 10.1109/ICCAD.1994.629877
I. Pomeranz, S. Reddy
We consider the problem of correcting errors in a macro-based circuit. Our formulation of the problem allows the correction of errors that arise both in the context of design error correction, before the circuit is realized, and in the context where a physical circuit needs to be corrected. Two error classes are defined, namely, component errors and line errors. Both single and multiple errors are considered. Accurate correction procedures are given for single errors. Heuristics are given for correcting multiple errors. Experimental results are given to demonstrate the correction procedures presented.
{"title":"On Error Correction In Macro-based Circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ICCAD.1994.629877","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629877","url":null,"abstract":"We consider the problem of correcting errors in a macro-based circuit. Our formulation of the problem allows the correction of errors that arise both in the context of design error correction, before the circuit is realized, and in the context where a physical circuit needs to be corrected. Two error classes are defined, namely, component errors and line errors. Both single and multiple errors are considered. Accurate correction procedures are given for single errors. Heuristics are given for correcting multiple errors. Experimental results are given to demonstrate the correction procedures presented.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89138497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：