Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328371
M. Sadr
In this paper, an economic approach to the linearization of the differential transconductors is proposed and compared with the source degeneration approach used to linearize the conventional differential pairs. The application of the resulted transconductor as a negative resistor is presented. The linearity, noise, and power performances are simulated, discussed, and compared with the conventional differential pair's.
{"title":"A novel approach to the linearization of the differential transconductors","authors":"M. Sadr","doi":"10.1109/ISCAS.2004.1328371","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328371","url":null,"abstract":"In this paper, an economic approach to the linearization of the differential transconductors is proposed and compared with the source degeneration approach used to linearize the conventional differential pairs. The application of the resulted transconductor as a negative resistor is presented. The linearity, noise, and power performances are simulated, discussed, and compared with the conventional differential pair's.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"125 ","pages":"1020-1023"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ISCAS.2004.1328371","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72419206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-01DOI: 10.1109/ISCAS.2004.1328828
Guangming Shi, Liya Sun, Honghua Liu, Daojun Huang
{"title":"Dynamic nonlinear threshold decomposition algorithm for implementing stack filters","authors":"Guangming Shi, Liya Sun, Honghua Liu, Daojun Huang","doi":"10.1109/ISCAS.2004.1328828","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328828","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"75 1","pages":"641-644"},"PeriodicalIF":0.0,"publicationDate":"2004-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74982185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-25DOI: 10.1109/ISCAS.2003.1204955
D. Cafagna, G. Grassi
This paper presents an approach to generate new hyperchaotic attractors in a closed chain of Chua's circuits. By taking a ring of three circuits and by exploiting sine functions as non-linearities, the proposed technique enables 3D-scroll attractors to be generated. In particular, the paper shows that 3D-scroll dynamics can be easily designed by modifying six parameters related to the circuit nonlinearities.
{"title":"A new approach to generate hyperchaotic 3D-scroll attractors in a closed chain of Chua's circuits","authors":"D. Cafagna, G. Grassi","doi":"10.1109/ISCAS.2003.1204955","DOIUrl":"https://doi.org/10.1109/ISCAS.2003.1204955","url":null,"abstract":"This paper presents an approach to generate new hyperchaotic attractors in a closed chain of Chua's circuits. By taking a ring of three circuits and by exploiting sine functions as non-linearities, the proposed technique enables 3D-scroll attractors to be generated. In particular, the paper shows that 3D-scroll dynamics can be easily designed by modifying six parameters related to the circuit nonlinearities.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"4 1","pages":"60-63"},"PeriodicalIF":0.0,"publicationDate":"2003-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76034441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-05-25DOI: 10.1109/ISCAS.2003.1204961
F. Han, Xinghuo Yu, Guanrong Chen, Wenbo Liu, Yong Feng
This paper proposes a method of generating multi-scroll chaos using second-order linear systems with a hysteresis series. It shows that multi-scroll chaos can be produced in any direction in the phase plane. Furthermore, two-dimensional multi-scroll chaos can be generated as well. Both computer simulations and circuitry implementation have verified the multi-scroll chaos generation scheme.
{"title":"Generation of multi-scroll chaos using second-order linear systems with hysteresis","authors":"F. Han, Xinghuo Yu, Guanrong Chen, Wenbo Liu, Yong Feng","doi":"10.1109/ISCAS.2003.1204961","DOIUrl":"https://doi.org/10.1109/ISCAS.2003.1204961","url":null,"abstract":"This paper proposes a method of generating multi-scroll chaos using second-order linear systems with a hysteresis series. It shows that multi-scroll chaos can be produced in any direction in the phase plane. Furthermore, two-dimensional multi-scroll chaos can be generated as well. Both computer simulations and circuitry implementation have verified the multi-scroll chaos generation scheme.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"22 1","pages":"84-87"},"PeriodicalIF":0.0,"publicationDate":"2003-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77955607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-01-01DOI: 10.1109/ISCAS.2003.1205953
C. Kim, Soonhak Kwon, C. Hong, In-Gil Nam
In this paper, we propose a new bit-serial systolic array for computing division over GF(2") using the standard basis representation. Based on a modified version of the binary extended GCD algorithm, we obtain a new data dependence graph (DG) and design an efficient bit-serial systolic array for division over GF(2"). Analysis shows that the proposed array provides a significant reduction in both chip area and computational. delay time compared to previously proposed systolic arrays with the same U 0 format. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomials and has a unidirectional data flow and regularity, it is well suited for division circuit of elliptic curve cryptosystems (ECC).
{"title":"Efficient bit-serial systolic array for division over GF(2m)","authors":"C. Kim, Soonhak Kwon, C. Hong, In-Gil Nam","doi":"10.1109/ISCAS.2003.1205953","DOIUrl":"https://doi.org/10.1109/ISCAS.2003.1205953","url":null,"abstract":"In this paper, we propose a new bit-serial systolic array for computing division over GF(2\") using the standard basis representation. Based on a modified version of the binary extended GCD algorithm, we obtain a new data dependence graph (DG) and design an efficient bit-serial systolic array for division over GF(2\"). Analysis shows that the proposed array provides a significant reduction in both chip area and computational. delay time compared to previously proposed systolic arrays with the same U 0 format. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomials and has a unidirectional data flow and regularity, it is well suited for division circuit of elliptic curve cryptosystems (ECC).","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"520 1","pages":"252-255"},"PeriodicalIF":0.0,"publicationDate":"2003-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77055863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-06DOI: 10.1109/ISCAS.2001.921451
M. Brucoli, D. Cafagna, L. Carnimeo
In this paper an approach to achieve a complete practical synchronization of hyperchaotic circuits with parameter mismatch via an impulsive scalar signal is presented. The chosen scalar signal is constituted by a sequence of samples of selected state variables alternatively transmitted for identical time frames. The approach is effectively applied to hyperchaotic circuits with parameter mismatch constituted by two bidirectionally coupled Chua's oscillators.
{"title":"Complete practical synchronization of hyperchaotic circuits via a scalar signal","authors":"M. Brucoli, D. Cafagna, L. Carnimeo","doi":"10.1109/ISCAS.2001.921451","DOIUrl":"https://doi.org/10.1109/ISCAS.2001.921451","url":null,"abstract":"In this paper an approach to achieve a complete practical synchronization of hyperchaotic circuits with parameter mismatch via an impulsive scalar signal is presented. The chosen scalar signal is constituted by a sequence of samples of selected state variables alternatively transmitted for identical time frames. The approach is effectively applied to hyperchaotic circuits with parameter mismatch constituted by two bidirectionally coupled Chua's oscillators.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"29 1","pages":"791-794"},"PeriodicalIF":0.0,"publicationDate":"2001-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73216434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856168
J. Harrison, N. Weste
Analytic limitations on the noise transfer function of sigma-delta modulators are derived. The noise transfer function magnitude in decibels integrated against frequency sums to at least zero. An excess delay of one sample in the modulator feedback loop is found to be detrimental for lowpass modulators.
{"title":"Analytic limitations on sigma-delta modulator performance","authors":"J. Harrison, N. Weste","doi":"10.1109/ISCAS.2000.856168","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856168","url":null,"abstract":"Analytic limitations on the noise transfer function of sigma-delta modulators are derived. The noise transfer function magnitude in decibels integrated against frequency sums to at least zero. An excess delay of one sample in the modulator feedback loop is found to be detrimental for lowpass modulators.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"70 1","pages":"746-749"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83795364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-28DOI: 10.1109/ISCAS.2000.856172
J. Morizio, M. Hoke, T. Koçak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, M. Hood, Ward Huffman, Takashi Okuda, H. Noda, Yasuo Morimoto, T. Kumamoto, M. Ishiwaki, H. Kondoh, Masao Nakaya, Takahiro Miki
{"title":"SNDR sensitivity analysis for cascaded ΣΔ modulators","authors":"J. Morizio, M. Hoke, T. Koçak, C. Geddie, C. Hughes, J. Perry, S. Madhavapeddi, M. Hood, Ward Huffman, Takashi Okuda, H. Noda, Yasuo Morimoto, T. Kumamoto, M. Ishiwaki, H. Kondoh, Masao Nakaya, Takahiro Miki","doi":"10.1109/ISCAS.2000.856172","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856172","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"25 1","pages":"765"},"PeriodicalIF":0.0,"publicationDate":"2000-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82776766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-01-01DOI: 10.1109/ISCAS.2000.856064
N. Filiol, T. Riley, M. Copeland, C. Plett
{"title":"A receive path ΔΣ frequency to digital converter","authors":"N. Filiol, T. Riley, M. Copeland, C. Plett","doi":"10.1109/ISCAS.2000.856064","DOIUrl":"https://doi.org/10.1109/ISCAS.2000.856064","url":null,"abstract":"","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"41 1","pages":"331-334"},"PeriodicalIF":0.0,"publicationDate":"2000-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86407283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-05-30DOI: 10.1109/ISCAS.1999.777539
D. Shmilovitz, D. Czarkowski, Z. Zabar
A general approach to evaluate the converter dynamics versus the necessary dynamics for operation as an active power factor corrector is introduced. A simple criterion is developed in the time domain that enables characterization of converter topology and component values for APFC applications. This criterion can be incorporated in the design of APFC circuits to define the upper bounds on reactive component values whereas the lower bound is derived from the ripple requirements. The input current distortions caused by a converter whose characteristics do not meet the minimum requirements are calculated for a boost converter, which is chosen as a particular example.
{"title":"Simple criteria to evaluate converter dynamics suitability for operation in active power factor correction systems","authors":"D. Shmilovitz, D. Czarkowski, Z. Zabar","doi":"10.1109/ISCAS.1999.777539","DOIUrl":"https://doi.org/10.1109/ISCAS.1999.777539","url":null,"abstract":"A general approach to evaluate the converter dynamics versus the necessary dynamics for operation as an active power factor corrector is introduced. A simple criterion is developed in the time domain that enables characterization of converter topology and component values for APFC applications. This criterion can be incorporated in the design of APFC circuits to define the upper bounds on reactive component values whereas the lower bound is derived from the ripple requirements. The input current distortions caused by a converter whose characteristics do not meet the minimum requirements are calculated for a boost converter, which is chosen as a particular example.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"14 1","pages":"176-179"},"PeriodicalIF":0.0,"publicationDate":"1999-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73268089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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