Chip最新文献

Reconfigurable field-effect transistors (R-FETs) that can dynamically reconfigure the transistor polarity, from n-type to p-type channel or vice versa, represent a promising new approach to reduce the logic complexity and granularity of programmable electronics. Although R-FETs have been successfully demonstrated upon silicon nanowire (SiNW) channels, a pair of extra program gates is still needed to control the source/drain (S/D) contacts. In this work, we propose a rather simple single gate R-FET structure with an asymmetric S/D electrode contact, where the FET channel polarity can be altered by changing the sign of channel bias V_ds. These R-FETs were fabricated upon an orderly array of planar SiNW channels, grown via in-plane solid-liquid-solid mechanism, and contacted by Ti/Al and Pt/Au at the S/D electrodes, respectively. Remarkably, this channel-bias-controlled R-FET strategy has been successfully testified and implemented upon both p-type-doped (with indium dopants) or n-type-doped (phosphorus) SiNW channels, whereas the R-FET prototypes demonstrate an impressive high I_on/off ratio of > 10⁶ and a steep subthreshold swing of 79 mV/dec. These results indicate a rather simple, compact and generic enough R-FET strategy for the construction of a new generation of SiNW-based programmable and low-power electronics.

The commercially available 4000-Watt continuous-wave (CW) Erbium-doped-fiber laser, emitting at the 1567-nm wavelength where the atmosphere has high transmission, provides an opportunity for harvesting electric power at remote “off the grid” locations using a multi-module photovoltaic (PV) “receiver” panel. This paper proposes a 32-element monocrystalline thick-layer Germanium PV panel for efficient harvesting of a collimated 1.13-m-diam beam. The 0.78-m² PV panel is constructed from commercial Ge wafers. For incident CW laser-beam power in the 4000 to 10,000 W range, our thermal, electrical, and infrared simulations predict 660 to 1510 Watts of electrical output at the panel temperatures of 350 to 423 K.

With the development of 5G technology and increasing chip integration, traditional active cooling methods struggle to meet the growing thermal demands of chips. Thermoelectric coolers (TECs) have garnered great attention due to their rapid response, significant cooling differentials, strong compatibility, high stability and controllable device dimensions. In this review, starting from the fundamental principles of thermoelectric cooling and device design, high-performance thermoelectric cooling materials are summarized, and the progress of advanced on-chip TECs is comprehensively reviewed. Finally, the paper outlines the challenges and opportunities in TEC design, performance and applications, laying great emphasis on the critical role of thermoelectric cooling in addressing the evolving thermal management requirements in the era of emerging chip technologies.

Two-dimensional metal chalcogenides have garnered significant attention as promising candidates for novel neuromorphic synaptic devices due to their exceptional structural and optoelectronic properties. However, achieving large-scale integration and practical applications of synaptic chips has proven to be challenging due to significant hurdles in materials preparation and the absence of effective nanofabrication techniques. In a recent breakthrough, we introduced a revolutionary allopatric defect-modulated Fe₇S₈@MoS₂ synaptic heterostructure, which demonstrated remarkable optoelectronic synaptic response capabilities. Building upon this achievement, our current study takes a step further by presenting a sulfurization-seeding synergetic growth strategy, enabling the large-scale and arrayed preparation of Fe₇S₈@MoS₂ heterostructures. Moreover, a three-dimensional vertical integration technique was developed for the fabrication of arrayed optoelectronic synaptic chips. Notably, we have successfully simulated the visual persistence function of the human eye with the adoption of the arrayed chip. Our synaptic devices exhibit a remarkable ability to replicate the preprocessing functions of the human visual system, resulting in significantly improved noise reduction and image recognition efficiency. This study might mark an important milestone in advancing the field of optoelectronic synaptic devices, which significantly prompts the development of mature integrated visual perception chips.

Tunneling-based static random-access memory (SRAM) devices have been developed to fulfill the demands of high density and low power, and the performance of SRAMs has also been greatly promoted. However, for a long time, there has not been a silicon based tunneling device with both high peak valley current ratio (PVCR) and practicality, which remains a gap to be filled. Based on the existing work, the current manuscript proposed the concept of a new silicon-based tunneling device, i.e., the silicon cross-coupled gated tunneling diode (Si XTD), which is quite simple in structure and almost completely compatible with mainstream technology. With technology computer aided design (TCAD) simulations, it has been validated that this type of device not only exhibits significant negative-differential-resistance (NDR) behavior with PVCRs up to 10⁶, but also possesses reasonable process margins. Moreover, SPICE simulation showed the great potential of such devices to achieve ultralow-power tunneling-based SRAMs with standby power down to 10⁻¹² W.

Inspired by the structure and principles of the human brain, spike neural networks (SNNs) appear as the latest generation of artificial neural networks, attracting significant and universal attention due to their remarkable low-energy transmission by pulse and powerful capability for large-scale parallel computation. Current research on artificial neural networks gradually change from software simulation into hardware implementation. However, such a process is fraught with challenges. In particular, memristors are highly anticipated hardware candidates owing to their fast-programming speed, low power consumption, and compatibility with the complementary metal–oxide semiconductor (CMOS) technology. In this review, we start from the basic principles of SNNs, and then introduced memristor-based technologies for hardware implementation of SNNs, and further discuss the feasibility of integrating customized algorithm optimization to promote efficient and energy-saving SNN hardware systems. Finally, based on the existing memristor technology, we summarize the current problems and challenges in this field.

Silicon technology offers the enticing opportunity for monolithic integration of quantum and classical electronic circuits. However, the power consumption levels of classical electronics may compromise the local chip temperature and hence affect the fidelity of qubit operations. In the current work, a quantum-dot-based thermometer embedded in an industry-standard silicon field-effect transistor (FET) was adopted to assess the local temperature increase produced by an active FET placed in close proximity. The impact of both static and dynamic operation regimes was thoroughly investigated. When the FET was operated statically, a power budget of 45 nW at 100-nm separation was found, whereas at 216 μm, the power budget was raised to 150 μW. Negligible temperature increase for the switch frequencies tested up to 10 MHz was observed when operating dynamically. The current work introduced a method to accurately map out the available power budget at a distance from a solid-state quantum processor, and indicated the possible conditions under which cryoelectronics circuits may allow the operation of hybrid quantum–classical systems.