Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931588
F. Buscemi, E. Piccinini, R. Brunetti, M. Rudan
The numerical approach to quantum transport in nanowires and nanotubes in the ballistic regime requires an accurate numerical solution of the coupled Schrödinger and Poisson equations. Here the feasibility of a 5th-order method is proved for the longitudinal part of the wave equation. The effectiveness of the method is demonstrated on a ballistic device.
{"title":"High-order solution scheme for transport in low-D devices","authors":"F. Buscemi, E. Piccinini, R. Brunetti, M. Rudan","doi":"10.1109/SISPAD.2014.6931588","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931588","url":null,"abstract":"The numerical approach to quantum transport in nanowires and nanotubes in the ballistic regime requires an accurate numerical solution of the coupled Schrödinger and Poisson equations. Here the feasibility of a 5th-order method is proved for the longitudinal part of the wave equation. The effectiveness of the method is demonstrated on a ballistic device.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115236586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-20DOI: 10.1109/SISPAD.2014.6931637
Akito Suzuki, Takanobu Watanabe, Y. Kamakura, T. Kamioka
We have realized the full-scale whole device EMC/MD simulation including source and drain regions by utilizing graphic processing unit. The transfer characteristic of a gate-all-around nanowire Si MOSFET is simulated by reproducing the field effect of the surrounding gate electrode with spreading charged particles on the gate insulator layer. We have found an appreciable impact of the random dopant distribution (RDF) in source and drain regions on the drain current variability. Furthermore, the dynamic fluctuation of the drain current is found to be increase as the channel length decreases. The EMC/MD simulation powered by GPU is a useful method to investigate the dynamic fluctuation as well as the statistical device-to-device variability of nano-scale FETs.
{"title":"Full-scale whole device EMC/MD simulation of Si nanowire transistor including source and drain regions by utilizing graphic processing units","authors":"Akito Suzuki, Takanobu Watanabe, Y. Kamakura, T. Kamioka","doi":"10.1109/SISPAD.2014.6931637","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931637","url":null,"abstract":"We have realized the full-scale whole device EMC/MD simulation including source and drain regions by utilizing graphic processing unit. The transfer characteristic of a gate-all-around nanowire Si MOSFET is simulated by reproducing the field effect of the surrounding gate electrode with spreading charged particles on the gate insulator layer. We have found an appreciable impact of the random dopant distribution (RDF) in source and drain regions on the drain current variability. Furthermore, the dynamic fluctuation of the drain current is found to be increase as the channel length decreases. The EMC/MD simulation powered by GPU is a useful method to investigate the dynamic fluctuation as well as the statistical device-to-device variability of nano-scale FETs.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"2459 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931582
C. Jungemann, C. Zimmermann
The hopping transport in organic semiconductors produces characteristic frequency dependencies of the admittance and noise, which are calculated in this paper for the first time based on the master equation approach, where noise is evaluated by the Langevin approach and a modified Ramo-Shockley theorem. At low frequencies and low injection the non-equilibrium noise is found to be shot noise in the framework of this model.
{"title":"DC, AC and noise simulation of organic semiconductor devices based on the master equation","authors":"C. Jungemann, C. Zimmermann","doi":"10.1109/SISPAD.2014.6931582","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931582","url":null,"abstract":"The hopping transport in organic semiconductors produces characteristic frequency dependencies of the admittance and noise, which are calculated in this paper for the first time based on the master equation approach, where noise is evaluated by the Langevin approach and a modified Ramo-Shockley theorem. At low frequencies and low injection the non-equilibrium noise is found to be shot noise in the framework of this model.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133240669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931638
Yu He, T. Kubis, M. Povolotskyi, J. Fonseca, Gerhard Klimeck
Quantum transport algorithms such as QTBM and NEGF/RGF have been efficiently implemented in the multi-scale simulation tool NEMO5 by taking advantage of the Hamiltonian's characteristics of nanowires without explicit spinorbit coupling in the tight binding representation. Benchmarks in a 3nm diameter, 20 nm length Si nanowire in atomistic 10 band tight binding representation demonstrate 3-5 times performance improvement over the current state of the literatures.
{"title":"Quantum transport in NEMO5: Algorithm improvements and high performance implementation","authors":"Yu He, T. Kubis, M. Povolotskyi, J. Fonseca, Gerhard Klimeck","doi":"10.1109/SISPAD.2014.6931638","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931638","url":null,"abstract":"Quantum transport algorithms such as QTBM and NEGF/RGF have been efficiently implemented in the multi-scale simulation tool NEMO5 by taking advantage of the Hamiltonian's characteristics of nanowires without explicit spinorbit coupling in the tight binding representation. Benchmarks in a 3nm diameter, 20 nm length Si nanowire in atomistic 10 band tight binding representation demonstrate 3-5 times performance improvement over the current state of the literatures.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127635881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931626
J. Colinge
Improvements in electrostatic channel control allow FinFETs and trigate FETs to extend Moore's law down to gate lengths of 15-20nm. Further scaling may require the better control that is provided by multigate devices. Using multigate FET architectures, gate length scaling down to 5 and 3 nm has been demonstrated experimentally and theoretically, respectively. At these dimensions, quantum confinement begins to appear and new effects such as drain current oscillations and tunneling through soft barriers can be observed. FET to SET and metal-semiconductor transitions resulting from quantum confinement present opportunities for new types of devices.
{"title":"Multigate transistors: Pushing Moore's law to the limit","authors":"J. Colinge","doi":"10.1109/SISPAD.2014.6931626","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931626","url":null,"abstract":"Improvements in electrostatic channel control allow FinFETs and trigate FETs to extend Moore's law down to gate lengths of 15-20nm. Further scaling may require the better control that is provided by multigate devices. Using multigate FET architectures, gate length scaling down to 5 and 3 nm has been demonstrated experimentally and theoretically, respectively. At these dimensions, quantum confinement begins to appear and new effects such as drain current oscillations and tunneling through soft barriers can be observed. FET to SET and metal-semiconductor transitions resulting from quantum confinement present opportunities for new types of devices.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931583
Z. Lun, Shuhuan Liu, Y. He, Yi Hou, K. Zhao, G. Du, Xiaoyan Liu, Yi Wang
This paper presents a comprehensive investigation on retention behavior for three-dimensional charge trapping NAND flash memory by two-dimensional self-consistent simulation. Major physical mechanisms, including tunneling, charge trapping and de-trapping process as well as drift-diffusion have been incorporated into the simulator. The developed simulator is able to describe the charge transport along the bitline and in vertical direction in the memory structure. This work aims to help to design and optimize three-dimensional stackable CT-NAND architectures.
{"title":"Investigation of retention behavior for 3D charge trapping NAND flash memory by 2D self-consistent simulation","authors":"Z. Lun, Shuhuan Liu, Y. He, Yi Hou, K. Zhao, G. Du, Xiaoyan Liu, Yi Wang","doi":"10.1109/SISPAD.2014.6931583","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931583","url":null,"abstract":"This paper presents a comprehensive investigation on retention behavior for three-dimensional charge trapping NAND flash memory by two-dimensional self-consistent simulation. Major physical mechanisms, including tunneling, charge trapping and de-trapping process as well as drift-diffusion have been incorporated into the simulator. The developed simulator is able to describe the charge transport along the bitline and in vertical direction in the memory structure. This work aims to help to design and optimize three-dimensional stackable CT-NAND architectures.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116032272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931610
W. Zisser, H. Ceric, J. Weinbub, S. Selberherr
Through silicon vias are the components in three-dimensional integrated circuits, which are responsible for the vertical connection inside the dies. In this work we present studies about the reliability of open through silicon vias against electromigration. A two-step approach is followed. In the first step the stress development of a void free structure is analyzed by means of simulation to find the locations, where voids due to stress are most probably nucleated. In the second step, voids are placed in the through silicon vias and their evolution is traced including the increase of resistance. The resistance raises more than linearly in time and shows an abrupt open circuit failure. Simulations were carried out for different currents and fitted to Black's equation. These results are in good agreement with results of time accelerated electromigration tests.
{"title":"Electromigration induced resistance increase in open TSVs","authors":"W. Zisser, H. Ceric, J. Weinbub, S. Selberherr","doi":"10.1109/SISPAD.2014.6931610","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931610","url":null,"abstract":"Through silicon vias are the components in three-dimensional integrated circuits, which are responsible for the vertical connection inside the dies. In this work we present studies about the reliability of open through silicon vias against electromigration. A two-step approach is followed. In the first step the stress development of a void free structure is analyzed by means of simulation to find the locations, where voids due to stress are most probably nucleated. In the second step, voids are placed in the through silicon vias and their evolution is traced including the increase of resistance. The resistance raises more than linearly in time and shows an abrupt open circuit failure. Simulations were carried out for different currents and fitted to Black's equation. These results are in good agreement with results of time accelerated electromigration tests.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126178949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931617
Sabareesh Nikhil Chinta, S. Mittal, P. Debashis, U. Ganguly
In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (VT) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error <; 10%) with a decrease in computation time of over 300×. The method thus proposed provides a fast and accurate way of estimating σVT from LER specifications of a fin patterning technology.
{"title":"A FinFET LER VT variability estimation scheme with 300× efficiency improvement","authors":"Sabareesh Nikhil Chinta, S. Mittal, P. Debashis, U. Ganguly","doi":"10.1109/SISPAD.2014.6931617","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931617","url":null,"abstract":"In this paper, we have proposed a computationally efficient method to evaluate threshold voltage (VT) variability due to Line Edge Roughness (LER) in sub-20nm node FinFETs. For channel lengths less than 15 nm, the variability in threshold voltage may be estimated to a great accuracy (error <; 10%) with a decrease in computation time of over 300×. The method thus proposed provides a fast and accurate way of estimating σVT from LER specifications of a fin patterning technology.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124840478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931614
M. Bellini, J. Vobecký
Continuous advances in computer hardware and solving algorithm enable more pervasive use of 3D TCAD simulations for both nanoscale and power semiconductor devices. However, while BiMOS power semiconductor devices such as IGBTs require relatively small 3D simulated structures (of the order of fa 10×10×1000/im3), bipolar power devices such as thyristors require much larger simulated structures of the order of fa 10 mm3. This work presents large scale 3D simulations of Phase Controlled Thyristors and describes the technique used to reduce computation times to extents compatible with industrial practice. 3D TCAD is used to understand the impact of cathode shorts on figures of merit such as the breakdown voltage and dV/dt.
{"title":"Large-scale 3D TCAD study of the impact of shorts in phase controlled thyristors","authors":"M. Bellini, J. Vobecký","doi":"10.1109/SISPAD.2014.6931614","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931614","url":null,"abstract":"Continuous advances in computer hardware and solving algorithm enable more pervasive use of 3D TCAD simulations for both nanoscale and power semiconductor devices. However, while BiMOS power semiconductor devices such as IGBTs require relatively small 3D simulated structures (of the order of fa 10×10×1000/im3), bipolar power devices such as thyristors require much larger simulated structures of the order of fa 10 mm3. This work presents large scale 3D simulations of Phase Controlled Thyristors and describes the technique used to reduce computation times to extents compatible with industrial practice. 3D TCAD is used to understand the impact of cathode shorts on figures of merit such as the breakdown voltage and dV/dt.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130842740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/SISPAD.2014.6931600
D. Fried, K. Greiner, D. Faken, M. Kamon, A. Pap, R. Patz, M. Stock, J. Lehto, S. Breit
We present a predictive modeling approach for pattern-dependent etch processes implemented in a 3D virtual fabrication software platform. This technique combines long-range effects using design data and short-range effects using predictive 3D models of the design-technology interaction. For the first time, this type of pattern-dependent predictive capability is integrated into a full 3D virtual fabrication environment to enable fast accurate structural modeling of complex advanced technologies such as FinFETs, 3D memory and BEOL interconnect.
{"title":"Predictive modeling of pattern-dependent etch effects in large-area fully-integrated 3D virtual fabrication","authors":"D. Fried, K. Greiner, D. Faken, M. Kamon, A. Pap, R. Patz, M. Stock, J. Lehto, S. Breit","doi":"10.1109/SISPAD.2014.6931600","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931600","url":null,"abstract":"We present a predictive modeling approach for pattern-dependent etch processes implemented in a 3D virtual fabrication software platform. This technique combines long-range effects using design data and short-range effects using predictive 3D models of the design-technology interaction. For the first time, this type of pattern-dependent predictive capability is integrated into a full 3D virtual fabrication environment to enable fast accurate structural modeling of complex advanced technologies such as FinFETs, 3D memory and BEOL interconnect.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124189776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：