Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931597
Yasuyuki Ookura, Nobuhiko Kato, Shin-ichiroh Kobayashi, T. Kuwabara, Masanori Harada, Kentaro Yamaguchi, H. Koike
A new 3-D TCAD system has been proposed aiming close coupling of first-principles calculator, process, and device simulators in response to requirements for ultra-small to high-power semiconductor devices. Using the first-principles calculator Schottky-barrier height has been derived. In the process simulator, a robust and high-speed topographical algorithm has been newly proposed and thus easier handling of complicated 3-D structure has been provided. And a 3-D effect due to arsenic deactivation has been demonstrated. In the device simulator, robust calculation for high-voltage breakdown characteristics of wide-gap devices has been demonstrated.
{"title":"A three-dimensional TCAD system focused on power and nano-scaled devices applications","authors":"Yasuyuki Ookura, Nobuhiko Kato, Shin-ichiroh Kobayashi, T. Kuwabara, Masanori Harada, Kentaro Yamaguchi, H. Koike","doi":"10.1109/SISPAD.2014.6931597","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931597","url":null,"abstract":"A new 3-D TCAD system has been proposed aiming close coupling of first-principles calculator, process, and device simulators in response to requirements for ultra-small to high-power semiconductor devices. Using the first-principles calculator Schottky-barrier height has been derived. In the process simulator, a robust and high-speed topographical algorithm has been newly proposed and thus easier handling of complicated 3-D structure has been provided. And a 3-D effect due to arsenic deactivation has been demonstrated. In the device simulator, robust calculation for high-voltage breakdown characteristics of wide-gap devices has been demonstrated.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124181018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931558
Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse Engel, X. Guan, H. Wong
We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.
{"title":"Verilog-A compact model for oxide-based resistive random access memory (RRAM)","authors":"Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse Engel, X. Guan, H. Wong","doi":"10.1109/SISPAD.2014.6931558","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931558","url":null,"abstract":"We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"19 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131840061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931577
O. Baumgartner, Z. Stanojević, L. Filipovic, A. Grill, T. Grasser, H. Kosina, M. Karner
In this paper, a comprehensive investigation of quantum transport in nanoscaled gallium nitride (GaN) high electron mobility transistors (HEMTs) is presented. A simulation model for quantum transport in nanodevices on unstructured grids in arbitrary dimension and for arbitrary crystal directions has been developed. The model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method. A new approach to reduce its computational effort has been realized. The model has been used to achieve a consistent treatment of quantization and transport effects in deeply scaled asymmetric GaN HEMTs. The self-consistent electron concentration, conduction band edges and ballistic current have been calculated. The effects of strain relaxation at the heterostructure interfaces on the potential and carrier concentration have been shown.
{"title":"Investigation of quantum transport in nanoscaled GaN high electron mobility transistors","authors":"O. Baumgartner, Z. Stanojević, L. Filipovic, A. Grill, T. Grasser, H. Kosina, M. Karner","doi":"10.1109/SISPAD.2014.6931577","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931577","url":null,"abstract":"In this paper, a comprehensive investigation of quantum transport in nanoscaled gallium nitride (GaN) high electron mobility transistors (HEMTs) is presented. A simulation model for quantum transport in nanodevices on unstructured grids in arbitrary dimension and for arbitrary crystal directions has been developed. The model has been implemented as part of the Vienna-Schrödinger-Poisson simulation and modeling framework. The transport formalism is based on the quantum transmitting boundary method. A new approach to reduce its computational effort has been realized. The model has been used to achieve a consistent treatment of quantization and transport effects in deeply scaled asymmetric GaN HEMTs. The self-consistent electron concentration, conduction band edges and ballistic current have been calculated. The effects of strain relaxation at the heterostructure interfaces on the potential and carrier concentration have been shown.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931618
Wen-Tsung Huang, Yiming Li
In this work, the DC characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFET induced by different line edge roughness (LER) is for the first time studied by using experimentally validated 3D device simulation. By considering a time-domain Gaussian noise function, we compare four types of LER: Fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFET with respect to different fin angles. The resist-LER and sidewall-LER have large impact on characteristics fluctuation. For each type of LER, the Vth fluctuation is comparable among fin angles.
{"title":"The impact of fin/sidewall/gate line edge roughness on trapezoidal bulk FinFET devices","authors":"Wen-Tsung Huang, Yiming Li","doi":"10.1109/SISPAD.2014.6931618","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931618","url":null,"abstract":"In this work, the DC characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFET induced by different line edge roughness (LER) is for the first time studied by using experimentally validated 3D device simulation. By considering a time-domain Gaussian noise function, we compare four types of LER: Fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFET with respect to different fin angles. The resist-LER and sidewall-LER have large impact on characteristics fluctuation. For each type of LER, the Vth fluctuation is comparable among fin angles.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127654056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931568
G. Rzepa, W. Goes, G. Rott, K. Rott, M. Karner, C. Kernstock, B. Kaczer, H. Reisinger, T. Grasser
Given the rapid recovery of the degradation induced by bias-temperature stress, the understanding and modeling of NBTI has been a challenge for nearly half a century. With the introduction of the time-dependent defect spectroscopy (TDDS), NBTI could be studied at the single defect level, confirming that it is dominated by a collection of first-order reactions rather then the previously invoked reaction-diffusion mechanism. The most intriguing feature of these first-order processes is the wide distribution of their time constants, which can be visualized in capture/emission time (CET) maps. In the following we clarify the microscopic link between individual defects seen in TDDS studies and the response of a large ensemble visible in the CET maps. In particular, we show how the distribution of the individual defect parameters can be extracted from measurements on large-area devices.
{"title":"Physical modeling of NBTI: From individual defects to devices","authors":"G. Rzepa, W. Goes, G. Rott, K. Rott, M. Karner, C. Kernstock, B. Kaczer, H. Reisinger, T. Grasser","doi":"10.1109/SISPAD.2014.6931568","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931568","url":null,"abstract":"Given the rapid recovery of the degradation induced by bias-temperature stress, the understanding and modeling of NBTI has been a challenge for nearly half a century. With the introduction of the time-dependent defect spectroscopy (TDDS), NBTI could be studied at the single defect level, confirming that it is dominated by a collection of first-order reactions rather then the previously invoked reaction-diffusion mechanism. The most intriguing feature of these first-order processes is the wide distribution of their time constants, which can be visualized in capture/emission time (CET) maps. In the following we clarify the microscopic link between individual defects seen in TDDS studies and the response of a large ensemble visible in the CET maps. In particular, we show how the distribution of the individual defect parameters can be extracted from measurements on large-area devices.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123054497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931585
K. Auluck, E. Kan, S. Rajwade
We present a physical circuit model for polarization reversal dynamics in ferroelectrics, which is implemented in Verilog-A, validated with PZT measurements and applicable in all operation modes for bulk, epitaxial and polycrystalline thin films. Consistent treatment of field-driven polarization not only gives accurate step-voltage responses across many decades in time, but also reproduces frequency and amplitude dependent P-E and I-V hysteresis loops for ferroelectric MIM capacitors. FE-RAM and gate-stack FE-FET circuit simulations are experimentally verified.
{"title":"A unified circuit model for ferroelectrics","authors":"K. Auluck, E. Kan, S. Rajwade","doi":"10.1109/SISPAD.2014.6931585","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931585","url":null,"abstract":"We present a physical circuit model for polarization reversal dynamics in ferroelectrics, which is implemented in Verilog-A, validated with PZT measurements and applicable in all operation modes for bulk, epitaxial and polycrystalline thin films. Consistent treatment of field-driven polarization not only gives accurate step-voltage responses across many decades in time, but also reproduces frequency and amplitude dependent P-E and I-V hysteresis loops for ferroelectric MIM capacitors. FE-RAM and gate-stack FE-FET circuit simulations are experimentally verified.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122856150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931631
Wai-kit Lee, Kasa Huang, Jim C. Liang, Juan-Yi Chen, Cheng Hsiao, Ke-Wei Su, Chung-Kai Lin, M. Jeng
In this paper, we discuss how to implement the self heating and aging models with TMI. Various examples about self heating and aging simulations with TMI methodology are shown in this paper. Without trading-off the accuracy, the one with proposed TMI approach for self heating simulations takes much shorter simulation time.
{"title":"Unifying self-heating and aging simulations with TMI2","authors":"Wai-kit Lee, Kasa Huang, Jim C. Liang, Juan-Yi Chen, Cheng Hsiao, Ke-Wei Su, Chung-Kai Lin, M. Jeng","doi":"10.1109/SISPAD.2014.6931631","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931631","url":null,"abstract":"In this paper, we discuss how to implement the self heating and aging models with TMI. Various examples about self heating and aging simulations with TMI methodology are shown in this paper. Without trading-off the accuracy, the one with proposed TMI approach for self heating simulations takes much shorter simulation time.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931627
G. Mil'nikov, N. Mori
The paper presents a method for quantum transport simulations in nanowire (NW) MOSFETs with inelastic scattering processes incorporated. An atomistic tight-binding Hamiltonian with realistic electron-phonon interaction is transformed into an equivalent low-dimensional transport model which can be easily used in full-scaled NEGF simulations. The utility of the method is demonstrated by computing IV characteristics in n-Si NW devices.
{"title":"Electron-phonon interaction in Si nanowire devices: Low field mobility and self-consistent EM NEGF simulations","authors":"G. Mil'nikov, N. Mori","doi":"10.1109/SISPAD.2014.6931627","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931627","url":null,"abstract":"The paper presents a method for quantum transport simulations in nanowire (NW) MOSFETs with inelastic scattering processes incorporated. An atomistic tight-binding Hamiltonian with realistic electron-phonon interaction is transformed into an equivalent low-dimensional transport model which can be easily used in full-scaled NEGF simulations. The utility of the method is demonstrated by computing IV characteristics in n-Si NW devices.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129717437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931624
Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara
0.5V operation and power-gating ability of nonvolatile SRAM (NV-SRAM) cell using pseudo-spin-FinFETs (PS-FinFETs) are investigated. The cell is configured so as to achieve a minimum occupied-area design, i.e., all the FinFETs used in the cell are designed with a single fin channel. The 0.5V operations are analyzed from various static noise margins (SNMs) for the normal operation and nonvolatile power-gating (NVPG) modes. The SNMs for all the normal (hold, read, and write) operations are satisfactorily large even for the 0.5V operation, although the wordline underdrive technique is needed to be introduced for the read operation. The SNMs for the store operations of the NVPG mode also satisfy requirements for the shutdown and wake-up operations, when bias-assisted techniques are employed for the PS-FinFETs of the cell. Energy performance of the NV-SRAM cell is evaluated using break-even time (BET). A sufficiently short BET applicable to fine-grained NVPG of microprocessors and SoCs can be achieved even for the 0.5V operation with the various bias-assisted techniques. In addition, store-free shutdown architecture is further effective at reducing BET. Average power of the cell can be dramatically reduced by 0.5V operation, although the reduction rate depends on the leakage current during shutdown mode and the proportion of shutdown period. This FinFET-based NV-SRAM cell using pseudo-spin-transistor architecture is promising for NVPG of low-voltage logic systems.
{"title":"0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture","authors":"Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara","doi":"10.1109/SISPAD.2014.6931624","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931624","url":null,"abstract":"0.5V operation and power-gating ability of nonvolatile SRAM (NV-SRAM) cell using pseudo-spin-FinFETs (PS-FinFETs) are investigated. The cell is configured so as to achieve a minimum occupied-area design, i.e., all the FinFETs used in the cell are designed with a single fin channel. The 0.5V operations are analyzed from various static noise margins (SNMs) for the normal operation and nonvolatile power-gating (NVPG) modes. The SNMs for all the normal (hold, read, and write) operations are satisfactorily large even for the 0.5V operation, although the wordline underdrive technique is needed to be introduced for the read operation. The SNMs for the store operations of the NVPG mode also satisfy requirements for the shutdown and wake-up operations, when bias-assisted techniques are employed for the PS-FinFETs of the cell. Energy performance of the NV-SRAM cell is evaluated using break-even time (BET). A sufficiently short BET applicable to fine-grained NVPG of microprocessors and SoCs can be achieved even for the 0.5V operation with the various bias-assisted techniques. In addition, store-free shutdown architecture is further effective at reducing BET. Average power of the cell can be dramatically reduced by 0.5V operation, although the reduction rate depends on the leakage current during shutdown mode and the proportion of shutdown period. This FinFET-based NV-SRAM cell using pseudo-spin-transistor architecture is promising for NVPG of low-voltage logic systems.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122284834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931609
Lidija Filipović, O. Baumgartner, Z. Stanojević, H. Kosina
This works presents a study of the location of 3D band-to-band tunneling barriers in order to create improved tunneling devices. Specifically, the i-Si/n-InAs junction is considered. The large lattice mismatch in this material system causes dislocations in the interface and traps in the bandgap. Alternative device configurations are considered that move the tunneling away from the physical interface, therefore reducing the the effects of lattice mismatch on tunneling current.
{"title":"BTB tunneling in InAs/Si heterojunctions","authors":"Lidija Filipović, O. Baumgartner, Z. Stanojević, H. Kosina","doi":"10.1109/SISPAD.2014.6931609","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931609","url":null,"abstract":"This works presents a study of the location of 3D band-to-band tunneling barriers in order to create improved tunneling devices. Specifically, the i-Si/n-InAs junction is considered. The large lattice mismatch in this material system causes dislocations in the interface and traps in the bandgap. Alternative device configurations are considered that move the tunneling away from the physical interface, therefore reducing the the effects of lattice mismatch on tunneling current.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131498640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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