Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931625
X. Mou, L. Register, S. Banerjee
It has been proposed that superfluid excitonic condensates may be possible in dielectrically separated graphene layers or other two-dimensional materials. This possibility was the basis for the proposed ultra-low power Bilayer pseudoSpin Field-effect Transistor (BiSFET). Previously, we developed an atomistic tight-binding quantum transport simulator, including the non-local exchange interaction, and used it to demonstrate the essential excitonic superfluid transport physics which underlies the proposed BiSFET in presence of such a condensate. Here we report on extension of that work to analyze dependencies on device scaling and the condensate strength of BiSFET performance and required device parameters including interlayer conductance, and critical current and voltage.
{"title":"Interplay among Bilayer pseudoSpin field-effect transistor (BiSFET) performance, BiSFET scaling and condensate strength","authors":"X. Mou, L. Register, S. Banerjee","doi":"10.1109/SISPAD.2014.6931625","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931625","url":null,"abstract":"It has been proposed that superfluid excitonic condensates may be possible in dielectrically separated graphene layers or other two-dimensional materials. This possibility was the basis for the proposed ultra-low power Bilayer pseudoSpin Field-effect Transistor (BiSFET). Previously, we developed an atomistic tight-binding quantum transport simulator, including the non-local exchange interaction, and used it to demonstrate the essential excitonic superfluid transport physics which underlies the proposed BiSFET in presence of such a condensate. Here we report on extension of that work to analyze dependencies on device scaling and the condensate strength of BiSFET performance and required device parameters including interlayer conductance, and critical current and voltage.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129547349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931558
Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse Engel, X. Guan, H. Wong
We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.
{"title":"Verilog-A compact model for oxide-based resistive random access memory (RRAM)","authors":"Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse Engel, X. Guan, H. Wong","doi":"10.1109/SISPAD.2014.6931558","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931558","url":null,"abstract":"We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"19 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131840061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931592
He Wang, Wenshen Li, Jinyu Zhang, Yan Wang, Zhiping Yu
Conditions for terahertz (THz) radiation due to the plasma-wave instability in the channel of HEMTs are re-examined by considering the electron viscosity in carrier hydrodynamic transport. Not only the DC output I-V characteristics are affected, but also the window for plasma-wave instability is altered by the term with viscosity in the transport equation. The solution procedure and numerical study are presented. The analysis has been applied to recent experimental work and it is shown that the device parameters required for plasma-wave instability are more stringent than those reported in the up-to-date THz emission experiments.
{"title":"The role of electron viscosity on plasma-wave instability in HEMTs","authors":"He Wang, Wenshen Li, Jinyu Zhang, Yan Wang, Zhiping Yu","doi":"10.1109/SISPAD.2014.6931592","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931592","url":null,"abstract":"Conditions for terahertz (THz) radiation due to the plasma-wave instability in the channel of HEMTs are re-examined by considering the electron viscosity in carrier hydrodynamic transport. Not only the DC output I-V characteristics are affected, but also the window for plasma-wave instability is altered by the term with viscosity in the transport equation. The solution procedure and numerical study are presented. The analysis has been applied to recent experimental work and it is shown that the device parameters required for plasma-wave instability are more stringent than those reported in the up-to-date THz emission experiments.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"396 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124170907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931597
Yasuyuki Ookura, Nobuhiko Kato, Shin-ichiroh Kobayashi, T. Kuwabara, Masanori Harada, Kentaro Yamaguchi, H. Koike
A new 3-D TCAD system has been proposed aiming close coupling of first-principles calculator, process, and device simulators in response to requirements for ultra-small to high-power semiconductor devices. Using the first-principles calculator Schottky-barrier height has been derived. In the process simulator, a robust and high-speed topographical algorithm has been newly proposed and thus easier handling of complicated 3-D structure has been provided. And a 3-D effect due to arsenic deactivation has been demonstrated. In the device simulator, robust calculation for high-voltage breakdown characteristics of wide-gap devices has been demonstrated.
{"title":"A three-dimensional TCAD system focused on power and nano-scaled devices applications","authors":"Yasuyuki Ookura, Nobuhiko Kato, Shin-ichiroh Kobayashi, T. Kuwabara, Masanori Harada, Kentaro Yamaguchi, H. Koike","doi":"10.1109/SISPAD.2014.6931597","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931597","url":null,"abstract":"A new 3-D TCAD system has been proposed aiming close coupling of first-principles calculator, process, and device simulators in response to requirements for ultra-small to high-power semiconductor devices. Using the first-principles calculator Schottky-barrier height has been derived. In the process simulator, a robust and high-speed topographical algorithm has been newly proposed and thus easier handling of complicated 3-D structure has been provided. And a 3-D effect due to arsenic deactivation has been demonstrated. In the device simulator, robust calculation for high-voltage breakdown characteristics of wide-gap devices has been demonstrated.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124181018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931627
G. Mil'nikov, N. Mori
The paper presents a method for quantum transport simulations in nanowire (NW) MOSFETs with inelastic scattering processes incorporated. An atomistic tight-binding Hamiltonian with realistic electron-phonon interaction is transformed into an equivalent low-dimensional transport model which can be easily used in full-scaled NEGF simulations. The utility of the method is demonstrated by computing IV characteristics in n-Si NW devices.
{"title":"Electron-phonon interaction in Si nanowire devices: Low field mobility and self-consistent EM NEGF simulations","authors":"G. Mil'nikov, N. Mori","doi":"10.1109/SISPAD.2014.6931627","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931627","url":null,"abstract":"The paper presents a method for quantum transport simulations in nanowire (NW) MOSFETs with inelastic scattering processes incorporated. An atomistic tight-binding Hamiltonian with realistic electron-phonon interaction is transformed into an equivalent low-dimensional transport model which can be easily used in full-scaled NEGF simulations. The utility of the method is demonstrated by computing IV characteristics in n-Si NW devices.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129717437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931631
Wai-kit Lee, Kasa Huang, Jim C. Liang, Juan-Yi Chen, Cheng Hsiao, Ke-Wei Su, Chung-Kai Lin, M. Jeng
In this paper, we discuss how to implement the self heating and aging models with TMI. Various examples about self heating and aging simulations with TMI methodology are shown in this paper. Without trading-off the accuracy, the one with proposed TMI approach for self heating simulations takes much shorter simulation time.
{"title":"Unifying self-heating and aging simulations with TMI2","authors":"Wai-kit Lee, Kasa Huang, Jim C. Liang, Juan-Yi Chen, Cheng Hsiao, Ke-Wei Su, Chung-Kai Lin, M. Jeng","doi":"10.1109/SISPAD.2014.6931631","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931631","url":null,"abstract":"In this paper, we discuss how to implement the self heating and aging models with TMI. Various examples about self heating and aging simulations with TMI methodology are shown in this paper. Without trading-off the accuracy, the one with proposed TMI approach for self heating simulations takes much shorter simulation time.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931624
Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara
0.5V operation and power-gating ability of nonvolatile SRAM (NV-SRAM) cell using pseudo-spin-FinFETs (PS-FinFETs) are investigated. The cell is configured so as to achieve a minimum occupied-area design, i.e., all the FinFETs used in the cell are designed with a single fin channel. The 0.5V operations are analyzed from various static noise margins (SNMs) for the normal operation and nonvolatile power-gating (NVPG) modes. The SNMs for all the normal (hold, read, and write) operations are satisfactorily large even for the 0.5V operation, although the wordline underdrive technique is needed to be introduced for the read operation. The SNMs for the store operations of the NVPG mode also satisfy requirements for the shutdown and wake-up operations, when bias-assisted techniques are employed for the PS-FinFETs of the cell. Energy performance of the NV-SRAM cell is evaluated using break-even time (BET). A sufficiently short BET applicable to fine-grained NVPG of microprocessors and SoCs can be achieved even for the 0.5V operation with the various bias-assisted techniques. In addition, store-free shutdown architecture is further effective at reducing BET. Average power of the cell can be dramatically reduced by 0.5V operation, although the reduction rate depends on the leakage current during shutdown mode and the proportion of shutdown period. This FinFET-based NV-SRAM cell using pseudo-spin-transistor architecture is promising for NVPG of low-voltage logic systems.
{"title":"0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture","authors":"Y. Shuto, Shuu'ichirou Yamamoto, S. Sugahara","doi":"10.1109/SISPAD.2014.6931624","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931624","url":null,"abstract":"0.5V operation and power-gating ability of nonvolatile SRAM (NV-SRAM) cell using pseudo-spin-FinFETs (PS-FinFETs) are investigated. The cell is configured so as to achieve a minimum occupied-area design, i.e., all the FinFETs used in the cell are designed with a single fin channel. The 0.5V operations are analyzed from various static noise margins (SNMs) for the normal operation and nonvolatile power-gating (NVPG) modes. The SNMs for all the normal (hold, read, and write) operations are satisfactorily large even for the 0.5V operation, although the wordline underdrive technique is needed to be introduced for the read operation. The SNMs for the store operations of the NVPG mode also satisfy requirements for the shutdown and wake-up operations, when bias-assisted techniques are employed for the PS-FinFETs of the cell. Energy performance of the NV-SRAM cell is evaluated using break-even time (BET). A sufficiently short BET applicable to fine-grained NVPG of microprocessors and SoCs can be achieved even for the 0.5V operation with the various bias-assisted techniques. In addition, store-free shutdown architecture is further effective at reducing BET. Average power of the cell can be dramatically reduced by 0.5V operation, although the reduction rate depends on the leakage current during shutdown mode and the proportion of shutdown period. This FinFET-based NV-SRAM cell using pseudo-spin-transistor architecture is promising for NVPG of low-voltage logic systems.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122284834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931585
K. Auluck, E. Kan, S. Rajwade
We present a physical circuit model for polarization reversal dynamics in ferroelectrics, which is implemented in Verilog-A, validated with PZT measurements and applicable in all operation modes for bulk, epitaxial and polycrystalline thin films. Consistent treatment of field-driven polarization not only gives accurate step-voltage responses across many decades in time, but also reproduces frequency and amplitude dependent P-E and I-V hysteresis loops for ferroelectric MIM capacitors. FE-RAM and gate-stack FE-FET circuit simulations are experimentally verified.
{"title":"A unified circuit model for ferroelectrics","authors":"K. Auluck, E. Kan, S. Rajwade","doi":"10.1109/SISPAD.2014.6931585","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931585","url":null,"abstract":"We present a physical circuit model for polarization reversal dynamics in ferroelectrics, which is implemented in Verilog-A, validated with PZT measurements and applicable in all operation modes for bulk, epitaxial and polycrystalline thin films. Consistent treatment of field-driven polarization not only gives accurate step-voltage responses across many decades in time, but also reproduces frequency and amplitude dependent P-E and I-V hysteresis loops for ferroelectric MIM capacitors. FE-RAM and gate-stack FE-FET circuit simulations are experimentally verified.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122856150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931629
H. Ryu, Jongseob Kim, K. Hong
Sensitivity of Phosphorus dopant placement to the channel size of highly doped silicon nanowires is studied using a 10-band sp3 d5 s* tight-binding approach coupled to self-consistent simulations. Extending the simulation scope to realistically sized nanowires, we observed that uniform doping does not necessarily reduce the channel energy compared to surface-oriented doping when the diameter of a nanowire cross-section is smaller than 20 nm, whilst uniform doping lowers the energy, making the channel more stable at larger cross-sections. This size-dependency, firmly connected to the recent experiment, is understood well in detail by investigating channel electrostatics.
{"title":"Channel-size dependent dopant placement in silicon nanowires","authors":"H. Ryu, Jongseob Kim, K. Hong","doi":"10.1109/SISPAD.2014.6931629","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931629","url":null,"abstract":"Sensitivity of Phosphorus dopant placement to the channel size of highly doped silicon nanowires is studied using a 10-band sp3 d5 s* tight-binding approach coupled to self-consistent simulations. Extending the simulation scope to realistically sized nanowires, we observed that uniform doping does not necessarily reduce the channel energy compared to surface-oriented doping when the diameter of a nanowire cross-section is smaller than 20 nm, whilst uniform doping lowers the energy, making the channel more stable at larger cross-sections. This size-dependency, firmly connected to the recent experiment, is understood well in detail by investigating channel electrostatics.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128833617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-23DOI: 10.1109/SISPAD.2014.6931568
G. Rzepa, W. Goes, G. Rott, K. Rott, M. Karner, C. Kernstock, B. Kaczer, H. Reisinger, T. Grasser
Given the rapid recovery of the degradation induced by bias-temperature stress, the understanding and modeling of NBTI has been a challenge for nearly half a century. With the introduction of the time-dependent defect spectroscopy (TDDS), NBTI could be studied at the single defect level, confirming that it is dominated by a collection of first-order reactions rather then the previously invoked reaction-diffusion mechanism. The most intriguing feature of these first-order processes is the wide distribution of their time constants, which can be visualized in capture/emission time (CET) maps. In the following we clarify the microscopic link between individual defects seen in TDDS studies and the response of a large ensemble visible in the CET maps. In particular, we show how the distribution of the individual defect parameters can be extracted from measurements on large-area devices.
{"title":"Physical modeling of NBTI: From individual defects to devices","authors":"G. Rzepa, W. Goes, G. Rott, K. Rott, M. Karner, C. Kernstock, B. Kaczer, H. Reisinger, T. Grasser","doi":"10.1109/SISPAD.2014.6931568","DOIUrl":"https://doi.org/10.1109/SISPAD.2014.6931568","url":null,"abstract":"Given the rapid recovery of the degradation induced by bias-temperature stress, the understanding and modeling of NBTI has been a challenge for nearly half a century. With the introduction of the time-dependent defect spectroscopy (TDDS), NBTI could be studied at the single defect level, confirming that it is dominated by a collection of first-order reactions rather then the previously invoked reaction-diffusion mechanism. The most intriguing feature of these first-order processes is the wide distribution of their time constants, which can be visualized in capture/emission time (CET) maps. In the following we clarify the microscopic link between individual defects seen in TDDS studies and the response of a large ensemble visible in the CET maps. In particular, we show how the distribution of the individual defect parameters can be extracted from measurements on large-area devices.","PeriodicalId":101858,"journal":{"name":"2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123054497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：