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Two-Step Single-Slope ADC Utilizing Differential Ramps for CMOS Image Sensors 利用差分斜坡的两步式单斜坡 ADC,适用于 CMOS 图像传感器
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-18 DOI: 10.1007/s00034-024-02767-2
Dongxing Fang, Kaiming Nie, Ziyang Zhang, Jiangtao Xu

This paper presents a two-step single-slope (TS-SS) analog-to-digital converter (ADC) for CMOS image sensors (CIS). The proposed TS-SS ADC divides the pixel signal into small and large signal regions using a precomparator. When quantizing large pixel signals, the TS-SS ADC enters accelerated mode, which leverages the differential topology of the ramp generator to speed up quantization. The accelerated mode reduces the row cycle, resulting in a 31.3% reduction at 320 MHz clock from 27.3 to 18.75 µs. The designed 12-bit TS-SS ADC was designed in a 110 nm 1P4M CMOS technology, and its linearity was verified by process corner post-simulation and Monte Carlo simulation.

本文介绍了一种用于 CMOS 图像传感器(CIS)的两步单斜率(TS-SS)模数转换器(ADC)。所提出的 TS-SS ADC 利用预比较器将像素信号分为小信号区和大信号区。在量化大像素信号时,TS-SS ADC 进入加速模式,利用斜坡发生器的差分拓扑结构加快量化速度。加速模式缩短了行周期,使 320 MHz 时钟下的行周期从 27.3 µs 缩短到 18.75 µs,缩短了 31.3%。所设计的 12 位 TS-SS ADC 采用 110 nm 1P4M CMOS 技术设计,其线性度通过工艺拐角后仿真和蒙特卡罗仿真进行了验证。
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引用次数: 0
Accelerated Simulation of Passive Analog Circuits Over GPU Using Explicit Integration Methods 利用显式积分法在 GPU 上加速模拟无源模拟电路
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-16 DOI: 10.1007/s00034-024-02780-5
Ginés Doménech-Asensi, Tom J. Kazmierski

Analog circuits composed by large number of nodes in a tightly coupled structure pose significant challenges due to their prohibitive CPU simulation time. This work describes a method to speed up the simulation of such circuits by means of the combination of space state formulation of circuit equations with explicit integration methods parallelized over a many-core processor such as a GPU. Although stability of explicit techniques require smaller integration steps compared to implicit methods, the proposed method employs a fast estimate of the maximum allowed step size to guarantee numerical stability, which yields a shorter simulation time for increasing complexity circuit architectures. Moreover, the proposed technique can be straightforward parallelized on a many core architecture. The proposed method is demonstrated with two examples using constant and variable coefficients respectively: an RLC interconnect and a MOS-C network to perform Gaussian filtering of medium resolution images. The results obtained have been compared to a parallel version of SPICE and show improvements up to two orders of magnitude for transient simulations depending of the circuit size.

模拟电路由大量紧密耦合结构中的节点组成,由于其 CPU 仿真时间过长,给模拟电路带来了巨大挑战。这项工作描述了一种方法,通过将电路方程的空间状态表述与 GPU 等多核处理器上并行的显式积分方法相结合,来加快此类电路的仿真速度。虽然与隐式方法相比,显式技术的稳定性要求更小的积分步长,但所提出的方法采用了对最大允许步长的快速估算,以保证数值稳定性,从而缩短了复杂度不断增加的电路架构的仿真时间。此外,所提出的技术可以在多核架构上直接并行处理。我们用两个分别使用恒定系数和可变系数的示例来演示所提出的方法:一个 RLC 互联器和一个 MOS-C 网络,用于对中等分辨率图像进行高斯滤波。所获得的结果与并行版 SPICE 进行了比较,结果表明,根据电路的大小,瞬态仿真最多可提高两个数量级。
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引用次数: 0
Polar Logic XOR/XNOR Circuits Using a Single Current Conveyor 使用单电流传输器的极性逻辑 XOR/XNOR 电路
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-12 DOI: 10.1007/s00034-024-02768-1
Sudhanshu Maheshwari

The paper reports simple yet effective circuits for realizing XOR and XNOR logic operations with polarity, each employing a single current conveyor. The proposed polar logic circuits require four MOS switches and two resistors, besides a single CCII+ (second generation current conveyor), in each case. The new proposed circuits are simulated using 0.18 µm CMOS process parameters with a ± 1.8 V supply voltage and reference DC voltage of 1 V, thus enabling polar logic outputs. The polar output for logic 0 and 1 is in form of − 1 V and + 1 V respectively. The results included in support of the work are promising for future applications of the proposal in design of communication circuits. To facilitate better integration prospects, the proposed circuits are further simplified by removing one of the two used resistors and replacing CCII by CCCII (current controlled current conveyor). The simplified polar XOR gate is also verified through simulations. System design applications are expected to evolve from proposed work. The new proposed circuits are expected to significantly contribute to the advancement of circuit design.

本文报告了实现带极性的 XOR 和 XNOR 逻辑运算的简单而有效的电路,每种电路均采用单个电流传送器。除了一个 CCII+(第二代电流传输器)外,所提出的极性逻辑电路在每种情况下都需要四个 MOS 开关和两个电阻器。新提出的电路采用 0.18 µm CMOS 工艺参数进行仿真,电源电压为 ± 1.8 V,参考直流电压为 1 V,从而实现了极性逻辑输出。逻辑 0 和逻辑 1 的极性输出分别为 - 1 V 和 + 1 V。为支持这项工作而取得的成果为该提案在未来通信电路设计中的应用带来了希望。为了促进更好的集成前景,建议的电路进一步简化,去掉了两个电阻中的一个,并用 CCCII(电流控制电流传送器)取代了 CCII。简化后的极性 XOR 门也通过仿真进行了验证。预计系统设计应用将从提议的工作中得到发展。新提出的电路有望为电路设计的进步做出重大贡献。
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引用次数: 0
Finite-Time $$H_infty $$ Control for Time-Delayed Markovian Jump Nonlinear Systems with Parameter Uncertainties and Generally Uncertain Transition Rates 具有参数不确定性和一般不确定性转换率的时延马尔可夫跃迁非线性系统的有限时间 $$H_infty $$ 控制
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-08 DOI: 10.1007/s00034-024-02782-3
Chenyang Jiao, Juan Zhou

This paper mainly investigates the problem of finite-time (H_{infty }) control for a class of uncertain Markovian jump nonlinear systems (MJNSs) with time-varying delay and generally uncertain transition rates. By constructing the appropriate Lyapunov–Krasovskii functional and free weighting matrices, a novel criterion on finite-time boundedness for the MJNSs with (H_{infty }) performance is derived. We use a special way to deal with the bilinear terms, the mode-dependent state feedback controller is designed to ensure the (H_{infty }) finite-time boundedness of the closed-loop system in the forms of strict linear matrix inequalities. Finally, numerical and practical examples are given to demonstrate the effectiveness of the proposed method.

本文主要研究一类具有时变延迟和一般不确定转换率的不确定马尔可夫跃迁非线性系统(MJNSs)的有限时间(H_{infty })控制问题。通过构建适当的 Lyapunov-Krasovskii 函数和自由加权矩阵,我们得出了具有 (H_{infty }) 性能的 MJNS 的有限时间约束性新标准。我们使用一种特殊的方法来处理双线性项,设计了与模式相关的状态反馈控制器,以严格线性矩阵不等式的形式确保闭环系统的有限时间约束性。最后,给出了数值和实际例子来证明所提方法的有效性。
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引用次数: 0
Premature Infant Cry Classification via Elephant Herding Optimized Convolutional Gated Recurrent Neural Network 通过大象放牧优化卷积门控递归神经网络进行早产儿哭声分类
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-04 DOI: 10.1007/s00034-024-02764-5
V. Vaishnavi, M. Braveen, N. Muthukumaran, P. Poonkodi

Premature babies scream to make contact with their mothers or other people. Infants communicate via their screams in different ways based on the motivation behind their cries. A considerable amount of work and focus is required these days to preprocess, extract features, and classify audio signals. This research aims to propose a novel Elephant Herding Optimized Deep Convolutional Gated Recurrent Neural Network (EHO-DCGR net) for classifying cry signals from premature babies. Cry signals are first preprocessed to remove distortion caused by short sample times. MFCC (Mel-frequency cepstral coefficient), Power Normalized Cepstral Coefficients (PNCC), BFCC (Bark-frequency cepstral coefficient), and LPCC (Linear Prediction cepstral coefficient) are used to identify abnormal weeping through their prosodic aspects. The Elephant Herding optimization (EHO) algorithm is utilized for choosing the best features from the extracted set to form a fused feature matrix. These characteristics are then used to categorize premature baby cry sounds using the DCGR net. The proposed EHO-DCGR net effectiveness is measured by precision, specificity, recall, and F1-score, accuracy. According to experimental fallouts, the proposed EHO-DCGR net detects baby cry signals with an astounding 98.45% classification accuracy. From the experimental analysis, the EHO-DCGR Net increases the overall accuracy by 12.64%, 3.18%, 9.71% and 3.50% better than MFCC-SVM, DFFNN, SVM-RBF and SGDM respectively.

早产儿尖叫是为了与母亲或其他人取得联系。根据哭声背后的动机,婴儿通过尖叫以不同的方式进行交流。如今,对音频信号进行预处理、提取特征和分类需要大量的工作和关注。本研究旨在提出一种新颖的大象放牧优化深度卷积门控递归神经网络(EHO-DCGR net),用于对早产儿的哭声信号进行分类。首先对哭声信号进行预处理,以消除因采样时间短而造成的失真。采用 MFCC(梅尔频率前谱系数)、功率归一化前谱系数(PNCC)、BFCC(吠声频率前谱系数)和 LPCC(线性预测前谱系数),通过其前音方面来识别异常哭声。利用大象放牧优化(EHO)算法从提取的特征集中选择最佳特征,形成融合特征矩阵。然后使用 DCGR 网将这些特征用于早产婴儿哭声的分类。拟议的 EHO-DCGR 网的有效性通过精确度、特异性、召回率和 F1 分数、准确度来衡量。实验结果表明,拟议的 EHO-DCGR 网检测婴儿哭声信号的分类准确率高达 98.45%。从实验分析来看,EHO-DCGR 网络比 MFCC-SVM、DFFNN、SVM-RBF 和 SGDM 分别提高了 12.64%、3.18%、9.71% 和 3.50%。
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引用次数: 0
Regional Language Speech Recognition from Bone Conducted Speech Signals Through CCWT Algorithm 通过 CCWT 算法从骨传导语音信号识别地区语言语音
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-04 DOI: 10.1007/s00034-024-02733-y
Venkata Subbaiah Putta, A. Selwin Mich Priyadharson

Speech enhancement, or SE, is a method of converting an input speech signal into a target signal with improved quality of voice and readability. To hear the voice, the skeleton bone vibrates ultra smooth thanks to bone conduction. The benefits of Bone-Conducted Microphone (BCM) speech include noise reduction and enhanced communication quality in high-noise environments. To acquire signals and precisely model word phonemes, BCM relies on the placement of bones. Certain computer techniques are expensive and ineffective in simulating signal phonemes. Three wavelet transform techniques are presented in this work: complex continuous wavelet transforms (CCWT), steady wavelet transforms (SWT), and discrete wavelet transforms (DWT). The right ramp, the voice box, and the mastoid were the three distinct bony locations for which the speech intelligibility of the BCM signal was evaluated. The listener evaluated the comprehension of the speech after obtaining the BCM signal for Tamil words. Speech quality is enhanced by the location of the larynx bone in comparison to alternative calculation methods.

语音增强或 SE 是一种将输入语音信号转换为目标信号的方法,可提高语音质量和可读性。为了听到语音,骨骼会通过骨传导进行超平滑振动。骨传导麦克风(BCM)语音的优点包括在高噪音环境中降低噪音和提高通信质量。要获取信号并精确模拟单词音素,骨传导麦克风依赖于骨骼的位置。某些计算机技术在模拟信号音素方面既昂贵又无效。本文介绍了三种小波变换技术:复杂连续小波变换(CCWT)、稳定小波变换(SWT)和离散小波变换(DWT)。评估 BCM 信号语音清晰度的三个不同骨性位置分别是右斜坡、声箱和乳突。听者在获得泰米尔语单词的 BCM 信号后,对语音理解能力进行评估。与其他计算方法相比,喉骨位置可提高语音质量。
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引用次数: 0
Joint Underdetermined Blind Separation Using Cross Third-Order Cumulant and Tensor Decomposition 利用交叉三阶累积量和张量分解进行联合欠定盲分选
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-04 DOI: 10.1007/s00034-024-02757-4
Weilin Luo, Xiaobai Li, Hao Li, Hongbin Jin, Ruijuan Yang

To address the issues of poor anti-noise performance of second-order statistics and low estimation accuracy in previous joint underdetermined blind source separation (JUBSS) methods, we propose a novel JUBSS method based on the dependence between different data sets and the advantages of cross third-order cumulant in resisting distributed noise. The method involves several steps. Firstly, we calculate the cross third-order cumulant of multiple whitening data sets with different delays. Then, we stack several third-order cumulants into fourth-order tensors. Next, we decompose the fourth-order tensor using Canonical Polyadic through weight nonlinear least squares, which allows us to estimate the mixed matrix. Finally, depending on the independence of source signals, we propose a matrix diagonalization method to recover the source signal. Experiments demonstrate that the method effectively suppresses the influence of Gaussian noise and performs well in underdetermined, positive and overdetermined cases and produces a better performance than various common approaches. Specifically, for the 3 × 4 mixed model with signal-to-noise ratio of 20 dB, the average relative error is − 14.48 dB, the average similarity coefficient is 0.92 and the signal-to-interference ratio is 24.84 dB.

针对以往的联合欠定盲源分离(JUBSS)方法中二阶统计抗噪声性能差、估计精度低的问题,我们提出了一种基于不同数据集之间的依赖性和交叉三阶积的抗分布噪声优势的新型 JUBSS 方法。该方法包括几个步骤。首先,我们计算多个具有不同延迟的白化数据集的交叉三阶累积量。然后,我们将多个三阶累积量堆叠成四阶张量。接着,我们通过加权非线性最小二乘法,使用卡农多项式分解四阶张量,从而估算出混合矩阵。最后,根据源信号的独立性,我们提出了一种矩阵对角化方法来恢复源信号。实验证明,该方法能有效抑制高斯噪声的影响,在欠定、正定和过定情况下都有良好的表现,其性能优于各种常见方法。具体而言,对于信噪比为 20 dB 的 3 × 4 混合模型,平均相对误差为 - 14.48 dB,平均相似系数为 0.92,信噪比为 24.84 dB。
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引用次数: 0
Introducing Gain Constant Adjustment Facility in a Class of Single OA Circuits 在一类单 OA 电路中引入增益常数调整功能
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-07-04 DOI: 10.1007/s00034-024-02763-6
T. S. Rathore

A class of single operational amplifier (OA) circuits is modified so that gain can be adjusted by varying two resistors. The theory is demonstrated by first order and second order circuits. The OA can be replaced by other devices such as FTFN, CCII, CFA.

对一类单运算放大器(OA)电路进行了改进,使增益可通过改变两个电阻进行调节。一阶和二阶电路演示了这一理论。运算放大器可由 FTFN、CCII、CFA 等其他器件取代。
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引用次数: 0
Approximate Floating Point Precise Carry Prediction Adder for FIR Filter Applications 用于 FIR 滤波器应用的近似浮点精确进位预测加法器
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-29 DOI: 10.1007/s00034-024-02760-9
C. Sridhar, Aniruddha Kanhe

Approximate computing plays a crucial role in faster operation for large-scale data computation in error-resilient applications. An approximate adder is a digital circuit that performs addition with less accuracy to achieve faster processing time and lower hardware overhead. This approach is well suited for error-tolerant applications where minor errors in the output are acceptable. In this paper, an approximate carry prediction adder (ACPA) is proposed to add the mantissa in a 32-bit single precision floating point adder, termed as approximate floating point precise carry prediction adder (AFPCPA). The proposed ACPA utilizes a carry prediction circuit to generate a precise carry for the precise part leading to an increase in accuracy. The error characteristics and hardware utilization of AFPCPA and other existing approximate adder architectures are compared. The results show that the proposed AFPCPA vide, on average, 50.56%, 59.66%, 56.13%, and 81.40% reduction in standard deviation, mean absolute error, normalized mean error distance, and mean square error, respectively. In addition, the proposed AFPCPA shows on average, 18.97% and 6.68% lesser hardware utilization and delay, respectively compared to existing approximate adder architectures and accurate adder. Finally, a 3-tap FIR Filter is designed using the proposed AFPCPA and compared with existing architectures.

近似计算在提高抗错应用中大规模数据计算的运行速度方面发挥着至关重要的作用。近似加法器是一种数字电路,它以较低的精度执行加法运算,以实现更快的处理时间和更低的硬件开销。这种方法非常适合输出中的微小误差可以接受的容错应用。本文提出了一种近似进位预测加法器(ACPA),用于在 32 位单精度浮点加法器中添加尾数,称为近似浮点精确进位预测加法器(AFPCPA)。拟议的 ACPA 利用进位预测电路为精确部分生成精确进位,从而提高了精确度。对 AFPCPA 和其他现有近似加法器架构的误差特性和硬件利用率进行了比较。结果表明,拟议的 AFPCPA 在标准偏差、平均绝对误差、归一化平均误差距离和均方误差方面分别平均降低了 50.56%、59.66%、56.13% 和 81.40%。此外,与现有的近似加法器架构和精确加法器相比,所提出的 AFPCPA 在硬件利用率和延迟方面分别平均降低了 18.97% 和 6.68%。最后,利用提出的 AFPCPA 设计了一个 3 抽头 FIR 滤波器,并与现有架构进行了比较。
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引用次数: 0
A Two-Way Active Contour Model for Incomplete Contour Segmentation 用于不完整轮廓分割的双向主动轮廓模型
IF 2.3 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Pub Date : 2024-06-29 DOI: 10.1007/s00034-024-02754-7
Ming Deng, Zhiheng Zhou, Mingyue Zhang, Guoqi Liu, Delu Zeng

A two-way segmentation model is proposed in this article. The model is used to solve the problem that the objective contour can not be completely extracted from image due to occlusion between objects within similar image groups or image sequences. The proposed model first decomposes incomplete contours into sub-segments using local features identified by seed points set along each path. Then, locate the occluded part of the target object and reconstruct the target. Finally, a new vector field is generated based on the reconstructed object from the proposed model, followed by iterative evolution. The experimental results show that the proposed algorithm can better handle the problem of occlusion or misleading features of targets in composite images and medical images. Not only does it facilitate subsequent measurement and analysis, but it also preserves the original shape of the object during the segmentation process without prior information. It is worth noting that the accuracy of the proposed model is robust to our initialization strategy.

本文提出了一种双向分割模型。该模型用于解决由于相似图像组或图像序列中的物体之间存在遮挡而无法从图像中完整提取目标轮廓的问题。所提出的模型首先利用沿每条路径设置的种子点所识别的局部特征,将不完整的轮廓分解为子段。然后,定位目标对象的遮挡部分并重建目标。最后,根据拟议模型重建的目标生成新的矢量场,然后进行迭代演化。实验结果表明,所提出的算法能更好地处理合成图像和医学图像中目标的遮挡或误导特征问题。它不仅便于后续的测量和分析,而且在分割过程中还能在没有先验信息的情况下保留物体的原始形状。值得注意的是,所提模型的准确性对我们的初始化策略是稳健的。
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引用次数: 0
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Circuits, Systems and Signal Processing
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