Circuits, Systems and Signal Processing最新文献

This paper presents a two-step single-slope (TS-SS) analog-to-digital converter (ADC) for CMOS image sensors (CIS). The proposed TS-SS ADC divides the pixel signal into small and large signal regions using a precomparator. When quantizing large pixel signals, the TS-SS ADC enters accelerated mode, which leverages the differential topology of the ramp generator to speed up quantization. The accelerated mode reduces the row cycle, resulting in a 31.3% reduction at 320 MHz clock from 27.3 to 18.75 µs. The designed 12-bit TS-SS ADC was designed in a 110 nm 1P4M CMOS technology, and its linearity was verified by process corner post-simulation and Monte Carlo simulation.

Analog circuits composed by large number of nodes in a tightly coupled structure pose significant challenges due to their prohibitive CPU simulation time. This work describes a method to speed up the simulation of such circuits by means of the combination of space state formulation of circuit equations with explicit integration methods parallelized over a many-core processor such as a GPU. Although stability of explicit techniques require smaller integration steps compared to implicit methods, the proposed method employs a fast estimate of the maximum allowed step size to guarantee numerical stability, which yields a shorter simulation time for increasing complexity circuit architectures. Moreover, the proposed technique can be straightforward parallelized on a many core architecture. The proposed method is demonstrated with two examples using constant and variable coefficients respectively: an RLC interconnect and a MOS-C network to perform Gaussian filtering of medium resolution images. The results obtained have been compared to a parallel version of SPICE and show improvements up to two orders of magnitude for transient simulations depending of the circuit size.

The paper reports simple yet effective circuits for realizing XOR and XNOR logic operations with polarity, each employing a single current conveyor. The proposed polar logic circuits require four MOS switches and two resistors, besides a single CCII+ (second generation current conveyor), in each case. The new proposed circuits are simulated using 0.18 µm CMOS process parameters with a ± 1.8 V supply voltage and reference DC voltage of 1 V, thus enabling polar logic outputs. The polar output for logic 0 and 1 is in form of − 1 V and + 1 V respectively. The results included in support of the work are promising for future applications of the proposal in design of communication circuits. To facilitate better integration prospects, the proposed circuits are further simplified by removing one of the two used resistors and replacing CCII by CCCII (current controlled current conveyor). The simplified polar XOR gate is also verified through simulations. System design applications are expected to evolve from proposed work. The new proposed circuits are expected to significantly contribute to the advancement of circuit design.

This paper mainly investigates the problem of finite-time (H_{infty }) control for a class of uncertain Markovian jump nonlinear systems (MJNSs) with time-varying delay and generally uncertain transition rates. By constructing the appropriate Lyapunov–Krasovskii functional and free weighting matrices, a novel criterion on finite-time boundedness for the MJNSs with (H_{infty }) performance is derived. We use a special way to deal with the bilinear terms, the mode-dependent state feedback controller is designed to ensure the (H_{infty }) finite-time boundedness of the closed-loop system in the forms of strict linear matrix inequalities. Finally, numerical and practical examples are given to demonstrate the effectiveness of the proposed method.

Premature babies scream to make contact with their mothers or other people. Infants communicate via their screams in different ways based on the motivation behind their cries. A considerable amount of work and focus is required these days to preprocess, extract features, and classify audio signals. This research aims to propose a novel Elephant Herding Optimized Deep Convolutional Gated Recurrent Neural Network (EHO-DCGR net) for classifying cry signals from premature babies. Cry signals are first preprocessed to remove distortion caused by short sample times. MFCC (Mel-frequency cepstral coefficient), Power Normalized Cepstral Coefficients (PNCC), BFCC (Bark-frequency cepstral coefficient), and LPCC (Linear Prediction cepstral coefficient) are used to identify abnormal weeping through their prosodic aspects. The Elephant Herding optimization (EHO) algorithm is utilized for choosing the best features from the extracted set to form a fused feature matrix. These characteristics are then used to categorize premature baby cry sounds using the DCGR net. The proposed EHO-DCGR net effectiveness is measured by precision, specificity, recall, and F1-score, accuracy. According to experimental fallouts, the proposed EHO-DCGR net detects baby cry signals with an astounding 98.45% classification accuracy. From the experimental analysis, the EHO-DCGR Net increases the overall accuracy by 12.64%, 3.18%, 9.71% and 3.50% better than MFCC-SVM, DFFNN, SVM-RBF and SGDM respectively.

Speech enhancement, or SE, is a method of converting an input speech signal into a target signal with improved quality of voice and readability. To hear the voice, the skeleton bone vibrates ultra smooth thanks to bone conduction. The benefits of Bone-Conducted Microphone (BCM) speech include noise reduction and enhanced communication quality in high-noise environments. To acquire signals and precisely model word phonemes, BCM relies on the placement of bones. Certain computer techniques are expensive and ineffective in simulating signal phonemes. Three wavelet transform techniques are presented in this work: complex continuous wavelet transforms (CCWT), steady wavelet transforms (SWT), and discrete wavelet transforms (DWT). The right ramp, the voice box, and the mastoid were the three distinct bony locations for which the speech intelligibility of the BCM signal was evaluated. The listener evaluated the comprehension of the speech after obtaining the BCM signal for Tamil words. Speech quality is enhanced by the location of the larynx bone in comparison to alternative calculation methods.

To address the issues of poor anti-noise performance of second-order statistics and low estimation accuracy in previous joint underdetermined blind source separation (JUBSS) methods, we propose a novel JUBSS method based on the dependence between different data sets and the advantages of cross third-order cumulant in resisting distributed noise. The method involves several steps. Firstly, we calculate the cross third-order cumulant of multiple whitening data sets with different delays. Then, we stack several third-order cumulants into fourth-order tensors. Next, we decompose the fourth-order tensor using Canonical Polyadic through weight nonlinear least squares, which allows us to estimate the mixed matrix. Finally, depending on the independence of source signals, we propose a matrix diagonalization method to recover the source signal. Experiments demonstrate that the method effectively suppresses the influence of Gaussian noise and performs well in underdetermined, positive and overdetermined cases and produces a better performance than various common approaches. Specifically, for the 3 × 4 mixed model with signal-to-noise ratio of 20 dB, the average relative error is − 14.48 dB, the average similarity coefficient is 0.92 and the signal-to-interference ratio is 24.84 dB.

A class of single operational amplifier (OA) circuits is modified so that gain can be adjusted by varying two resistors. The theory is demonstrated by first order and second order circuits. The OA can be replaced by other devices such as FTFN, CCII, CFA.

Approximate computing plays a crucial role in faster operation for large-scale data computation in error-resilient applications. An approximate adder is a digital circuit that performs addition with less accuracy to achieve faster processing time and lower hardware overhead. This approach is well suited for error-tolerant applications where minor errors in the output are acceptable. In this paper, an approximate carry prediction adder (ACPA) is proposed to add the mantissa in a 32-bit single precision floating point adder, termed as approximate floating point precise carry prediction adder (AFPCPA). The proposed ACPA utilizes a carry prediction circuit to generate a precise carry for the precise part leading to an increase in accuracy. The error characteristics and hardware utilization of AFPCPA and other existing approximate adder architectures are compared. The results show that the proposed AFPCPA vide, on average, 50.56%, 59.66%, 56.13%, and 81.40% reduction in standard deviation, mean absolute error, normalized mean error distance, and mean square error, respectively. In addition, the proposed AFPCPA shows on average, 18.97% and 6.68% lesser hardware utilization and delay, respectively compared to existing approximate adder architectures and accurate adder. Finally, a 3-tap FIR Filter is designed using the proposed AFPCPA and compared with existing architectures.

The Hilbert transformation for generating the analytic signal or signal envelope is widely used in modern communication receivers, in radar and sonar systems. It introduces a (90^{circ }) phase shift of the input signal. Since the impulse response of the ideal Hilbert transformer is non-causal, it must be approximated by an FIR or IIR filter. This paper shows results of novel algorithms for designing broadband digital IIR Hilbert transformers and its implementation. The designs employ Galerkin or collocation techniques. The transfer function of the Hilbert transformer is a rational polynomial of low order and exhibits approximately linear phase. The filters match the (90^{circ }) phase shift requirement of Hilbert transformers almost perfectly and exhibit approximately constant group delay in the passband. The achieved image rejection ratio is typically larger than 50 dB. The quantization of the filter coefficients is realized by a Canonical Signed Digit (CSD) representation, reducing the hardware resources compared with two’s complement. The resulting filters are multiplier-less, which is crucial for high-speed signal processing and low power consumption. The design techniques and the CSD representation are realized in a MATLAB toolbox. The filters were moreover implemented in VHDL and SystemC. Additionally, a MATLAB tool for automatically generating a VHDL package containing the filter parameters has been implemented.