Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430943
T. Sugizaki, M. Nakamura, M. Yanagita, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, R. Yamamoto, S. Kanda, K. Yagami, T. Oda
We fabricated alternative SRAM cells based on a thyristor using SOI and bulk Si wafers, and then compared their performance. A selective epitaxy technique was applied to form anode regions (SEA) for both types. These devices performed extremely well, with high-speed read/write, high lon/Ioff current ratio (>108), and low stand-by current (< 0.5 nA/cell). Write "1" (turn-on) and read performance were comparable for both bulk and SOI (< 100 ps). However, for write "0" (turn-off), the bulk type had much faster speed and lower voltage than the SOI type. In RAM operations, performance of the SOI type would be dominated by write "0" operation speed. These results suggest that the bulk type is more suitable than the SOI type for RAM devices that operate at highspeed.
{"title":"Advantages of bulk over SOI in performance of thyristor-based SRAM cell with selective epitaxy anode","authors":"T. Sugizaki, M. Nakamura, M. Yanagita, M. Shinohara, T. Ikuta, T. Ohchi, K. Kugimiya, R. Yamamoto, S. Kanda, K. Yagami, T. Oda","doi":"10.1109/ESSDERC.2007.4430943","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430943","url":null,"abstract":"We fabricated alternative SRAM cells based on a thyristor using SOI and bulk Si wafers, and then compared their performance. A selective epitaxy technique was applied to form anode regions (SEA) for both types. These devices performed extremely well, with high-speed read/write, high lon/Ioff current ratio (>108), and low stand-by current (< 0.5 nA/cell). Write \"1\" (turn-on) and read performance were comparable for both bulk and SOI (< 100 ps). However, for write \"0\" (turn-off), the bulk type had much faster speed and lower voltage than the SOI type. In RAM operations, performance of the SOI type would be dominated by write \"0\" operation speed. These results suggest that the bulk type is more suitable than the SOI type for RAM devices that operate at highspeed.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430904
W. Schoenmaker, P. Meuris, W. Schilders, D. Ioan
This paper deals with the modeling of the injection of electromagnetic fields into the active devices/circuits originating from integrated passive devices. It is shown that the impact of induced electromagnetic fields can be included as modified terminal conditions of the nearby devices.
{"title":"Modeling of passive-active device interactions","authors":"W. Schoenmaker, P. Meuris, W. Schilders, D. Ioan","doi":"10.1109/ESSDERC.2007.4430904","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430904","url":null,"abstract":"This paper deals with the modeling of the injection of electromagnetic fields into the active devices/circuits originating from integrated passive devices. It is shown that the impact of induced electromagnetic fields can be included as modified terminal conditions of the nearby devices.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126421230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430942
J. Hållstedt, B. Malm, P. Hellstrom, M. Ostling, M. Oehme, J. Werner, K. Lyutovich, E. Kasper
We present a comprehensive study of biaxially strained (up to ~3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage for the relaxed SiGe substrates compared to conventional implantation. The source to drain leakage in 80 nm devices was effectively reduced by increment of channel doping and rotation of the channel direction.
{"title":"Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates","authors":"J. Hållstedt, B. Malm, P. Hellstrom, M. Ostling, M. Oehme, J. Werner, K. Lyutovich, E. Kasper","doi":"10.1109/ESSDERC.2007.4430942","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430942","url":null,"abstract":"We present a comprehensive study of biaxially strained (up to ~3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage for the relaxed SiGe substrates compared to conventional implantation. The source to drain leakage in 80 nm devices was effectively reduced by increment of channel doping and rotation of the channel direction.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126977453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430971
S. Jun, C. Baik, S.I. Kim, J.M. Kim, H. Jin Kim, X.M.H. Huang, S. Hone
Effects of electrothermal tuning mechanisms for nanoelectromechnical resonators are demonstrated. Voltages induced by oscillation of Al/SiC nanoresonators in a moderate magnetic filed are measured using a room-temperature tabletop setup in moderate vacuum. The dynamic range as well as the resonance frequency of the resonator can be reversibly controlled by electrothermal tuning using DC voltage. This paper presents experimental results on the resonance frequency, Q factor and dynamic range during the electrothermal tuning. As the input DC power increases, Q factor decreases due to the decrease in the resonance frequency, and SNR decreases due to the reduced amplitude or increased noise.
{"title":"Electrothermal tuning and SNR of nanoelectromechanical resonators","authors":"S. Jun, C. Baik, S.I. Kim, J.M. Kim, H. Jin Kim, X.M.H. Huang, S. Hone","doi":"10.1109/ESSDERC.2007.4430971","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430971","url":null,"abstract":"Effects of electrothermal tuning mechanisms for nanoelectromechnical resonators are demonstrated. Voltages induced by oscillation of Al/SiC nanoresonators in a moderate magnetic filed are measured using a room-temperature tabletop setup in moderate vacuum. The dynamic range as well as the resonance frequency of the resonator can be reversibly controlled by electrothermal tuning using DC voltage. This paper presents experimental results on the resonance frequency, Q factor and dynamic range during the electrothermal tuning. As the input DC power increases, Q factor decreases due to the decrease in the resonance frequency, and SNR decreases due to the reduced amplitude or increased noise.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430895
Tibor Grasser, B. Kaczer
The analysis of negative bias temperature instability (NBTI) conventionally focuses on the stress phase where features like the power-law exponent, the temperature-dependence, and saturation of the observed threshold voltage shift have been extensively studied. As soon as the stress is removed, however, relaxation sets in, restoring at least some of the degradation. Although some studies on the relaxation phase have been presented, few authors have acknowledged the importance of the relaxation phase as a means of deepening our understanding of NBTI. We present a detailed analysis of NBTI relaxation, show that even at lower stressing voltages a permanent/slowly relaxing component is present, and demonstrate how this initially less dominant component might eventually determine the device lifetime.
{"title":"Negative bias temperature instability: Recoverable versus permanent degradation","authors":"Tibor Grasser, B. Kaczer","doi":"10.1109/ESSDERC.2007.4430895","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430895","url":null,"abstract":"The analysis of negative bias temperature instability (NBTI) conventionally focuses on the stress phase where features like the power-law exponent, the temperature-dependence, and saturation of the observed threshold voltage shift have been extensively studied. As soon as the stress is removed, however, relaxation sets in, restoring at least some of the degradation. Although some studies on the relaxation phase have been presented, few authors have acknowledged the importance of the relaxation phase as a means of deepening our understanding of NBTI. We present a detailed analysis of NBTI relaxation, show that even at lower stressing voltages a permanent/slowly relaxing component is present, and demonstrate how this initially less dominant component might eventually determine the device lifetime.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125723983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430960
A. Pham, C. Jungemann, B. Meinerzhagen
The hole inversion layer mobility of in-plane uniaxially strained Si is modeled by a microscopic approach. For an arbitrary crystallographic surface orientation the two dimensional hole gas subband structure is calculated by solving the 6 times 6 koarr ldr poarr Schrodinger equation self-consistently with the electrostatic potential. Three important scattering mechanisms are included: optical phonon scattering, acoustic phonon scattering and surface roughness scattering. The model parameters are calibrated by matching the measured low-field mobility of relaxed Si on (001) Si wafers. The calibrated model reproduces available channel mobility measurements for unstrained and uniaxially strained Si on (001), (111) and (110) substrates.
{"title":"Modeling of hole inversion layer mobility in unstrained and uniaxially strained Si on arbitrarily oriented substrates","authors":"A. Pham, C. Jungemann, B. Meinerzhagen","doi":"10.1109/ESSDERC.2007.4430960","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430960","url":null,"abstract":"The hole inversion layer mobility of in-plane uniaxially strained Si is modeled by a microscopic approach. For an arbitrary crystallographic surface orientation the two dimensional hole gas subband structure is calculated by solving the 6 times 6 koarr ldr poarr Schrodinger equation self-consistently with the electrostatic potential. Three important scattering mechanisms are included: optical phonon scattering, acoustic phonon scattering and surface roughness scattering. The model parameters are calibrated by matching the measured low-field mobility of relaxed Si on (001) Si wafers. The calibrated model reproduces available channel mobility measurements for unstrained and uniaxially strained Si on (001), (111) and (110) substrates.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126910503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430901
T. Liow, K. Tan, R.T.-P. Lee, M. Zhu, K. Hoe, G. Samudra, N. Balasubramanian, Y. Yeo
By removing the SiN gate spacers in n-channel FinFETs with Silicon-Carbon (SiC) Source and Drain (S/D) stressors, the mechanical stress equilibrium is perturbed. Higher tensile channel stress can be achieved, after the transistor structure attains mechanical equilibrium once again after spacer removal. This stress increase results in up to ~15 % further IDsat enhancement over strained SiC S/D FinFETs with spacers intact. Peak Gm is enhanced by ~33 %.
{"title":"Strain enhancement in spacerless N-channel FinFETs with silicon-carbon source and drain stressors","authors":"T. Liow, K. Tan, R.T.-P. Lee, M. Zhu, K. Hoe, G. Samudra, N. Balasubramanian, Y. Yeo","doi":"10.1109/ESSDERC.2007.4430901","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430901","url":null,"abstract":"By removing the SiN gate spacers in n-channel FinFETs with Silicon-Carbon (SiC) Source and Drain (S/D) stressors, the mechanical stress equilibrium is perturbed. Higher tensile channel stress can be achieved, after the transistor structure attains mechanical equilibrium once again after spacer removal. This stress increase results in up to ~15 % further IDsat enhancement over strained SiC S/D FinFETs with spacers intact. Peak Gm is enhanced by ~33 %.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"107 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131372229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430883
K. Itoh, M. Horiguchi, M. Yamaoka
The low-voltage limitations of memory-rich nano-scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip-flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger VT variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as well as by using repair techniques. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: high-VDD bulk CMOS LSIs for low-cost low-standby-current applications and low-VDD FD-SOI LSIs for low-power applications.
{"title":"Low-voltage limitations of memory-rich nano-scale CMOS LSIs","authors":"K. Itoh, M. Horiguchi, M. Yamaoka","doi":"10.1109/ESSDERC.2007.4430883","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430883","url":null,"abstract":"The low-voltage limitations of memory-rich nano-scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip-flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger VT variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as well as by using repair techniques. Consequently, two possible LSIs are predicted to coexist in the deep-sub-100-nm generation: high-VDD bulk CMOS LSIs for low-cost low-standby-current applications and low-VDD FD-SOI LSIs for low-power applications.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122371628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430917
A. Lacaita, D. Ielmini
From the stage of concept-level alternative to Flash memories, the phase-change memory (PCM) is rapidly gaining the status of reference technology for high performance, high endurance next generation non volatile applications. To sustain the development of new and scaled PCM technologies, a comprehensive understanding and modelling of the cell at the material, cell and large-array levels are required. This paper will address the most significant achievements in the electrothermal modelling of PCM single cell. After reviewing the transport modeling in the amorphous and crystalline phases of the chalcogenide material, we focus on the application modeling of the cell, discussing programming current minimization by geometry optimization, trade-off between programming current and readout resistance and the program disturb issue. Scaling of the PCM is extensively addressed, comparing isotropic and non isotropic scaling and the respective impact on cell reliability. The open issues for PCM physical modeling are finally pointed out.
{"title":"Status and challenges of PCM modeling","authors":"A. Lacaita, D. Ielmini","doi":"10.1109/ESSDERC.2007.4430917","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430917","url":null,"abstract":"From the stage of concept-level alternative to Flash memories, the phase-change memory (PCM) is rapidly gaining the status of reference technology for high performance, high endurance next generation non volatile applications. To sustain the development of new and scaled PCM technologies, a comprehensive understanding and modelling of the cell at the material, cell and large-array levels are required. This paper will address the most significant achievements in the electrothermal modelling of PCM single cell. After reviewing the transport modeling in the amorphous and crystalline phases of the chalcogenide material, we focus on the application modeling of the cell, discussing programming current minimization by geometry optimization, trade-off between programming current and readout resistance and the program disturb issue. Scaling of the PCM is extensively addressed, comparing isotropic and non isotropic scaling and the respective impact on cell reliability. The open issues for PCM physical modeling are finally pointed out.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123850289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430927
Yong Soo Kim, K. Lim, M. Sung, Soohyeon Kim, Hong-Seon Yang, Heung-Jae Cho, S. Jang, Jae-Geun Oh, Kwangok Kim, Y.-K. Jung, T. Jung, C. Kim, Doek-Won Lee, Won Kim, Young-Hoon Kim, K. Choi, T. Oh, Y. Hwang, S. Pyi, J. Ku, Jin-Woong Kim
We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B2H6-based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.
{"title":"Low resistive tungsten dual polymetal gate process for high speed and high density memory devices","authors":"Yong Soo Kim, K. Lim, M. Sung, Soohyeon Kim, Hong-Seon Yang, Heung-Jae Cho, S. Jang, Jae-Geun Oh, Kwangok Kim, Y.-K. Jung, T. Jung, C. Kim, Doek-Won Lee, Won Kim, Young-Hoon Kim, K. Choi, T. Oh, Y. Hwang, S. Pyi, J. Ku, Jin-Woong Kim","doi":"10.1109/ESSDERC.2007.4430927","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430927","url":null,"abstract":"We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process with B2H6-based nucleation layer. The low resistive CVD-W (LRW) polymetal gate process not only reveals good gate oxide reliability comparable to PVD-W process, but also highly improved transistor performances such as signal delay characteristics.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123906374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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