{"title":"Lateral HV-MOS transistors (50V) for integration in a 0.18μm CMOS-process","authors":"M. Gross, M. Stoisiek, T. Uhlig, C. Ellmers, F. Furnhammer","doi":"10.1109/ESSDERC.2007.4430908","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430908","url":null,"abstract":"<sub>DS(on)</sub> *A = 36.2 mQmm<sup>2</sup> at a breakdown voltage of 60 V. The integration of the devices in the CMOS base process uses five additional photo masks.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127357336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430919
C. Liaw, M. Kund, D. Schmitt-Landsiedel, I. Ruge
CBRAM is investigated as a NVM memory with respect to retention characteristics and multilevel capability. The CB-junction is characterised by photocurrent and photoluminescence. Measurement results showing the long-term data retention of the CBRAM technology are presented. The stability of four levels corresponds to the capability to store two bits. Scalability is shown with suitable switching characteristics and area-independent on-resistance down to sub 40 nm junction size. Operating conditions and circuits are introduced for CBRAM writing and voltage sensing.
{"title":"The conductive bridging random access memory (CBRAM): A non-volatile multi-level memory technology","authors":"C. Liaw, M. Kund, D. Schmitt-Landsiedel, I. Ruge","doi":"10.1109/ESSDERC.2007.4430919","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430919","url":null,"abstract":"CBRAM is investigated as a NVM memory with respect to retention characteristics and multilevel capability. The CB-junction is characterised by photocurrent and photoluminescence. Measurement results showing the long-term data retention of the CBRAM technology are presented. The stability of four levels corresponds to the capability to store two bits. Scalability is shown with suitable switching characteristics and area-independent on-resistance down to sub 40 nm junction size. Operating conditions and circuits are introduced for CBRAM writing and voltage sensing.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117087100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430959
V. Sverdlov, E. Ungersboeck, H. Kosina, S. Selberherr
We present an efficient two-band kldrp theory which accurately describes the six lowest conduction band valleys in silicon. By comparing the model with full band pseudo-potential calculations we demonstrate that the model captures both the nonparabolicity effects and the stress-induced band structure modification for general stress conditions. It reproduces the stress dependence of the effective masses and the nonparabolicity parameter. Analytical expressions for the valley shifts and the transversal and longitudinal effective mass modifications induced by uniaxial [110] stress are obtained and analyzed. The low-field mobility enhancement in the direction of tensile [110] stress in {001} SOI FETs with arbitrary small body thickness is due to a modification of the conductivity mass and is shown to be partly hampered by an increase in nonparabolicity at high stress value.
{"title":"Effects of shear strain on the conduction band in silicon: An efficient two-band k·p theory","authors":"V. Sverdlov, E. Ungersboeck, H. Kosina, S. Selberherr","doi":"10.1109/ESSDERC.2007.4430959","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430959","url":null,"abstract":"We present an efficient two-band kldrp theory which accurately describes the six lowest conduction band valleys in silicon. By comparing the model with full band pseudo-potential calculations we demonstrate that the model captures both the nonparabolicity effects and the stress-induced band structure modification for general stress conditions. It reproduces the stress dependence of the effective masses and the nonparabolicity parameter. Analytical expressions for the valley shifts and the transversal and longitudinal effective mass modifications induced by uniaxial [110] stress are obtained and analyzed. The low-field mobility enhancement in the direction of tensile [110] stress in {001} SOI FETs with arbitrary small body thickness is due to a modification of the conductivity mass and is shown to be partly hampered by an increase in nonparabolicity at high stress value.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128038005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430947
J. Singer, F. Salvetti, V. Kaeppelin, F. Wacquant, N. Cagnat, M. Jaraíz, P. Castrillo, E. Rubio, A. Poncet
This study is aimed to understand the mechanisms leading to different device behaviors while switching from one type of implanter, which scans a batch of wafers with a spot ion beam, to another one, which scans a single wafer with a ribbon ion beam. Thanks to atomistic simulations, we bring to the fore that the implant dose rate is responsible for the observed mismatch. Increasing the dose rate reduces the amount of interstitials present beyond the amorphous layer. During subsequent annealing, these interstitials first accelerate boron clusters dissolution at projected range, then agglomerate themselves into stable dislocation loops. The latter will in turn deactivate the boron in source and drain region, modifying the electrical characteristics of the device.
{"title":"Atomistic modeling and physical comprehension of the effects of implant dose rate on boron activation in pMOSFET S/D","authors":"J. Singer, F. Salvetti, V. Kaeppelin, F. Wacquant, N. Cagnat, M. Jaraíz, P. Castrillo, E. Rubio, A. Poncet","doi":"10.1109/ESSDERC.2007.4430947","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430947","url":null,"abstract":"This study is aimed to understand the mechanisms leading to different device behaviors while switching from one type of implanter, which scans a batch of wafers with a spot ion beam, to another one, which scans a single wafer with a ribbon ion beam. Thanks to atomistic simulations, we bring to the fore that the implant dose rate is responsible for the observed mismatch. Increasing the dose rate reduces the amount of interstitials present beyond the amorphous layer. During subsequent annealing, these interstitials first accelerate boron clusters dissolution at projected range, then agglomerate themselves into stable dislocation loops. The latter will in turn deactivate the boron in source and drain region, modifying the electrical characteristics of the device.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124518838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430932
W. von Emden, W. Krautschneider, G. Tempel, R. Hagenbeck, M. F. Beug
The functionality of nonvolatile memories with lateral multi-bit charge storage capabilities like NROM/TwinFlash is critically related to spatial separation of the injected charge quantities to discriminate different logical states. In this paper we develop an adapted methodology to extract local charge densities based on the constant field charge pumping method. Our method overcomes the problem of non self-consistency of conventional constant field charge pumping by determination of the spatial coordinate after every injection step. The method is demonstrated to directly extract the electron/hole mismatch after program and erase injection.
{"title":"A modified constant field charge pumping method for sensitive profiling of near-junction charges","authors":"W. von Emden, W. Krautschneider, G. Tempel, R. Hagenbeck, M. F. Beug","doi":"10.1109/ESSDERC.2007.4430932","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430932","url":null,"abstract":"The functionality of nonvolatile memories with lateral multi-bit charge storage capabilities like NROM/TwinFlash is critically related to spatial separation of the injected charge quantities to discriminate different logical states. In this paper we develop an adapted methodology to extract local charge densities based on the constant field charge pumping method. Our method overcomes the problem of non self-consistency of conventional constant field charge pumping by determination of the spatial coordinate after every injection step. The method is demonstrated to directly extract the electron/hole mismatch after program and erase injection.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133939179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430953
L. Pancheri, D. Stoppa
The implementation of single-photon avalanche diode detectors (SPAD) in a standard high voltage 0.7-mum CMOS technology is presented. Two different device structures, combined with integrated quenching circuits, have been fabricated and successfully tested. A novel biasing scheme is proposed allowing the reduction of afterpulsing effect and the decrease of minimum device-to-device distance. Good noise performance is obtained for the 100 mum2 active area device where over 50% of the population has a dark count rate below lOOcps and afterpulsing lower than 0.3% with a 4-V excess bias and a 32-ns dead time. The peak photon detection probability is about 30%, while the overall system, upper limit, for the time resolution is 144 ps.
介绍了在标准高压0.7 μ m CMOS技术上实现单光子雪崩二极管探测器(SPAD)的方法。两种不同的器件结构，结合集成淬火电路，已经制造并成功测试。提出了一种新的偏置方案，可以减小后脉冲效应和器件间最小距离。在100 mum2有源器件中，超过50%的器件具有低于loopps的暗计数率和低于0.3%的后脉冲，具有4 v的过量偏置和32ns的死区时间，具有良好的噪声性能。峰值光子检测概率约为30%，而整个系统的时间分辨率上限为144ps。
{"title":"Low-Noise CMOS single-photon avalanche diodes with 32 ns dead time","authors":"L. Pancheri, D. Stoppa","doi":"10.1109/ESSDERC.2007.4430953","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430953","url":null,"abstract":"The implementation of single-photon avalanche diode detectors (SPAD) in a standard high voltage 0.7-mum CMOS technology is presented. Two different device structures, combined with integrated quenching circuits, have been fabricated and successfully tested. A novel biasing scheme is proposed allowing the reduction of afterpulsing effect and the decrease of minimum device-to-device distance. Good noise performance is obtained for the 100 mum2 active area device where over 50% of the population has a dark count rate below lOOcps and afterpulsing lower than 0.3% with a 4-V excess bias and a 32-ns dead time. The peak photon detection probability is about 30%, while the overall system, upper limit, for the time resolution is 144 ps.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129482594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430957
F. Gámiz, L. Donetti, N. Rodriguez
We simulated the behavior of electron mobility and the effect of volume inversion in FinFETs with different surface (hkl) orientations and channel directions, using a Monte Carlo simulator. For each surface orientation, different channel directions were also considered. In the case of the (110) surface, a strong anisotropy of electron mobility with channel direction was seen: when the channel was in the (110)/<001> direction, electron mobility was 50% higher than in (110)/<1-10>, and was similar to the mobility for a (100)/<001> direction. This anisotropic behavior with channel orientation was not observed in the (100)-or (111)-surface orientations. The study with silicon thickness also revealed some interesting consequences of the volume inversion effect.
{"title":"Anisotropy of electron mobility in arbitrarily oriented FinFETs","authors":"F. Gámiz, L. Donetti, N. Rodriguez","doi":"10.1109/ESSDERC.2007.4430957","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430957","url":null,"abstract":"We simulated the behavior of electron mobility and the effect of volume inversion in FinFETs with different surface (hkl) orientations and channel <hkl> directions, using a Monte Carlo simulator. For each surface orientation, different channel directions were also considered. In the case of the (110) surface, a strong anisotropy of electron mobility with channel direction was seen: when the channel was in the (110)/<001> direction, electron mobility was 50% higher than in (110)/<1-10>, and was similar to the mobility for a (100)/<001> direction. This anisotropic behavior with channel orientation was not observed in the (100)-or (111)-surface orientations. The study with silicon thickness also revealed some interesting consequences of the volume inversion effect.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"69 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113961563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430931
M. Charbonnier, J. Mitard, C. Leroux, G. Ghibaudo, V. Cosnier, P. Besson, F. Martin, G. Reimbold
In this paper, we extract the gate work function of metal/High-K stacks (WFM) with an internal photoemission (IPE) based method and a C(V) characterization method. We attempt to apply both of them on the same specially designed samples. We show that it leads to a better reliability of WFM and highlights new phenomena.
{"title":"Reliable extraction of metal gate work function by combining two electrical characterization methods","authors":"M. Charbonnier, J. Mitard, C. Leroux, G. Ghibaudo, V. Cosnier, P. Besson, F. Martin, G. Reimbold","doi":"10.1109/ESSDERC.2007.4430931","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430931","url":null,"abstract":"In this paper, we extract the gate work function of metal/High-K stacks (WFM) with an internal photoemission (IPE) based method and a C(V) characterization method. We attempt to apply both of them on the same specially designed samples. We show that it leads to a better reliability of WFM and highlights new phenomena.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123692540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430921
D. Pulfrey
The emerging body of literature on the high-frequency performance of carbon nanotube field-effect transistors (CNFETs) is critically reviewed. The focus is on the figure-of-merit fT, the common-source, short-circuit current gain. The intentions are: to direct attention to the most relevant measured data; to compare this data with record values for other transistors, and with predicted results for CNFETs; to explain the large spread in predicted data; to offer a prognosis for high-frequency CNFETs.
{"title":"Critique of high-frequency performance of carbon nanotube FETs","authors":"D. Pulfrey","doi":"10.1109/ESSDERC.2007.4430921","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430921","url":null,"abstract":"The emerging body of literature on the high-frequency performance of carbon nanotube field-effect transistors (CNFETs) is critically reviewed. The focus is on the figure-of-merit fT, the common-source, short-circuit current gain. The intentions are: to direct attention to the most relevant measured data; to compare this data with record values for other transistors, and with predicted results for CNFETs; to explain the large spread in predicted data; to offer a prognosis for high-frequency CNFETs.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430934
K. Moselund, V. Pott, D. Bouvet, A. Ionescu
In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Omega-MOSFET). The Omega-MOSFETs are fabricated on low-doped (8times1014 cm-3) bulk silicon by bulk silicon isotropic etching and sacrificial oxidation. A specific abrupt impact ionization and hysteresis of ID(VDS) are observed at high drain voltage (VDS>11 V) on transistors that have short channel effects (L=0.9-10 um). This is explained by the accumulation of a hole pocket under the gate due to the formation of a saddle point region. An outstanding feature is that this effect can be exploited to abruptly switch from low to high current (2 decades of current) states of ID(VGS) characteristics with ultra-abrupt slopes of 5 to 10 mV/dec. Moreover, the hysteresis window DeltaVGS~500 mV is suitable for DRAM memory. Dynamic switching characteristics and a retention time of up to tens of seconds are originally demonstrated. The proposed Omega-MOSFET stands as a very promising alternative to I-MOS devices, being more scalable and integrable on a standard (low cost) bulk-Si Multi-Gate FET platform. Its experimental performances are promising for both small-slope switches and dynamic RAM memories.
{"title":"Abrupt current switching due to impact ionization effects in Ω-MOSFET on low doped bulk silicon","authors":"K. Moselund, V. Pott, D. Bouvet, A. Ionescu","doi":"10.1109/ESSDERC.2007.4430934","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430934","url":null,"abstract":"In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Omega-MOSFET). The Omega-MOSFETs are fabricated on low-doped (8times1014 cm-3) bulk silicon by bulk silicon isotropic etching and sacrificial oxidation. A specific abrupt impact ionization and hysteresis of ID(VDS) are observed at high drain voltage (VDS>11 V) on transistors that have short channel effects (L=0.9-10 um). This is explained by the accumulation of a hole pocket under the gate due to the formation of a saddle point region. An outstanding feature is that this effect can be exploited to abruptly switch from low to high current (2 decades of current) states of ID(VGS) characteristics with ultra-abrupt slopes of 5 to 10 mV/dec. Moreover, the hysteresis window DeltaVGS~500 mV is suitable for DRAM memory. Dynamic switching characteristics and a retention time of up to tens of seconds are originally demonstrated. The proposed Omega-MOSFET stands as a very promising alternative to I-MOS devices, being more scalable and integrable on a standard (low cost) bulk-Si Multi-Gate FET platform. Its experimental performances are promising for both small-slope switches and dynamic RAM memories.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121591069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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