Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430970
N. D. Badila-Ciressan, M. Mazza, D. Grogg, A. Ionescu
The design, fabrication and experimental investigation of 21 MHz MEM bulk lateral resonators (BLR) on 1.5 mum silicon-on-insulator (SOI) fragmented membranes with 100 nm air-gaps are reported. Quality factors as high as 33'000 are measured under vacuum at room temperature, with 20 V DC bias and low AC-power. The influence of temperature on the resonance frequency and quality factor is studied and discussed from 80 K and 380 K. A very high quality factor of 182'000 and a motional resistance of 165 kOmega, are reported at 80 K. The paper shows that high-quality factor MEM resonator can be integrated on partially-depleted thin SOI, which demonstrates the possibility of making full-integrated hybrid MEM-CMOS integrated circuits for future communication applications.
{"title":"Fragmented membrane MEM bulk lateral resonators with nano-gaps on 1.5μm SOI","authors":"N. D. Badila-Ciressan, M. Mazza, D. Grogg, A. Ionescu","doi":"10.1109/ESSDERC.2007.4430970","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430970","url":null,"abstract":"The design, fabrication and experimental investigation of 21 MHz MEM bulk lateral resonators (BLR) on 1.5 mum silicon-on-insulator (SOI) fragmented membranes with 100 nm air-gaps are reported. Quality factors as high as 33'000 are measured under vacuum at room temperature, with 20 V DC bias and low AC-power. The influence of temperature on the resonance frequency and quality factor is studied and discussed from 80 K and 380 K. A very high quality factor of 182'000 and a motional resistance of 165 kOmega, are reported at 80 K. The paper shows that high-quality factor MEM resonator can be integrated on partially-depleted thin SOI, which demonstrates the possibility of making full-integrated hybrid MEM-CMOS integrated circuits for future communication applications.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128926833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430910
C. Leyris, S. Pilorget, M. Marin, M. Minondo, H. Jaouen
In small area MOSFET devices widely used in analog and RF circuit design, low frequency noise behavior is increasingly dominated by Random Telegraph Signal noise. For analog circuit designers, awareness of these single electron noise phenomena is crucial. If optimal circuits are to be designed these effects can aid in low noise circuit design if used properly, while they may be detrimental to performance if inadvertently applied. This paper presents the investigation of Random Telegraph Signal (RTS) implementation in circuit simulator. A model based on Shockley-Read-Hall statistics to explain the behavior is presented. This work takes into account the impact of noise power spectral density (PSD) dispersion. The distinctiveness of the noise variations is discussed in detail and the proposed mechanisms behind the phenomena are viewed in light of the collected data. Results are compared with experimental data.
{"title":"Random telegraph signal noise SPICE modeling for circuit simulators","authors":"C. Leyris, S. Pilorget, M. Marin, M. Minondo, H. Jaouen","doi":"10.1109/ESSDERC.2007.4430910","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430910","url":null,"abstract":"In small area MOSFET devices widely used in analog and RF circuit design, low frequency noise behavior is increasingly dominated by Random Telegraph Signal noise. For analog circuit designers, awareness of these single electron noise phenomena is crucial. If optimal circuits are to be designed these effects can aid in low noise circuit design if used properly, while they may be detrimental to performance if inadvertently applied. This paper presents the investigation of Random Telegraph Signal (RTS) implementation in circuit simulator. A model based on Shockley-Read-Hall statistics to explain the behavior is presented. This work takes into account the impact of noise power spectral density (PSD) dispersion. The distinctiveness of the noise variations is discussed in detail and the proposed mechanisms behind the phenomena are viewed in light of the collected data. Results are compared with experimental data.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124368331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430978
B. de Jaeger, G. Nicholas, D.P. Borneo, G. Eneman, M. Meuris, M. Heyns
Ge pMOSFETs with gate lengths down to 125 nm are fabricated in a Si-like process flow. The addition of a halo implant reduces VT roll-off from 207 mV to 36 mV, and DIBL from 230 mV/V to 54 mV/V. Ion of 770 muA/mum is attained for Ioff of 8.8 nA/mum at VDD = -1.5 V, when evaluating from the source. Benchmarking shows these Ge pMOSFETs have the potential to outperform their (strained) Si counterparts. Measurements at 100degC suggest that Ge will continue to be competitive at realistic logic operating temperatures.
{"title":"High Performance High-k/Metal Gate Ge pMOSFETs with gate lengths down to 125 nm and halo implant","authors":"B. de Jaeger, G. Nicholas, D.P. Borneo, G. Eneman, M. Meuris, M. Heyns","doi":"10.1109/ESSDERC.2007.4430978","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430978","url":null,"abstract":"Ge pMOSFETs with gate lengths down to 125 nm are fabricated in a Si-like process flow. The addition of a halo implant reduces VT roll-off from 207 mV to 36 mV, and DIBL from 230 mV/V to 54 mV/V. Ion of 770 muA/mum is attained for Ioff of 8.8 nA/mum at VDD = -1.5 V, when evaluating from the source. Benchmarking shows these Ge pMOSFETs have the potential to outperform their (strained) Si counterparts. Measurements at 100degC suggest that Ge will continue to be competitive at realistic logic operating temperatures.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121934334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430937
K. Boucart, A. Ionescu
This work reports on the physical definition and extraction of threshold voltage in tunnel FETs based on numerical simulation data. It is shown that the tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, VTG, and one in terms of drain voltage, VTD. These threshold voltages can be physically defined based on the saturation of the barrier width narrowing with respect to VG or VD. The extractions of VTG and VTD are performed based on the transconductance change method in the double gate tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these threshold voltages, current, conductance characteristics, gm/ID and gm/gds of the tunnel FET is investigated for the first time.
{"title":"Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design","authors":"K. Boucart, A. Ionescu","doi":"10.1109/ESSDERC.2007.4430937","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430937","url":null,"abstract":"This work reports on the physical definition and extraction of threshold voltage in tunnel FETs based on numerical simulation data. It is shown that the tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, V<sub>TG</sub>, and one in terms of drain voltage, V<sub>TD</sub>. These threshold voltages can be physically defined based on the saturation of the barrier width narrowing with respect to V<sub>G</sub> or V<sub>D</sub>. The extractions of V<sub>TG</sub> and V<sub>TD</sub> are performed based on the transconductance change method in the double gate tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these threshold voltages, current, conductance characteristics, g<sub>m</sub>/I<sub>D</sub> and g<sub>m</sub>/g<sub>ds</sub> of the tunnel FET is investigated for the first time.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131340643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430925
T. Maebashi, N. Nakamura, S. Nakayama, N. Miyakawa
This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent.
{"title":"A new fabrication method for multi-layer stacked devices using wafer-to-wafer stacked technology based on 8-inch wafers","authors":"T. Maebashi, N. Nakamura, S. Nakayama, N. Miyakawa","doi":"10.1109/ESSDERC.2007.4430925","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430925","url":null,"abstract":"This paper presents 3-layer stacked devices in which each wafer is stacked one after another, using 8.18 mum CMOS technology based on 8-inch wafers. Electrical conductivity between each layer was almost 100% and interconnection resistance was less than 0.7Omega between the upper and lower wafers with a Buried Interconnection (BI) and a micro-bump. The prototype devices showed sophisticated functionality by testing, and the ratio of functional devices in the stacked wafer reached more than 60 percent.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131840856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430929
C. Steen, A. Martinez-Limia, P. Pichler, H. Ryssel, Lirong Pei, G. Duscher, W. Windl
The pile up of As at the SiO2/Si interface was investigated by grazing incidence X-ray fluorescence spectroscopy in combination with removal of silicon layers by etching with thicknesses on the order of a nanometer. In order to determine the thickness of the silicon layers removed at the interface, atomic force microscope measurements were performed at trench structures. With this method, it is possible to determine the thickness of the piled-up region in the silicon. In addition, it is possible to clearly distinguish between the segregated atoms and the As atoms in the bulk over a large range of implantation doses from 3middot1012 cm-2 to 1middot10-16 cm-2. The samples were annealed at 900degC and 1000degC, respectively, for times sufficiently long to ensure that the segregation reflects an equilibrium effect. With this approach, the pile-up of As was measured with new precision.
{"title":"Characterization of the pile-up of As at the SiO2/Si interface","authors":"C. Steen, A. Martinez-Limia, P. Pichler, H. Ryssel, Lirong Pei, G. Duscher, W. Windl","doi":"10.1109/ESSDERC.2007.4430929","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430929","url":null,"abstract":"The pile up of As at the SiO2/Si interface was investigated by grazing incidence X-ray fluorescence spectroscopy in combination with removal of silicon layers by etching with thicknesses on the order of a nanometer. In order to determine the thickness of the silicon layers removed at the interface, atomic force microscope measurements were performed at trench structures. With this method, it is possible to determine the thickness of the piled-up region in the silicon. In addition, it is possible to clearly distinguish between the segregated atoms and the As atoms in the bulk over a large range of implantation doses from 3middot1012 cm-2 to 1middot10-16 cm-2. The samples were annealed at 900degC and 1000degC, respectively, for times sufficiently long to ensure that the segregation reflects an equilibrium effect. With this approach, the pile-up of As was measured with new precision.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124616821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430940
G. Wang, E. Toh, Y. Foo, S. Tripathy, S. Balakumar, G. Lo, G. Samudra, Y. Yeo
We demonstrate a novel strained Si n-FET where the strain-transfer efficiency of lattice-mismatched source/drain (S/D) stressors is increased significantly by the interaction between an embedded Si0.7Ge0.3 stress transfer layer (STL) and the SiC source/drain (S/D) stressors. The compliance of the SiGe-OI STL caused significant uniaxial tensile strain to be induced in the Si channel. Devices with gate length LG down to 50 nm were fabricated. The strain effects resulted in 59% drive current improvement compared to unstrained Si control n-FETs. In addition, the incorporation of a tensile stress SiN liner improves Id,sat by an additional 10%. Improvement in source-side injection velocity as a result of the lattice interaction between the Si0.7Ge0.3 STL and S/D regions is further investigated.
{"title":"Uniaxial strained silicon n-FETs on silicon-germanium-on-insulator substrates with an e-Si0.7Ge0.3 stress transfer layer and source/drain stressors for performance enhancement","authors":"G. Wang, E. Toh, Y. Foo, S. Tripathy, S. Balakumar, G. Lo, G. Samudra, Y. Yeo","doi":"10.1109/ESSDERC.2007.4430940","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430940","url":null,"abstract":"We demonstrate a novel strained Si n-FET where the strain-transfer efficiency of lattice-mismatched source/drain (S/D) stressors is increased significantly by the interaction between an embedded Si0.7Ge0.3 stress transfer layer (STL) and the SiC source/drain (S/D) stressors. The compliance of the SiGe-OI STL caused significant uniaxial tensile strain to be induced in the Si channel. Devices with gate length LG down to 50 nm were fabricated. The strain effects resulted in 59% drive current improvement compared to unstrained Si control n-FETs. In addition, the incorporation of a tensile stress SiN liner improves Id,sat by an additional 10%. Improvement in source-side injection velocity as a result of the lattice interaction between the Si0.7Ge0.3 STL and S/D regions is further investigated.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133430298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430954
L. Harik, J. Sallese, M. Kayal
In this paper, we have used the partially depleted SOI MOSFET to measure the intensity of light. The charge pumping technique was used to get rid of the photogenerated carriers in the body in an attempt to keep the drain current constant. Using this technique flux densities as low as 2 mW/m2 were measured.
{"title":"Transient charge pumping as a new technique for a higher sensitivity SOI MOSFET photodetector","authors":"L. Harik, J. Sallese, M. Kayal","doi":"10.1109/ESSDERC.2007.4430954","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430954","url":null,"abstract":"In this paper, we have used the partially depleted SOI MOSFET to measure the intensity of light. The charge pumping technique was used to get rid of the photogenerated carriers in the body in an attempt to keep the drain current constant. Using this technique flux densities as low as 2 mW/m2 were measured.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125774823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430969
Y. Chauhan, R. Gillon, M. Declercq, A. Ionescu
In this work, a detailed analysis of capacitance behavior of high voltage MOSFET (HV-MOS) e.g. LDMOS, VDMOS using device simulation is made. The impact of lateral non-uniform doping and drift region is separately analyzed. It is shown that the peaks in CGD and CGS capacitances of HV-MOS originate from lateral non-uniform doping. The drift region decreases the CGD capacitance and increases the peaks in CGS and also gives rise to peaks in CGG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier degradation modulates (or introduce) the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation.
{"title":"Impact of lateral non-uniform doping and hot carrier degradation on capacitance behavior of high voltage MOSFETs","authors":"Y. Chauhan, R. Gillon, M. Declercq, A. Ionescu","doi":"10.1109/ESSDERC.2007.4430969","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430969","url":null,"abstract":"In this work, a detailed analysis of capacitance behavior of high voltage MOSFET (HV-MOS) e.g. LDMOS, VDMOS using device simulation is made. The impact of lateral non-uniform doping and drift region is separately analyzed. It is shown that the peaks in CGD and CGS capacitances of HV-MOS originate from lateral non-uniform doping. The drift region decreases the CGD capacitance and increases the peaks in CGS and also gives rise to peaks in CGG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier degradation modulates (or introduce) the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129754493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430949
J. Duvernay, G. Borot, P. Chevalier, D. Dutartre, R. Pantel, L. Rubaldo, T. Schwartzmann, B. Vandelle, A. Chantre
In this paper, we describe the development of a pnp SiGeC HBT using a self-aligned selective epitaxy emitter/base architecture. The device physics and the impact of the valence band barriers taking place in pnp HBTs are detailed. The Ge and impurities profiles optimization necessary to limit their negative influence is particularly described. Static and dynamic device characteristics are discussed.
{"title":"An experimental and simulation study of pnp Si/SiGeC HBTs using box-like Ge profiles","authors":"J. Duvernay, G. Borot, P. Chevalier, D. Dutartre, R. Pantel, L. Rubaldo, T. Schwartzmann, B. Vandelle, A. Chantre","doi":"10.1109/ESSDERC.2007.4430949","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430949","url":null,"abstract":"In this paper, we describe the development of a pnp SiGeC HBT using a self-aligned selective epitaxy emitter/base architecture. The device physics and the impact of the valence band barriers taking place in pnp HBTs are detailed. The Ge and impurities profiles optimization necessary to limit their negative influence is particularly described. Static and dynamic device characteristics are discussed.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130750793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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