Pub Date : 2007-01-09DOI: 10.1109/ESSDERC.2007.4430958
K. Huet, J. Saint-Martin, A. Bournel, S. Galdin-Retailleau, P. Dollfus, G. Ghibaudo, M. Mouis
The concept of mobility, resulting from an analysis of stationary transport where carrier velocity is limited by scattering phenomena, has been widely used till today in microelectronics as a measurable factor of merit and as a parameter of analytical models developed to predict device performance. If scatterings are still playing a major role in decananometer MOSFET and cannot be neglected, ballistic transport in the channel takes a growing importance as the gate length of MOSFETs tends to the nanometer scale. In this context, the mobility concept may appear as highly questionable.
{"title":"Monte Carlo study of apparent mobility reduction in nano-MOSFETs","authors":"K. Huet, J. Saint-Martin, A. Bournel, S. Galdin-Retailleau, P. Dollfus, G. Ghibaudo, M. Mouis","doi":"10.1109/ESSDERC.2007.4430958","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430958","url":null,"abstract":"The concept of mobility, resulting from an analysis of stationary transport where carrier velocity is limited by scattering phenomena, has been widely used till today in microelectronics as a measurable factor of merit and as a parameter of analytical models developed to predict device performance. If scatterings are still playing a major role in decananometer MOSFET and cannot be neglected, ballistic transport in the channel takes a growing importance as the gate length of MOSFETs tends to the nanometer scale. In this context, the mobility concept may appear as highly questionable.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With technology scaling becoming ever more difficult, the drive to continue to deliver performance and density has led to increasing technology complexity. Examples include the pervasive application of resolution enhancement techniques (RET) to enable sub-wavelength lithography and achieve circuit density, and strain engineering to improve device mobility and achieve circuit performance. The result of this increasing technology complexity has been a corresponding increase in the complexity of design/technology interaction. This phenomena demonstrates itself as a drastic increase in the number and complexity of design rules. Many of these rules are the result of the increase of the number and magnitude of systematic effects. In addition to these systematic sources of variability, we have an increasing host of random variations such as line edge roughness, which impacts channel lengths, and random dopant fluctuations, which impact threshold voltage. The net result has been a reduction in our ability to reliably predict the outcome of the manufacturing process. Given that the integrated circuit design process is based completely on our ability to create computer models of the expected behavior of a design, this gap in predictability is a source of grave concern. Model to Hardware matching attempts to close this gap by developing techniques, tools, and design components which can be used to improve technology predictability.
{"title":"Model to hardware matching for nano-meter scale technologies","authors":"S. Nassif","doi":"10.1145/1165573.1165621","DOIUrl":"https://doi.org/10.1145/1165573.1165621","url":null,"abstract":"With technology scaling becoming ever more difficult, the drive to continue to deliver performance and density has led to increasing technology complexity. Examples include the pervasive application of resolution enhancement techniques (RET) to enable sub-wavelength lithography and achieve circuit density, and strain engineering to improve device mobility and achieve circuit performance. The result of this increasing technology complexity has been a corresponding increase in the complexity of design/technology interaction. This phenomena demonstrates itself as a drastic increase in the number and complexity of design rules. Many of these rules are the result of the increase of the number and magnitude of systematic effects. In addition to these systematic sources of variability, we have an increasing host of random variations such as line edge roughness, which impacts channel lengths, and random dopant fluctuations, which impact threshold voltage. The net result has been a reduction in our ability to reliably predict the outcome of the manufacturing process. Given that the integrated circuit design process is based completely on our ability to create computer models of the expected behavior of a design, this gap in predictability is a source of grave concern. Model to Hardware matching attempts to close this gap by developing techniques, tools, and design components which can be used to improve technology predictability.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"126 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122377056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ESSDERC.2007.4430914
Hongyu Yu, Shou-Zen Chang, A. Veloso, A. Lauwers, A. Delabie, J. Everaert, R. Singanamalla, C. Kerner, C. Vrancken, S. Brus, P. Absil, T. Hoffmann, S. Biesemans
In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V, is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI, and nFETs PBTI) are clearly improved; 4) both the gate capacitance equivalent thickness (Tinv) and the long channel device high Eeff mobility are preserved. High-Vt ring oscillator with a delay of 17ps has been demonstrated, showing a much-reduced static power (~10 times) as compared to the devices using the pure SiON dielectrics. It is proposed that the SiON dielectrics capped with sub-monolayer HfSiON, in combination with the phase-controlled Ni-FUSI technology, is promising for 45 nm and beyond low power CMOS applications.
{"title":"Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications","authors":"Hongyu Yu, Shou-Zen Chang, A. Veloso, A. Lauwers, A. Delabie, J. Everaert, R. Singanamalla, C. Kerner, C. Vrancken, S. Brus, P. Absil, T. Hoffmann, S. Biesemans","doi":"10.1109/ESSDERC.2007.4430914","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430914","url":null,"abstract":"In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V, is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI, and nFETs PBTI) are clearly improved; 4) both the gate capacitance equivalent thickness (Tinv) and the long channel device high Eeff mobility are preserved. High-Vt ring oscillator with a delay of 17ps has been demonstrated, showing a much-reduced static power (~10 times) as compared to the devices using the pure SiON dielectrics. It is proposed that the SiON dielectrics capped with sub-monolayer HfSiON, in combination with the phase-controlled Ni-FUSI technology, is promising for 45 nm and beyond low power CMOS applications.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127834428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/esscirc.2007.4430256
C. Koch, J. Oehm, J. Emde, W. Budde
Integrated optical sensors make use of a p-n-junction for light intensity detection, typically. Because of the costs, additional optical components are not available in standard integration processes. Therefore, in higher level optical sensors extra optical components are not part of an integration. In this paper a concept for integration is proposed, which especially allows to measure the angles of a far distance light source relative to the surface of the chip and the coordinate system of the integrated structure. The invention makes use of the stack topology and the light opacity of metal layers in the monolithic integration, the light translucency of SiO2, and the electrical light sensitivity of p-n-junctions. The implementation can be done most advantageously in SOI CMOS technology. With minor modifications it is applicable in other integration technologies as well.
{"title":"Integrated sensor for light source position measurement applicable in SOI technology","authors":"C. Koch, J. Oehm, J. Emde, W. Budde","doi":"10.1109/esscirc.2007.4430256","DOIUrl":"https://doi.org/10.1109/esscirc.2007.4430256","url":null,"abstract":"Integrated optical sensors make use of a p-n-junction for light intensity detection, typically. Because of the costs, additional optical components are not available in standard integration processes. Therefore, in higher level optical sensors extra optical components are not part of an integration. In this paper a concept for integration is proposed, which especially allows to measure the angles of a far distance light source relative to the surface of the chip and the coordinate system of the integrated structure. The invention makes use of the stack topology and the light opacity of metal layers in the monolithic integration, the light translucency of SiO2, and the electrical light sensitivity of p-n-junctions. The implementation can be done most advantageously in SOI CMOS technology. With minor modifications it is applicable in other integration technologies as well.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131172146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ESSDERC.2007.4430939
B. Tsui, Chi-Pei Lu
Current transport mechanisms of Schottky barrier (SB) and modified Schottky barrier (MSB) MOSFETs are investigated by measuring the temperature effect on current-voltage characteristics. For SB MOSFETs, current transport could be dominated by thermionic emission or tunneling mechanism depends on the Schottky barrier height and the gate voltage. The current transport of the MSB MOSFETs changes from tunneling mechanism to drift-diffusion mechanism as the gate voltage increases. The changing point is a good indicator to evaluate the efficiency of the MSB junction. Since the current transport mechanism depends on bias condition, the extraction of mobility should be treated carefully, especially at low gate voltage.
{"title":"Current transport mechanisms of Schottky barrier and modified Schottky barrier MOSFETs","authors":"B. Tsui, Chi-Pei Lu","doi":"10.1109/ESSDERC.2007.4430939","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430939","url":null,"abstract":"Current transport mechanisms of Schottky barrier (SB) and modified Schottky barrier (MSB) MOSFETs are investigated by measuring the temperature effect on current-voltage characteristics. For SB MOSFETs, current transport could be dominated by thermionic emission or tunneling mechanism depends on the Schottky barrier height and the gate voltage. The current transport of the MSB MOSFETs changes from tunneling mechanism to drift-diffusion mechanism as the gate voltage increases. The changing point is a good indicator to evaluate the efficiency of the MSB junction. Since the current transport mechanism depends on bias condition, the extraction of mobility should be treated carefully, especially at low gate voltage.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/esscirc.2007.4430258
C. Pacha, K. Arnim, F. Bauer, T. Schulz, W. Xiong, K. T. San, A. Marshall, T. Baumann, C. Cleavelin, K. Schruefer, J. Berthold
Energy dissipation, performance, and voltage scaling of multi-gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.
{"title":"Efficiency of low-power design techniques in multi-gate FET CMOS circuits","authors":"C. Pacha, K. Arnim, F. Bauer, T. Schulz, W. Xiong, K. T. San, A. Marshall, T. Baumann, C. Cleavelin, K. Schruefer, J. Berthold","doi":"10.1109/esscirc.2007.4430258","DOIUrl":"https://doi.org/10.1109/esscirc.2007.4430258","url":null,"abstract":"Energy dissipation, performance, and voltage scaling of multi-gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132512977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/essderc.2007.4430885
A. Kahng
Semiconductor product value increasingly depends on "equivalent scaling" achieved by design and design-for-manufacturability (DFM) techniques. This talk addresses trends and a roadmap for "equivalent scaling" innovation at the design-manufacturing interface. The first part will discuss precepts of electrical DFM. What are dominant aspects of manufacturing variability and design requirements? Can designs match process, or must process inevitably adapt to designs? In what sense can concepts of "virtual manufacturing" or "statistical optimization" succeed in the design flow? How should design technology balance analyses that preserve value, versus optimizations that extend value? How should we balance preventions (correct by construction), versus early interventions, versus cures (construct by correction), versus "do no harm" opportunism? Or, tools that can model and predict well, versus tools that can make upstream assumptions come true? The second part will give a roadmap for electrical DFM technologies, motivated by emerging challenges (stress/strain engineering, mask errors, double-patterning lithography, etc.) and highlighting needs for < 45 nm nodes.
{"title":"Key directions and a roadmap for electrical design for manufacturability","authors":"A. Kahng","doi":"10.1109/essderc.2007.4430885","DOIUrl":"https://doi.org/10.1109/essderc.2007.4430885","url":null,"abstract":"Semiconductor product value increasingly depends on \"equivalent scaling\" achieved by design and design-for-manufacturability (DFM) techniques. This talk addresses trends and a roadmap for \"equivalent scaling\" innovation at the design-manufacturing interface. The first part will discuss precepts of electrical DFM. What are dominant aspects of manufacturing variability and design requirements? Can designs match process, or must process inevitably adapt to designs? In what sense can concepts of \"virtual manufacturing\" or \"statistical optimization\" succeed in the design flow? How should design technology balance analyses that preserve value, versus optimizations that extend value? How should we balance preventions (correct by construction), versus early interventions, versus cures (construct by correction), versus \"do no harm\" opportunism? Or, tools that can model and predict well, versus tools that can make upstream assumptions come true? The second part will give a roadmap for electrical DFM technologies, motivated by emerging challenges (stress/strain engineering, mask errors, double-patterning lithography, etc.) and highlighting needs for < 45 nm nodes.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"278 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133048127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/esscirc.2007.4430255
B. Hosticka
This contribution is devoted to CMOS analog circuit design for integrated sensor systems. While today complex sensor signal processing tends to be implemented in digital domain, analog circuits still play a crucial role in sensor signal acquisition due to analog nature of sensory signals. Though sensor front-ends frequently employ analog circuits, e.g. for sensor signal conditioning and conversion, generation of bias and reference voltages and currents, and system interfacing, the most important circuit here -for both, on-and off-chip sensors -is the sensor readout, since it directly interfaces the sensor.
{"title":"Analog circuits for sensors","authors":"B. Hosticka","doi":"10.1109/esscirc.2007.4430255","DOIUrl":"https://doi.org/10.1109/esscirc.2007.4430255","url":null,"abstract":"This contribution is devoted to CMOS analog circuit design for integrated sensor systems. While today complex sensor signal processing tends to be implemented in digital domain, analog circuits still play a crucial role in sensor signal acquisition due to analog nature of sensory signals. Though sensor front-ends frequently employ analog circuits, e.g. for sensor signal conditioning and conversion, generation of bias and reference voltages and currents, and system interfacing, the most important circuit here -for both, on-and off-chip sensors -is the sensor readout, since it directly interfaces the sensor.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115571536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/esscirc.2007.4430247
Kinam Kim, Donggun Park
Summary form only given. Since the inventions of silicon memory devices at early 70's, silicon memory devices have been advanced with unprecedented pace which results in exponential growth of storage capacity of memory devices, and now they reach to 1Gb density with 60 nm node for DRAM and 16 Gb density with 50 nm node for NAND Flash. During the evolution of silicon memory devices for the last 3 decades, silicon memory devices on-and-off faced critical challenges which seemed to be very difficult to surmount at initial stage, but those challenges were eventually cleared by appropriate cost-effective solutions and some of challenges paradigm shifted silicon memory technologies from simple and common planar technology to complicated and diversified technologies such as planar transistor with 3-D capacitor and recently 3-D transistor with 3-D capacitor and etc. However, as the silicon technologies further enter deep nano-scale dimensions, silicon memory devices will encounter much critical challenges originated from ultimate limit of the transistor scaling and shallow margins in manufacturing due to ever-increasing fabrication costs resulting from technical complexities. Although there seems to be no unanimous solutions for silicon memory devices in future, most of experts working in silicon memory area, however, believe that silicon memory technology will be given right solutions down to a 20 nm node where a transistor contains only a small number of electrons, which is believed to be a practical limit to avoid noise errors owing to random telegraph noises, signal variations due to 1/radicn statistics, and fluctuations due to both rough edges of propagating lines and thickness variations and so forth. In addition, there are still many unknowns about the deep nano scaled memory devices. Thus, in this paper, in order to find the right directions of future semiconductor memory devices, key challenges and their possible solutions will be mainly discussed in views of basics and key features of semiconductor memory devices, key technologies and designs.
{"title":"The future outlook of memory devices","authors":"Kinam Kim, Donggun Park","doi":"10.1109/esscirc.2007.4430247","DOIUrl":"https://doi.org/10.1109/esscirc.2007.4430247","url":null,"abstract":"Summary form only given. Since the inventions of silicon memory devices at early 70's, silicon memory devices have been advanced with unprecedented pace which results in exponential growth of storage capacity of memory devices, and now they reach to 1Gb density with 60 nm node for DRAM and 16 Gb density with 50 nm node for NAND Flash. During the evolution of silicon memory devices for the last 3 decades, silicon memory devices on-and-off faced critical challenges which seemed to be very difficult to surmount at initial stage, but those challenges were eventually cleared by appropriate cost-effective solutions and some of challenges paradigm shifted silicon memory technologies from simple and common planar technology to complicated and diversified technologies such as planar transistor with 3-D capacitor and recently 3-D transistor with 3-D capacitor and etc. However, as the silicon technologies further enter deep nano-scale dimensions, silicon memory devices will encounter much critical challenges originated from ultimate limit of the transistor scaling and shallow margins in manufacturing due to ever-increasing fabrication costs resulting from technical complexities. Although there seems to be no unanimous solutions for silicon memory devices in future, most of experts working in silicon memory area, however, believe that silicon memory technology will be given right solutions down to a 20 nm node where a transistor contains only a small number of electrons, which is believed to be a practical limit to avoid noise errors owing to random telegraph noises, signal variations due to 1/radicn statistics, and fluctuations due to both rough edges of propagating lines and thickness variations and so forth. In addition, there are still many unknowns about the deep nano scaled memory devices. Thus, in this paper, in order to find the right directions of future semiconductor memory devices, key challenges and their possible solutions will be mainly discussed in views of basics and key features of semiconductor memory devices, key technologies and designs.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127445947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：