Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430946
I. Martín-Bragado, I. Avci, N. Zographos, P. Castrillo, M. Jaraíz
An atomistic model for self-interstitial extended defects is presented in this work. Using a limited set of assumptions about the shape and emission frequency of extended defects, and taking as parameters the interstitial binding energies of extended defects versus their size, this model is able to predict a wide variety of experimental results. The model accounts for the whole extended defect evolution, from the initial small irregular clusters to the {311} defects and to the more stable dislocation loops. The model predicts the extended defect dissolution, supersaturation and defect size evolution with time, and it takes into account the thermally activated transformation of {311} defects into dislocation. The model is also used to explore a two-phase exponential decay observed in the dissolution of {311} defects.
{"title":"From point defects to dislocation loops: A comprehensive TCAD model for self-interstitial defects in silicon","authors":"I. Martín-Bragado, I. Avci, N. Zographos, P. Castrillo, M. Jaraíz","doi":"10.1109/ESSDERC.2007.4430946","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430946","url":null,"abstract":"An atomistic model for self-interstitial extended defects is presented in this work. Using a limited set of assumptions about the shape and emission frequency of extended defects, and taking as parameters the interstitial binding energies of extended defects versus their size, this model is able to predict a wide variety of experimental results. The model accounts for the whole extended defect evolution, from the initial small irregular clusters to the {311} defects and to the more stable dislocation loops. The model predicts the extended defect dissolution, supersaturation and defect size evolution with time, and it takes into account the thermally activated transformation of {311} defects into dislocation. The model is also used to explore a two-phase exponential decay observed in the dissolution of {311} defects.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133953099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430977
C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J. Hartmann, M. Roure, H. Grampeix, S. Deleonibus
Abstract-For the first time, we report on deep sub-micron (gate length down to 0.12 mum) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cuttrade process to fabricate 200 mm GeOI wafers with Ge thickness down to 60 nm. A full CMOS compatible p-MOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION IOFF Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.
{"title":"0.12μm P-MOSFETs with High-K and Metal Gate Fabricated in a Si Process Line on 200mm GeOI Wafers","authors":"C. Le Royer, L. Clavelier, C. Tabone, C. Deguet, L. Sanchez, J. Hartmann, M. Roure, H. Grampeix, S. Deleonibus","doi":"10.1109/ESSDERC.2007.4430977","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430977","url":null,"abstract":"Abstract-For the first time, we report on deep sub-micron (gate length down to 0.12 mum) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart-Cuttrade process to fabricate 200 mm GeOI wafers with Ge thickness down to 60 nm. A full CMOS compatible p-MOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION IOFF Gm, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134496606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, the electroless plated (EP) Pd/InGaP high electron mobility transistor (HEMT) was firstly employed for hydrogen sensing. The current-voltage (I-V) characteristics under hydrogen concentrations of 5 ppm-1% and temperatures of 303-503 K were investigated. Experimentally, the Pd gate of three-terminal devices were successfully fabricated by the electroless plating method, and the studied devices exhibited excellent current-voltage characteristics with superior current control ability. For hydrogen sensing performances, the studied EP device demonstrated low detection limit, high sensitivity, and fast response. As compared with the thermal evaporated (TE) device, larger current variations can be achieved by the EP device. Even at extremely low hydrogen concentration, e.g., 4.3 ppm H2/air, obvious current modulation was found. The maximum relative sensitivity reaches up to 428 % at a optimal gate voltage of -0.75 V. Furthermore, the transient detections showed that the sensing response was fairly fast, especially at high concentrations and high temperatures. At detection temperature of 403 K, the time for 90% response at 1 % H2/air was within 4 seconds. These excellent sensing performances of the EP device indeed made it promising and competitive in future developments of smart hydrogen sensors integrated microelectronic systems.
{"title":"A High-Sensitive Pd/InGaP transistor hydrogen sensor","authors":"Chung-Yeh Wu, Chin-Tien Lin, Yen-I Chou, Chieng-Chi Tung, Wen-Chau Liu, Huey-Ing Chen","doi":"10.1109/ESSDERC.2007.4430973","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430973","url":null,"abstract":"In this work, the electroless plated (EP) Pd/InGaP high electron mobility transistor (HEMT) was firstly employed for hydrogen sensing. The current-voltage (I-V) characteristics under hydrogen concentrations of 5 ppm-1% and temperatures of 303-503 K were investigated. Experimentally, the Pd gate of three-terminal devices were successfully fabricated by the electroless plating method, and the studied devices exhibited excellent current-voltage characteristics with superior current control ability. For hydrogen sensing performances, the studied EP device demonstrated low detection limit, high sensitivity, and fast response. As compared with the thermal evaporated (TE) device, larger current variations can be achieved by the EP device. Even at extremely low hydrogen concentration, e.g., 4.3 ppm H2/air, obvious current modulation was found. The maximum relative sensitivity reaches up to 428 % at a optimal gate voltage of -0.75 V. Furthermore, the transient detections showed that the sensing response was fairly fast, especially at high concentrations and high temperatures. At detection temperature of 403 K, the time for 90% response at 1 % H2/air was within 4 seconds. These excellent sensing performances of the EP device indeed made it promising and competitive in future developments of smart hydrogen sensors integrated microelectronic systems.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132079394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430979
D. Moran, R. Hill, X. Li, H. Zhou, D. Mclntyre, S. Thoms, R. Droopad, P. Zurcher, K. Rajagopalan, J. Abrokwah, M. Passlack, I. Thayne
The performance of 300 nm, 500 nm and 1 mum metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10 nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-kappa (kappa=20) dielectric stack grown upon a delta-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 mum to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 muA/mum and extrinsic transconductance of 400 muS/mum are obtained from these devices. Gate leakage current of less than 100 pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance sub-micron enhancement mode III-V MOSFETs reported to date.
报道了300 nm、500 nm和1 μ m金属栅、无植入物、增强模式III-V型mosfet的性能。器件采用在δ掺杂AlGaAs/InGaAs/AlGaAs/GaAs异质结构上生长的10 nm MBE生长的Ga2O3/(GaxGd1-x)2O3高kappa (kappa=20)介电层来实现。当栅极尺寸从1微米减小到300纳米时，在三个栅极长度上保持增强模式操作，阈值电压从0.26 V降低到0.08 V。随着栅极尺寸的减小，也观察到跨导率的增加。这些器件的最大漏极电流为420 μ a /mum，外部跨导为400 μ a /mum。在所有栅极长度下，栅极泄漏电流均小于100 pA，亚阈值斜率为90 mV/ 10年。这些被认为是迄今为止报道的性能最高的亚微米增强模式III-V mosfet。
{"title":"Sub-micron, metal gate, high-к dielectric, implant-free, enhancement-mode III-V mosfets","authors":"D. Moran, R. Hill, X. Li, H. Zhou, D. Mclntyre, S. Thoms, R. Droopad, P. Zurcher, K. Rajagopalan, J. Abrokwah, M. Passlack, I. Thayne","doi":"10.1109/ESSDERC.2007.4430979","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430979","url":null,"abstract":"The performance of 300 nm, 500 nm and 1 mum metal gate, implant free, enhancement mode III-V MOSFETs are reported. Devices are realised using a 10 nm MBE grown Ga2O3/(GaxGd1-x)2O3 high-kappa (kappa=20) dielectric stack grown upon a delta-doped AlGaAs/InGaAs/AlGaAs/GaAs heterostructure. Enhancement mode operation is maintained across the three reported gate lengths with a reduction in threshold voltage from 0.26 V to 0.08 V as the gate dimension is reduced from 1 mum to 300 nm. An increase in transconductance is also observed with reduced gate dimension. Maximum drain current of 420 muA/mum and extrinsic transconductance of 400 muS/mum are obtained from these devices. Gate leakage current of less than 100 pA and subthreshold slope of 90 mV/decade were obtained for all gate lengths. These are believed to be the highest performance sub-micron enhancement mode III-V MOSFETs reported to date.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123154412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430972
A. Batmanov, A. Boutejdar, E. Burte, A. Omar
A new compact microwave defected-ground-structure (DGS) coplanar bandpass filter (BPF), which operates from 18 to 26 GHz (k-band), has been designed and simulated. The proposed structure can be redesigned for an other frequency range by changing the geometrical parameters of the CPW lines. The bandpass filter occupies an area of 2.8times1.3 mm2 and consists of two cascaded parallel-resonance circuits coupled with a series capacitor, forming a series resonator. The use of MEMS series-resistive contact switches between the additional external stub and metallic ground planes permits systematic control of the bandwidth and thus the control of two transmission zeroes in the frequency domain. Therefore, the designed bandpass filter has a wide upper bandstop and an improved symmetry of the bandpass response. The equivalent circuit extraction method has also been derived. Simulations based on the proposed circuit model are in good agreement with the electromagnetic (EM) simulation. The BPF has been designed in CPW environment on high-resistivity silicon substrate and therefore is suitable for standard MIS and MMIS.
{"title":"New compact MEMS-switch controlled tunable DGS coplanar bandpass filter","authors":"A. Batmanov, A. Boutejdar, E. Burte, A. Omar","doi":"10.1109/ESSDERC.2007.4430972","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430972","url":null,"abstract":"A new compact microwave defected-ground-structure (DGS) coplanar bandpass filter (BPF), which operates from 18 to 26 GHz (k-band), has been designed and simulated. The proposed structure can be redesigned for an other frequency range by changing the geometrical parameters of the CPW lines. The bandpass filter occupies an area of 2.8times1.3 mm2 and consists of two cascaded parallel-resonance circuits coupled with a series capacitor, forming a series resonator. The use of MEMS series-resistive contact switches between the additional external stub and metallic ground planes permits systematic control of the bandwidth and thus the control of two transmission zeroes in the frequency domain. Therefore, the designed bandpass filter has a wide upper bandstop and an improved symmetry of the bandpass response. The equivalent circuit extraction method has also been derived. Simulations based on the proposed circuit model are in good agreement with the electromagnetic (EM) simulation. The BPF has been designed in CPW environment on high-resistivity silicon substrate and therefore is suitable for standard MIS and MMIS.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116642355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430920
A. Villaret, E. Ebrard, N. Casanova, S. Guillaumet, P. Candelier, P. Coronel, J. Schoellkopf, T. Skotnicki
In this paper, we report a study on an alternative one time programmable (OTP) memory cell consisting in an access MOSFET and a capacitor integrated between the contact plug and the first metal line level. Such an OTP should result in a denser cell as compared to the standard polyfuse or antifuse OTPs. The results obtained on these integrated capacitors show good overall electrical performance with breakdown voltage adjustable under 5 V and large sense current margins (about 6 decades). The dispersion, even if quite large in this initial study, proved to be manageable since the capacitor's acceleration factors are high.
{"title":"W/Ta2O5/TaN MIM capacitor for high density one time programmable memory","authors":"A. Villaret, E. Ebrard, N. Casanova, S. Guillaumet, P. Candelier, P. Coronel, J. Schoellkopf, T. Skotnicki","doi":"10.1109/ESSDERC.2007.4430920","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430920","url":null,"abstract":"In this paper, we report a study on an alternative one time programmable (OTP) memory cell consisting in an access MOSFET and a capacitor integrated between the contact plug and the first metal line level. Such an OTP should result in a denser cell as compared to the standard polyfuse or antifuse OTPs. The results obtained on these integrated capacitors show good overall electrical performance with breakdown voltage adjustable under 5 V and large sense current margins (about 6 decades). The dispersion, even if quite large in this initial study, proved to be manageable since the capacitor's acceleration factors are high.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123415537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSCIRC.2007.4430254
B. Cheng, Scott Roy, A. Asenov
Intrinsic parameter fluctuations are already a limiting factor for 6-Transistor SRAM scaling. In order to maintain the benefits of CMOS scaling, new SRAM cell designs are necessary. An 8-Transistor SRAM cell structure is investigated and the impact of random doping fluctuations on its read and write noise margins, considering various supply voltages, are discussed. The results demonstrate impressive scalability, and indicate that the scaling window is still open for SRAM in the deca-nanometer regime.
{"title":"The scalability of 8T-SRAM cells under the influence of intrinsic parameter fluctuations","authors":"B. Cheng, Scott Roy, A. Asenov","doi":"10.1109/ESSCIRC.2007.4430254","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430254","url":null,"abstract":"Intrinsic parameter fluctuations are already a limiting factor for 6-Transistor SRAM scaling. In order to maintain the benefits of CMOS scaling, new SRAM cell designs are necessary. An 8-Transistor SRAM cell structure is investigated and the impact of random doping fluctuations on its read and write noise margins, considering various supply voltages, are discussed. The results demonstrate impressive scalability, and indicate that the scaling window is still open for SRAM in the deca-nanometer regime.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125774784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430926
D. Aimé, C. Fenouillet-Béranger, P. Perreau, S. Denorme, J. Coignus, A. Cros, D. Fleury, O. Faynot, A. Vandooren, R. Gassilloud, F. Martin, S. Barnola, T. Salvetat, G. Chabanne, L. Brevard, M. Aminpur, F. Leverd, R. Gwoziecki, F. Boeuf, C. Hobbs, A. Zauner, M. Muller, V. Cosnier, S. Minoref, D. Bensahel, M. Orlowski, H. Mingam, A. Wild, S. Deleonibus, T. Skotnicki
This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.
本文描述了一种全耗尽SOI技术的制造和电气性能，该技术使用直接金属栅极和高k介电集成在300 mm SOI晶圆上，用于低功耗应用。我们报道了在HfSiON栅极电介质上具有WN金属栅极(覆有TiN)的超薄FDSOI MOS晶体管。演示了器件和电路级的性能，并与TiN中隙金属栅极进行了比较。
{"title":"Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric","authors":"D. Aimé, C. Fenouillet-Béranger, P. Perreau, S. Denorme, J. Coignus, A. Cros, D. Fleury, O. Faynot, A. Vandooren, R. Gassilloud, F. Martin, S. Barnola, T. Salvetat, G. Chabanne, L. Brevard, M. Aminpur, F. Leverd, R. Gwoziecki, F. Boeuf, C. Hobbs, A. Zauner, M. Muller, V. Cosnier, S. Minoref, D. Bensahel, M. Orlowski, H. Mingam, A. Wild, S. Deleonibus, T. Skotnicki","doi":"10.1109/ESSDERC.2007.4430926","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430926","url":null,"abstract":"This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130278609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430877
K. Ishimaru
Product of 45 nm node technology will start by the end of this year. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the usage of immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high-k gate insulator system. Self barrier layer formation for BEOL is also new item. To achieve the target performance, performance improvement for each component is required. Variability in not only SRAM but also in logic will increase. To overcome these difficulties, closer collaboration between device and circuit is important.
{"title":"45nm/32nm CMOS ∼challenge and perspective∼","authors":"K. Ishimaru","doi":"10.1109/ESSDERC.2007.4430877","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430877","url":null,"abstract":"Product of 45 nm node technology will start by the end of this year. However, difficulty of new technology development is increasing and some company dropped off from the competition. The big challenge for 45 nm node is the usage of immersion lithography. Most of the other technologies used for 45 nm node are the extension of those used for 65 nm node. On the other hand, there will be a big jump for 32 nm node technology. The biggest item is metal gate and high-k gate insulator system. Self barrier layer formation for BEOL is also new item. To achieve the target performance, performance improvement for each component is required. Variability in not only SRAM but also in logic will increase. To overcome these difficulties, closer collaboration between device and circuit is important.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134600472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/ESSDERC.2007.4430909
M. Ramonas, P. Sakalas, C. Jungemann, M. Schroter, W. Kraus, A. Shimukovitch
The SIMS doping profile of SiGe heterojunction bipolar transistor is calibrated for best agreement of the hydrodynamic model results with the experiment. DC and small-signal data is used for the calibration. The terminal current noise calculations are performed using both hydrodynamic and drift-diffusion models with the calibrated doping profile. The calculation results are compared with the experimental values. Overall good agreement for the minimum noise figure, the noise resistance, and the optimum reflection coefficient is obtained. The difference between the hydrodynamic and drift-diffusion model results is analyzed using spectral intensities of the base and collector current fluctuations.
{"title":"Microscopic modeling of high frequency noise in SiGe HBTs","authors":"M. Ramonas, P. Sakalas, C. Jungemann, M. Schroter, W. Kraus, A. Shimukovitch","doi":"10.1109/ESSDERC.2007.4430909","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430909","url":null,"abstract":"The SIMS doping profile of SiGe heterojunction bipolar transistor is calibrated for best agreement of the hydrodynamic model results with the experiment. DC and small-signal data is used for the calibration. The terminal current noise calculations are performed using both hydrodynamic and drift-diffusion models with the calibrated doping profile. The calculation results are compared with the experimental values. Overall good agreement for the minimum noise figure, the noise resistance, and the optimum reflection coefficient is obtained. The difference between the hydrodynamic and drift-diffusion model results is analyzed using spectral intensities of the base and collector current fluctuations.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134345320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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