Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028415
D. Andrews, Levi Hill, A. Collins, Kok Inn Hoo, Stevan Hunter
Copper (Cu) wirebonds exhibit higher strength and stiffness as compared to gold (Au) wirebonds. Cu's higher shear strength is studied in this project. There is currently no industry standard specifically for the Cu ballbond shear procedure nor an appropriate bond reliability specification limit. The JEDEC industrial standard JESD22-B116A “Wire Bond Shear Test Method”, issued in 1998, covers Au ball bond reliability testing by shear. Companies typically apply the shear test limits of Au from this standard to Cu ball bonds on Al pads in manufacturing, though the Cu bonds may show significantly more shear strength than Au balls. Cu wirebonds have different failure modes, so a unique test method and reliability spec limit for Cu bonds is needed. ON Semiconductor has conducted experiments comparing shear test results for two Cu ball diameters on two different Al thicknesses, participating in the industrial committee to develop a new Cu shear test procedure (in progress). Selected data from the ON experiments are provided in this paper, demonstrating the behavior of Cu as compared with the limits that were developed for Au ball bonds.
{"title":"Copper ball bond shear test for two pad aluminum thicknesses","authors":"D. Andrews, Levi Hill, A. Collins, Kok Inn Hoo, Stevan Hunter","doi":"10.1109/EPTC.2014.7028415","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028415","url":null,"abstract":"Copper (Cu) wirebonds exhibit higher strength and stiffness as compared to gold (Au) wirebonds. Cu's higher shear strength is studied in this project. There is currently no industry standard specifically for the Cu ballbond shear procedure nor an appropriate bond reliability specification limit. The JEDEC industrial standard JESD22-B116A “Wire Bond Shear Test Method”, issued in 1998, covers Au ball bond reliability testing by shear. Companies typically apply the shear test limits of Au from this standard to Cu ball bonds on Al pads in manufacturing, though the Cu bonds may show significantly more shear strength than Au balls. Cu wirebonds have different failure modes, so a unique test method and reliability spec limit for Cu bonds is needed. ON Semiconductor has conducted experiments comparing shear test results for two Cu ball diameters on two different Al thicknesses, participating in the industrial committee to develop a new Cu shear test procedure (in progress). Selected data from the ON experiments are provided in this paper, demonstrating the behavior of Cu as compared with the limits that were developed for Au ball bonds.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130580601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028364
F. Che, Yong Han, B. L. Lau, Hengyun Zhang, Lu Zhang, Xiaowu Zhang
As chip power densities are now increasing beyond air cooling limits, a variety of liquid cooling methods are being investigated. The silicon microchannel cooling (SMC) is an attractive approach due to its high heat transfer coefficient. In this study, a thermal test chip with heating spots was mounted onto a synthetic diamond heat spreader, and then mounted onto the SMC cooler through temperature compression bonding (TCB) process. Finally, this structure was mounted onto the printed circuit board (PCB) and connected with the manifold. The reliability of the cooler system was investigated through mechanical modeling and characterization. Four types of models were conducted considering process flow and application conditions, including model of bonding thermal chip to heater spreader, model of whole cooler structure assembly, shear test model, and thermal-mechanical coupling analysis model considering hot spot heating. The cooler system was optimized based on finite element modeling results to reduce chip stress and package warpage. Die attach materials were also evaluated based on shear test and modeling results. The thermo-mechanical coupling simulation was conducted for cooler system by considering temperature non-uniform distribution due to hot spot and cooling effect. Results show that the designed cooler system meets the requirement of performance and reliability thermally and mechanically.
{"title":"Mechanical modeling and characterization of silicon micro cooler","authors":"F. Che, Yong Han, B. L. Lau, Hengyun Zhang, Lu Zhang, Xiaowu Zhang","doi":"10.1109/EPTC.2014.7028364","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028364","url":null,"abstract":"As chip power densities are now increasing beyond air cooling limits, a variety of liquid cooling methods are being investigated. The silicon microchannel cooling (SMC) is an attractive approach due to its high heat transfer coefficient. In this study, a thermal test chip with heating spots was mounted onto a synthetic diamond heat spreader, and then mounted onto the SMC cooler through temperature compression bonding (TCB) process. Finally, this structure was mounted onto the printed circuit board (PCB) and connected with the manifold. The reliability of the cooler system was investigated through mechanical modeling and characterization. Four types of models were conducted considering process flow and application conditions, including model of bonding thermal chip to heater spreader, model of whole cooler structure assembly, shear test model, and thermal-mechanical coupling analysis model considering hot spot heating. The cooler system was optimized based on finite element modeling results to reduce chip stress and package warpage. Die attach materials were also evaluated based on shear test and modeling results. The thermo-mechanical coupling simulation was conducted for cooler system by considering temperature non-uniform distribution due to hot spot and cooling effect. Results show that the designed cooler system meets the requirement of performance and reliability thermally and mechanically.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130201540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028266
Giuseppe Schiavone, Thomas Jones, D. Price, R. McPhillips, Z. Qiu, C. Démoré, Yun Jiang, C. Meggs, S. Mahboob, S. Eljamel, T. Button, S. Cochran, M. Desmulliez
Real-time ultrasound guidance during neurosurgery is a novel and sought-after technique that enables imaging data to be acquired with improved precision during surgical intervention. Surgical needles that are inserted in the tissue of interest can be guided using the real-time graphical information collected by an embedded ultrasound transducer. The miniaturisation capabilities of modern manufacturing technologies allow the fabrication of ultrasound probes that are small enough to be fitted in needles conventionally used in surgical practices (down to ~2 mm inner diameter). High lateral resolution may in fact be achieved by producing miniaturised ultrasound transducer arrays with a series of emitting/receiving elements, each electrically isolated from the others. To guarantee the functionality of such devices, a series of independent electrical interconnections must be implemented that enables the external driving electronics of the imaging system to be connected to the miniaturised ultrasound probe array. This paper presents a novel interconnection scheme designed to interface ultrasound probes integrated in surgical needles with the driving electronics. The presented solution utilises a flexible printed circuit board carrying the electrical tracks and a bonding technique with an anisotropic conductive paste.
{"title":"Advanced electrical array interconnections for ultrasound probes integrated in surgical needles","authors":"Giuseppe Schiavone, Thomas Jones, D. Price, R. McPhillips, Z. Qiu, C. Démoré, Yun Jiang, C. Meggs, S. Mahboob, S. Eljamel, T. Button, S. Cochran, M. Desmulliez","doi":"10.1109/EPTC.2014.7028266","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028266","url":null,"abstract":"Real-time ultrasound guidance during neurosurgery is a novel and sought-after technique that enables imaging data to be acquired with improved precision during surgical intervention. Surgical needles that are inserted in the tissue of interest can be guided using the real-time graphical information collected by an embedded ultrasound transducer. The miniaturisation capabilities of modern manufacturing technologies allow the fabrication of ultrasound probes that are small enough to be fitted in needles conventionally used in surgical practices (down to ~2 mm inner diameter). High lateral resolution may in fact be achieved by producing miniaturised ultrasound transducer arrays with a series of emitting/receiving elements, each electrically isolated from the others. To guarantee the functionality of such devices, a series of independent electrical interconnections must be implemented that enables the external driving electronics of the imaging system to be connected to the miniaturised ultrasound probe array. This paper presents a novel interconnection scheme designed to interface ultrasound probes integrated in surgical needles with the driving electronics. The presented solution utilises a flexible printed circuit board carrying the electrical tracks and a bonding technique with an anisotropic conductive paste.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127617667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028322
J. Zaal, A. Mavinkurve, R. Rongen, J. Janssen, P. Drummen
Cu bond wires in microelectronics have great potential but also provides several challenges. The acceleration factors or failure mechanisms in reliability tests are somewhat different with respect to gold wire bonding which, using unchanged but not validated test conditions and duration requirements, may lead to non-justified failures. With copper wire technology, the intermetallic compounds (IMC's) that form between the bond ball and the bond pad change in composition and corrosion behavior when compared to the gold wirebonding IMC's. When exposed to high temperatures, high moisture levels and high bias, these three different stress factors can add up to very high acceleration factors. When a product or material system fails in this test the question arises what the acceleration factor actually is and how this test compares to application conditions where temperatures may also rise significantly while high humidity levels may still be present and bias is applied. This could the operational startup phase after a long time of being in off or standby stage. The product will suddenly heat up due to the internal heat generation but moisture might still be present in the package. Combined with a high bias voltage this could lead to conditions as seen in the HAST test. To make a comparison between application and test, data was collected on the moisture properties of several molding compounds as a function of temperature. This data was then used in combination with thermal transient simulations of a product in application to compare actual moisture levels under use conditions to moisture levels in test. The simulation shows that the HAST test condition never occurs in the actual application and that the test condition is unrealistically accelerating due to the very high moisture loading. Less extreme conditions will be proposed and discussed. Finally some actual corrosion data will be shown that proof the validity of the simulation results.
{"title":"Over-acceleration of corrosion mechanisms during reliability testing: A method to relate biased HAST tests and application conditions for Cu wire products","authors":"J. Zaal, A. Mavinkurve, R. Rongen, J. Janssen, P. Drummen","doi":"10.1109/EPTC.2014.7028322","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028322","url":null,"abstract":"Cu bond wires in microelectronics have great potential but also provides several challenges. The acceleration factors or failure mechanisms in reliability tests are somewhat different with respect to gold wire bonding which, using unchanged but not validated test conditions and duration requirements, may lead to non-justified failures. With copper wire technology, the intermetallic compounds (IMC's) that form between the bond ball and the bond pad change in composition and corrosion behavior when compared to the gold wirebonding IMC's. When exposed to high temperatures, high moisture levels and high bias, these three different stress factors can add up to very high acceleration factors. When a product or material system fails in this test the question arises what the acceleration factor actually is and how this test compares to application conditions where temperatures may also rise significantly while high humidity levels may still be present and bias is applied. This could the operational startup phase after a long time of being in off or standby stage. The product will suddenly heat up due to the internal heat generation but moisture might still be present in the package. Combined with a high bias voltage this could lead to conditions as seen in the HAST test. To make a comparison between application and test, data was collected on the moisture properties of several molding compounds as a function of temperature. This data was then used in combination with thermal transient simulations of a product in application to compare actual moisture levels under use conditions to moisture levels in test. The simulation shows that the HAST test condition never occurs in the actual application and that the test condition is unrealistically accelerating due to the very high moisture loading. Less extreme conditions will be proposed and discussed. Finally some actual corrosion data will be shown that proof the validity of the simulation results.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028390
Y. S. Chan, J. Chew, C. H. Goh, Siang Kuan Chua, A. Yeo
We observed experimentally that the dicing tape “adhesion” increases during a mimicked die pick-up process when the die thickness decreases. This agrees apparently with the numerical results reported by B. Peng et al. in 2011. This paper describes in detail our experimental procedures and the testing results we obtained for chips ranging from 30 to 200 μm. We will report the trends we observed and subsequently, propose a model for characterizing the dicing tape adhesion using the strain energy release rate G (in [J/m2]). This may serve as a generalized criterion for the initiation of tape peeling for various chip configurations and die pick-up conditions. The current study will be important to the characterization of the “ability of being-picked” of an ultra-thin die, which remains a major reliability concern in the industry.
{"title":"Characterization of dicing tape adhesion for ultra-thin die pick-up process","authors":"Y. S. Chan, J. Chew, C. H. Goh, Siang Kuan Chua, A. Yeo","doi":"10.1109/EPTC.2014.7028390","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028390","url":null,"abstract":"We observed experimentally that the dicing tape “adhesion” increases during a mimicked die pick-up process when the die thickness decreases. This agrees apparently with the numerical results reported by B. Peng et al. in 2011. This paper describes in detail our experimental procedures and the testing results we obtained for chips ranging from 30 to 200 μm. We will report the trends we observed and subsequently, propose a model for characterizing the dicing tape adhesion using the strain energy release rate G (in [J/m2]). This may serve as a generalized criterion for the initiation of tape peeling for various chip configurations and die pick-up conditions. The current study will be important to the characterization of the “ability of being-picked” of an ultra-thin die, which remains a major reliability concern in the industry.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124362487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028383
Daniel Rhee Min Woo, How Yuan Hwang, J. Li, H. Ling, Lee Jong Bum, Zhang Songbai, Zhang Hengyun, S. L. Selvaraj, Sorono Dexter Velez, R. Singh
The SiC based high power 3 phase inverter module with double side cooling structure was developed. By applying flipchip bonding of SiC based high power DMOSFET device on DBC substrate, the source and gate bonding could be achieved. The drain interconnection was done by copper clip attach. The developed structure can provide the flat structure for both top and bottom surfaces, which can be effectively utilized for double side cooling design for high power heat dissipation. In addition to power module design with double side cooling capability, the high temperature endurable material set which can endure over 220°C device junction temperature such as high temperature interconnection, encapsulation and TIM (thermal interface materials) are developed and identified. Through the thermal, mechanical, electrical modeling & characterization and the reliability test for the developed functional test vehicles, the author could demonstrate the possibility of flip-chip based double side cooling capable high power module structure which can be utilized to high power and high temperature endurable applications for future wide band-gap device such as SiC and GaN based inverter modules.
{"title":"High power SiC inverter module packaging solutions for junction temperature over 220°C","authors":"Daniel Rhee Min Woo, How Yuan Hwang, J. Li, H. Ling, Lee Jong Bum, Zhang Songbai, Zhang Hengyun, S. L. Selvaraj, Sorono Dexter Velez, R. Singh","doi":"10.1109/EPTC.2014.7028383","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028383","url":null,"abstract":"The SiC based high power 3 phase inverter module with double side cooling structure was developed. By applying flipchip bonding of SiC based high power DMOSFET device on DBC substrate, the source and gate bonding could be achieved. The drain interconnection was done by copper clip attach. The developed structure can provide the flat structure for both top and bottom surfaces, which can be effectively utilized for double side cooling design for high power heat dissipation. In addition to power module design with double side cooling capability, the high temperature endurable material set which can endure over 220°C device junction temperature such as high temperature interconnection, encapsulation and TIM (thermal interface materials) are developed and identified. Through the thermal, mechanical, electrical modeling & characterization and the reliability test for the developed functional test vehicles, the author could demonstrate the possibility of flip-chip based double side cooling capable high power module structure which can be utilized to high power and high temperature endurable applications for future wide band-gap device such as SiC and GaN based inverter modules.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121505257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028395
G. Banwell, R. Sharpe, P. Conway, A. West
With sensors and sensor circuits becoming increasingly smaller there is the possibility of embedding such systems within products to monitor their handling and operation during the whole life cycle. The manufacturing stage of the life cycle is seen as an important stage to monitor as the defects during operation can often be attributed to manufacturing faults. The assembly of high value printed circuit boards has been identified as a process that could benefit from such sensor circuits. Vibration sensors on the boards could detect many scenarios during manufacturing, such as shock loadings and number of times a board is manually handled. In addition to this, vibrations excited in the board are known to cause cracks in solder joints [1] and also thought to cause defects during the manufacture process, although this has yet to be fully quantified. The position of the accelerometer on the board is not greatly important in detecting shock loadings and whole body motion, however, when measuring vibration of the board the position of the accelerometer greatly influences the measured amplitude depending on the relative distance to nodal lines. This paper presents experimental and theoretical methods to identify the most appropriate location for an accelerometer to be positioned.
{"title":"Evaluating the optimal location for embedded accelerometers using experimentally validated computer algorithms","authors":"G. Banwell, R. Sharpe, P. Conway, A. West","doi":"10.1109/EPTC.2014.7028395","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028395","url":null,"abstract":"With sensors and sensor circuits becoming increasingly smaller there is the possibility of embedding such systems within products to monitor their handling and operation during the whole life cycle. The manufacturing stage of the life cycle is seen as an important stage to monitor as the defects during operation can often be attributed to manufacturing faults. The assembly of high value printed circuit boards has been identified as a process that could benefit from such sensor circuits. Vibration sensors on the boards could detect many scenarios during manufacturing, such as shock loadings and number of times a board is manually handled. In addition to this, vibrations excited in the board are known to cause cracks in solder joints [1] and also thought to cause defects during the manufacture process, although this has yet to be fully quantified. The position of the accelerometer on the board is not greatly important in detecting shock loadings and whole body motion, however, when measuring vibration of the board the position of the accelerometer greatly influences the measured amplitude depending on the relative distance to nodal lines. This paper presents experimental and theoretical methods to identify the most appropriate location for an accelerometer to be positioned.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115474354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028291
Jianhui Ling, Huiyun Li, Guoqing Xu, Liying Xiong
Despite of numerous advantages of three dimensional integrated circuits (3D-ICs), their commercial success remains limited. The reason lies, in part, on the lack of physical design tools about Through-Silicon-Vias (TSVs) and 3D die stacking. In this paper, we propose a novel TSV placement method on the periphery of the dies. Based on this method, we derive a novel mathematical model to estimate 3D-IC wire-length and area with TSVs before floor-planning. We analyze the impact of TSVs on silicon area and wire-length. A case study with ISCAS benchmark circuits demonstrates that the proposed TSV placement method reduces the chip area and alleviates the reliability issues.
{"title":"Stochastic wire-length model with TSV placement on periphery area","authors":"Jianhui Ling, Huiyun Li, Guoqing Xu, Liying Xiong","doi":"10.1109/EPTC.2014.7028291","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028291","url":null,"abstract":"Despite of numerous advantages of three dimensional integrated circuits (3D-ICs), their commercial success remains limited. The reason lies, in part, on the lack of physical design tools about Through-Silicon-Vias (TSVs) and 3D die stacking. In this paper, we propose a novel TSV placement method on the periphery of the dies. Based on this method, we derive a novel mathematical model to estimate 3D-IC wire-length and area with TSVs before floor-planning. We analyze the impact of TSVs on silicon area and wire-length. A case study with ISCAS benchmark circuits demonstrates that the proposed TSV placement method reduces the chip area and alleviates the reliability issues.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131553415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028303
Lee Jong Bum, J. Li, Daniel Rhee Min Woo
In the 3D integration, multiple chip stacking structure requires large numbers of interconnections inside of each chip. 3D integration, however, encounters several fundamental technology challenges which are Cu TSV expansion, transistor degradation or open failures on Cu contamination, micro-bump stress, and so on. The reliability issues on TSV and micro-bumps are very critical at the stacked chip package as well as during the wafer level processes. Micro-bumps used in this study have 10 μm diameters on TSVs and are placed with 20 μm pitch. The diameter of TSV which used in the study is 5μm. Total 122,054 bumps on each chip which was thinned down to 50 μm are fabricated and stacked for 6 die stacking. Measured electrical resistance was well matched with calculated electrical resistance.
{"title":"Process development of multi-die stacking using 20 um pitch micro bumps on large scale dies","authors":"Lee Jong Bum, J. Li, Daniel Rhee Min Woo","doi":"10.1109/EPTC.2014.7028303","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028303","url":null,"abstract":"In the 3D integration, multiple chip stacking structure requires large numbers of interconnections inside of each chip. 3D integration, however, encounters several fundamental technology challenges which are Cu TSV expansion, transistor degradation or open failures on Cu contamination, micro-bump stress, and so on. The reliability issues on TSV and micro-bumps are very critical at the stacked chip package as well as during the wafer level processes. Micro-bumps used in this study have 10 μm diameters on TSVs and are placed with 20 μm pitch. The diameter of TSV which used in the study is 5μm. Total 122,054 bumps on each chip which was thinned down to 50 μm are fabricated and stacked for 6 die stacking. Measured electrical resistance was well matched with calculated electrical resistance.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131895072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028318
T. Tsunoda, K. Shi, I. Shohji, Kotaro Matsu, Yasuhiro Taguchi
For thermal conversion parts of electrical equipment which are required high corrosion resistance, stainless steel is often used. The joining of such materials is generally conducted with brazing with Ni-based filler. Since Ni is a rare and high-cost material, the substitute filler material which is low-Ni or Ni-free is expected to be developed. Fe-based filler has been developed as one candidate. In this study, joint strength and the microstructure of stainless steel type 304 brazed joint with Fe-based filler were investigated. As the results, it was clarified that shear strength of the joint with Fe-based filler is the almost same level as that with conventional Ni-based filler. Moreover, the effect of joint clearance on the joint strength and the microstructure was also investigated. When joint clearance is more than 50 μm, the final solidified area which consists of Fe-Cr-Ni-Si phases and P-rich phases forms in the center of the brazed joint. The formation of P-rich phases causes the joint strength reduction.
{"title":"Joint strength and microstructures of brazed joints of stainless steel with Fe-based filler","authors":"T. Tsunoda, K. Shi, I. Shohji, Kotaro Matsu, Yasuhiro Taguchi","doi":"10.1109/EPTC.2014.7028318","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028318","url":null,"abstract":"For thermal conversion parts of electrical equipment which are required high corrosion resistance, stainless steel is often used. The joining of such materials is generally conducted with brazing with Ni-based filler. Since Ni is a rare and high-cost material, the substitute filler material which is low-Ni or Ni-free is expected to be developed. Fe-based filler has been developed as one candidate. In this study, joint strength and the microstructure of stainless steel type 304 brazed joint with Fe-based filler were investigated. As the results, it was clarified that shear strength of the joint with Fe-based filler is the almost same level as that with conventional Ni-based filler. Moreover, the effect of joint clearance on the joint strength and the microstructure was also investigated. When joint clearance is more than 50 μm, the final solidified area which consists of Fe-Cr-Ni-Si phases and P-rich phases forms in the center of the brazed joint. The formation of P-rich phases causes the joint strength reduction.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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