Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028307
F. Yen, L. Hung, N. Kao, D. Jiang
The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and bump pitch, especially when Molded Underfill (MUF) is used during transfer molding process. There is one important challenge that faced severe air void entrapment under the die (air void concentrate among bumps region). Generally, the experiments involving a lot of DOE matrixes which spend a lot of time and materials (dummy die, substrate, mold compound...etc.) to solve this air void issue. As above reasons, the moldflow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of MUF FCCSP with different bump structure or substrate structure design, which can reduce development cycle time before mass production. In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. There are two molding flow factors will be presented in this paper. One is MUF FCCSP with different stand-off height construction (control different bump height dimension) which performs significant difference molding melt-front position. And another is substrate solder mask with different pattern design (solder mask w/ all open or finger like pattern design) which molding compound through over on solder mask pattern (solder mask with open region as 10um depth structure) and performs different melt-front pattern. From this study, we can conclude some results for improvement molding performance of MUF FCCSP during transfer molding process. The MUF FCCSP with the 50um stand-off height structure performs low air void risk due to mold compound could easily flow under die region with more flow space. In addition, mold compound also performs well melt-front flow that the substrate solder mask with all open structure design can get more 10um flow space under die region. Finally, the simulation results are aligned with experiments and it can be used to predict void risk.
{"title":"MoldFlow simulation study on void risk prediction for FCCSP with molded underfill technology","authors":"F. Yen, L. Hung, N. Kao, D. Jiang","doi":"10.1109/EPTC.2014.7028307","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028307","url":null,"abstract":"The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and bump pitch, especially when Molded Underfill (MUF) is used during transfer molding process. There is one important challenge that faced severe air void entrapment under the die (air void concentrate among bumps region). Generally, the experiments involving a lot of DOE matrixes which spend a lot of time and materials (dummy die, substrate, mold compound...etc.) to solve this air void issue. As above reasons, the moldflow simulation can be used to apply molding parameters to find out optimum solutions for air void risk free of MUF FCCSP with different bump structure or substrate structure design, which can reduce development cycle time before mass production. In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. There are two molding flow factors will be presented in this paper. One is MUF FCCSP with different stand-off height construction (control different bump height dimension) which performs significant difference molding melt-front position. And another is substrate solder mask with different pattern design (solder mask w/ all open or finger like pattern design) which molding compound through over on solder mask pattern (solder mask with open region as 10um depth structure) and performs different melt-front pattern. From this study, we can conclude some results for improvement molding performance of MUF FCCSP during transfer molding process. The MUF FCCSP with the 50um stand-off height structure performs low air void risk due to mold compound could easily flow under die region with more flow space. In addition, mold compound also performs well melt-front flow that the substrate solder mask with all open structure design can get more 10um flow space under die region. Finally, the simulation results are aligned with experiments and it can be used to predict void risk.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128456353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028403
L. Tsai, B. Wang, A. Shorey, Alvin Lee, Jay Su, Baron Huang, Wen-Wei Shen, Hsiang-Hung Chang, C. Chien
Interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and the substrate [1]. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE as well as the ability to provide a low cost solution [2]. In this investigation, another cost reduction concept of through glass via (TGV) wafer processing is being studied. By leveraging current semiconductor equipment and know-how, we bond TGV wafers onto glass carriers as shown in Figure 1, the TGV wafer thickness is directly 100um and center diameter (CD) of through glass via is 30 μm. This approach provides a method to temporarily bond these TGV wafers to glass carriers enabling handling through processes such as via fill and surface metallization. The ability to form glass at the target 100 um thickness and provide through holes and thus avoid backgrinding processes provides substantial opportunity to save costs and avoid yield loss. The TGV interposer wafer is bonded with a glass carrier by a polymeric bonding material. The bonding material must be compatible with surface materials as well as good step coverage to void-free bonding [3]. Most importantly, the bonding material shall remain stable and good resistance in harsh thermal and chemical environments to protect interposer at all time [4]. The thermal stability and characteristics of the bonding material used in this study as shown in Figure 2, is important to maintain low warp. Finally, the treated glass carrier is released from the bonding material by a laser de-bond method. The laser debond method is known to have several benefits such as (a) high throughput: possible to de-bond one pair within 30s (b). low temperature: UV range wavelength does not generate heat in the de-bonding process (c). zero force de-bon ding: after laser scanning, the carrier can be lifted off directly (d). process efficiency: laser release layer is a spin-on material, so only a spin bowl is required. Here we use 308 nm laser and this wavelength also has the benefit with less impact to the device.
{"title":"Laminating thin glass onto glass carrier to eliminate grinding and bonding process for glass interposer","authors":"L. Tsai, B. Wang, A. Shorey, Alvin Lee, Jay Su, Baron Huang, Wen-Wei Shen, Hsiang-Hung Chang, C. Chien","doi":"10.1109/EPTC.2014.7028403","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028403","url":null,"abstract":"Interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and the substrate [1]. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE as well as the ability to provide a low cost solution [2]. In this investigation, another cost reduction concept of through glass via (TGV) wafer processing is being studied. By leveraging current semiconductor equipment and know-how, we bond TGV wafers onto glass carriers as shown in Figure 1, the TGV wafer thickness is directly 100um and center diameter (CD) of through glass via is 30 μm. This approach provides a method to temporarily bond these TGV wafers to glass carriers enabling handling through processes such as via fill and surface metallization. The ability to form glass at the target 100 um thickness and provide through holes and thus avoid backgrinding processes provides substantial opportunity to save costs and avoid yield loss. The TGV interposer wafer is bonded with a glass carrier by a polymeric bonding material. The bonding material must be compatible with surface materials as well as good step coverage to void-free bonding [3]. Most importantly, the bonding material shall remain stable and good resistance in harsh thermal and chemical environments to protect interposer at all time [4]. The thermal stability and characteristics of the bonding material used in this study as shown in Figure 2, is important to maintain low warp. Finally, the treated glass carrier is released from the bonding material by a laser de-bond method. The laser debond method is known to have several benefits such as (a) high throughput: possible to de-bond one pair within 30s (b). low temperature: UV range wavelength does not generate heat in the de-bonding process (c). zero force de-bon ding: after laser scanning, the carrier can be lifted off directly (d). process efficiency: laser release layer is a spin-on material, so only a spin bowl is required. Here we use 308 nm laser and this wavelength also has the benefit with less impact to the device.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"106 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028263
A. A. Aziz, F. Danaher, A. Hashim
Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment.
{"title":"A robust chip capacitor for video band width in RF power amplifiers","authors":"A. A. Aziz, F. Danaher, A. Hashim","doi":"10.1109/EPTC.2014.7028263","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028263","url":null,"abstract":"Year 2013 demonstrated a considerable manufacturing challenges to enable the roll out of RF 4G systems. The popularity of utilizing the High chip capacitor for increased VBW tested the resources for both RF assembly in Freescale and the chip manufacturer and subcontractors associated with chip capacitor production. It was demonstrated that the existing chip capacitor device, while designed well, required several enhancements to increase final product assembly quality while reducing the significant CLC footprint. The initial chip capacitor design utilized a standardized ceramic build process needed plating format which in the long run contributed to chip shorting at final assembly due to the existing chip capacitor prone to get solder short and supplier not able to provide consistent solder pattern. To remedy this design, the chip cap processing was radically redefined to produce a chip cap with reverse electrodes and an in-house solder foil process. To date, the new capacitor has been introduced in over a dozen RF products and is being utilized in significant run rates to produce the higher margins needed in this competitive environment.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"181 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114098862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028414
R. Islam, M. Matin, R. Mahbub, M. A. Hakim, M. F. Islam
In this pioneering work, lanthanum (La)/tantalum (Ta) co-doped Ba(1-3x)La2xTi(1-5y)Ta4yO3 ferroelectric functional ceramic was synthesized to obtain improved dielectric and polarization properties. The calcinated pressed sample was subjected to double stage sintering at a maximum temperature of 1375°C for 2, 4 and 6 h. The presence of tetragonal phase was confirmed in the perovskite structure using X-ray diffractometry. The microstructure has been studied using FESEM. The influence of sintering time on grain growth was found to be significant. It was found that La doping has significant effect on tilting of the perovskite structure. On the other hand, Ta is responsible for the polarization and control of the grain growth. In addition, double doping resulted in higher dielectric constant and low dielectric loss factor, which was measured using impedance analyzer. This research thus develops new Ba(1-3x)La2xTi(1-5y)Ta4yO3 ferroelectric materials with improved dielectric and polarization properties that can find prospective applications in FeRAM, capacitor and transducer in particular.
{"title":"Novel smart ferroelectric functional material for application in transducers","authors":"R. Islam, M. Matin, R. Mahbub, M. A. Hakim, M. F. Islam","doi":"10.1109/EPTC.2014.7028414","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028414","url":null,"abstract":"In this pioneering work, lanthanum (La)/tantalum (Ta) co-doped Ba(1-3x)La2xTi(1-5y)Ta4yO3 ferroelectric functional ceramic was synthesized to obtain improved dielectric and polarization properties. The calcinated pressed sample was subjected to double stage sintering at a maximum temperature of 1375°C for 2, 4 and 6 h. The presence of tetragonal phase was confirmed in the perovskite structure using X-ray diffractometry. The microstructure has been studied using FESEM. The influence of sintering time on grain growth was found to be significant. It was found that La doping has significant effect on tilting of the perovskite structure. On the other hand, Ta is responsible for the polarization and control of the grain growth. In addition, double doping resulted in higher dielectric constant and low dielectric loss factor, which was measured using impedance analyzer. This research thus develops new Ba(1-3x)La2xTi(1-5y)Ta4yO3 ferroelectric materials with improved dielectric and polarization properties that can find prospective applications in FeRAM, capacitor and transducer in particular.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115926898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028299
M. Ding, C. Kantak, V. S. Rao, M. K. Park, C. Wong
In recent years, advanced incorporation of complementary metal oxide semiconductor (CMOS) biosensor chips with sensory microarrays has gained tremendous attention. In this paper, we investigated a maskless approach to microfluidic channel fabrication that integrates seamlessly with CMOS biosensor chip packaging. The microfluidic channels were formed via precisely controlled dispensing of adhesive to define microfluidic dam structures. This was followed by encapsulation of the microfluidic dam with a lid, thereby producing an impervious seal. Four types of commercial adhesives used in medical/implantable devices were evaluated in this study; a silicone-based adhesive, an ultraviolet curable epoxy, an ultraviolet curing acrylate adhesive, and a thermal curing epoxy. The adhesives were evaluated based on the performance criteria such as: (i) critical dimension (CD) of microfluidic channels, (ii) minimum microfluidic dam height, (iii) biocompatibility, and (iv) bond strength of the adhesive between CMOS substrate film to the lid material. The test vehicles comprising of ITO glass lid material, SiN substrate material and various evaluated adhesives, were subjected to burst pressure leak test. From the results obtained, Dow Corning® 3140 silicone-based adhesive has the best performance as a suitable adhesive for microfluidic dam structure formation. Lastly, a seamless approach to integrating electronic and microfluidic packaging through the use of controlled adhesive dispensing and a pick and place assembly tool was demonstrated with the use of Dow Corning® 3140 adhesive for microfluidic biological applications.
{"title":"Integrated electronic and microfluidic packaging for CMOS biosensor chip","authors":"M. Ding, C. Kantak, V. S. Rao, M. K. Park, C. Wong","doi":"10.1109/EPTC.2014.7028299","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028299","url":null,"abstract":"In recent years, advanced incorporation of complementary metal oxide semiconductor (CMOS) biosensor chips with sensory microarrays has gained tremendous attention. In this paper, we investigated a maskless approach to microfluidic channel fabrication that integrates seamlessly with CMOS biosensor chip packaging. The microfluidic channels were formed via precisely controlled dispensing of adhesive to define microfluidic dam structures. This was followed by encapsulation of the microfluidic dam with a lid, thereby producing an impervious seal. Four types of commercial adhesives used in medical/implantable devices were evaluated in this study; a silicone-based adhesive, an ultraviolet curable epoxy, an ultraviolet curing acrylate adhesive, and a thermal curing epoxy. The adhesives were evaluated based on the performance criteria such as: (i) critical dimension (CD) of microfluidic channels, (ii) minimum microfluidic dam height, (iii) biocompatibility, and (iv) bond strength of the adhesive between CMOS substrate film to the lid material. The test vehicles comprising of ITO glass lid material, SiN substrate material and various evaluated adhesives, were subjected to burst pressure leak test. From the results obtained, Dow Corning® 3140 silicone-based adhesive has the best performance as a suitable adhesive for microfluidic dam structure formation. Lastly, a seamless approach to integrating electronic and microfluidic packaging through the use of controlled adhesive dispensing and a pick and place assembly tool was demonstrated with the use of Dow Corning® 3140 adhesive for microfluidic biological applications.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"19 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120837600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028394
Songbai Zhang, Yaojiang Zhang, W. M. Kwek, L. Goi, A. Trigg, L. Tang
Recent development of Electron Backscattering Diffraction (EBSD) technique has advanced to allow users to perform Transmission Kikuchi diffraction (TKD), and also known as transmission-EBSD (t-EBSD) with the existing conventional EBSD detector, and field emission scanning electron microscope (FESEM). More importantly, this technique has been known for the significant improvement in spatial resolution. In this paper, this technique has been employed to characterize a high topography surface Aluminum sample containing submicron or smaller grain sizes, which is a limitation to the conventional EBSD method because a conventional EBSD method requires relative smooth and flat surfaces. The objective of this paper is to illustrate the successful employment of t-EBSD technique, to obtain the mean grain size of Aluminum prepared by Physical Vapour Deposition (PVD), as well as to determine percentage of grains orientation grown in <;111> parallel to the growth direction to the silicon substrate or simply the normal direction (ND) as specify in during the ESBD analysis run. This paper will account on how the sample was prepared by means of FIB to achieve and electron transparent TEM foil. Results has shown that 81% of the desired <;111> orientation parallel to the ND direction (i.e. <;111>//ND) and a mean grain size of 0.317um were determined, with more than 50% of the area mapped contain grains equivalent diameter less than submicron size. Therefore, t-EBSD is a relatively effective application towards this study because this does not compromise on the spatial resolution less than submicron scales.
{"title":"Application of transmission EBSD on high topography surface Aluminum thin film","authors":"Songbai Zhang, Yaojiang Zhang, W. M. Kwek, L. Goi, A. Trigg, L. Tang","doi":"10.1109/EPTC.2014.7028394","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028394","url":null,"abstract":"Recent development of Electron Backscattering Diffraction (EBSD) technique has advanced to allow users to perform Transmission Kikuchi diffraction (TKD), and also known as transmission-EBSD (t-EBSD) with the existing conventional EBSD detector, and field emission scanning electron microscope (FESEM). More importantly, this technique has been known for the significant improvement in spatial resolution. In this paper, this technique has been employed to characterize a high topography surface Aluminum sample containing submicron or smaller grain sizes, which is a limitation to the conventional EBSD method because a conventional EBSD method requires relative smooth and flat surfaces. The objective of this paper is to illustrate the successful employment of t-EBSD technique, to obtain the mean grain size of Aluminum prepared by Physical Vapour Deposition (PVD), as well as to determine percentage of grains orientation grown in <;111> parallel to the growth direction to the silicon substrate or simply the normal direction (ND) as specify in during the ESBD analysis run. This paper will account on how the sample was prepared by means of FIB to achieve and electron transparent TEM foil. Results has shown that 81% of the desired <;111> orientation parallel to the ND direction (i.e. <;111>//ND) and a mean grain size of 0.317um were determined, with more than 50% of the area mapped contain grains equivalent diameter less than submicron size. Therefore, t-EBSD is a relatively effective application towards this study because this does not compromise on the spatial resolution less than submicron scales.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117342041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028374
Pan Wei Chih, Baquiran Joseph Aaron Mesa, X. Hong, Goh Min Hao
Zn-Al based alloys are good candidates in the proposal of alternative lead-free solder alloys for Silicon (Si) die attach in high-temperature applications because of its proper melting range and excellent thermal and electrical properties. There are limited studies on the feasibility of Zn based alloys in die attachment application and out of these studies, many did not include reliability test. In this report, the reliability of Si die attachment on Cu and Ni leadframes using Zn-Al-Ge based solder was investigated through high temperature storage (HTS) test. The die attachment process capability was verified using visual inspection, CSAM, and microscopic inspection on cross-sectioned samples. Die attached samples subsequently underwent HTS at 200 oC for up to 500 hours. SEM/EDX analysis was then carried out on cross-sectioned die attached samples being exposed to various storage durations to inspect for any failures and to identify intermetallic layers that were formed during the HTS. Results showed that good temperature tolerance at 500 hours was observed for soldering on Ni leadframe. However, several failures were seen in die attachment on Cu leadframe as early as 25 hours and up to 500 hours. This paper covers extensive analyses to understand these failure mechanisms applicable in this die attachment configuration.
{"title":"Application and high temperature storage test on Zn-Al-Ge high temperature solder for die attach","authors":"Pan Wei Chih, Baquiran Joseph Aaron Mesa, X. Hong, Goh Min Hao","doi":"10.1109/EPTC.2014.7028374","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028374","url":null,"abstract":"Zn-Al based alloys are good candidates in the proposal of alternative lead-free solder alloys for Silicon (Si) die attach in high-temperature applications because of its proper melting range and excellent thermal and electrical properties. There are limited studies on the feasibility of Zn based alloys in die attachment application and out of these studies, many did not include reliability test. In this report, the reliability of Si die attachment on Cu and Ni leadframes using Zn-Al-Ge based solder was investigated through high temperature storage (HTS) test. The die attachment process capability was verified using visual inspection, CSAM, and microscopic inspection on cross-sectioned samples. Die attached samples subsequently underwent HTS at 200 oC for up to 500 hours. SEM/EDX analysis was then carried out on cross-sectioned die attached samples being exposed to various storage durations to inspect for any failures and to identify intermetallic layers that were formed during the HTS. Results showed that good temperature tolerance at 500 hours was observed for soldering on Ni leadframe. However, several failures were seen in die attachment on Cu leadframe as early as 25 hours and up to 500 hours. This paper covers extensive analyses to understand these failure mechanisms applicable in this die attachment configuration.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122024125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028262
J. Xie, S. Wickramanayaka
PVD AlN film deposition rate, within wafer stress uniformity, roughness and crystal orientation were studied on different process pressure. It was found that AlN deposition rate decreased with pressure increased. The decreasing rate dramatically increased when process pressure more than 12mT. Film stress tends to be more tensile with increased pressure at wafer edge and becomes more compressive when process pressure higher than 14mT. Within wafer film stress range can be reduced from ~600MPa to ~300Mpa when process pressure increased from 7mT to 14mT. Film becomes more rough with process pressure increased. Roughness RMS increased from 2.605~2.825nm to 3.131~3.692nm when pressure increased from 7mT to 14mT.
{"title":"Effect of process pressure on PVD AlN thin film","authors":"J. Xie, S. Wickramanayaka","doi":"10.1109/EPTC.2014.7028262","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028262","url":null,"abstract":"PVD AlN film deposition rate, within wafer stress uniformity, roughness and crystal orientation were studied on different process pressure. It was found that AlN deposition rate decreased with pressure increased. The decreasing rate dramatically increased when process pressure more than 12mT. Film stress tends to be more tensile with increased pressure at wafer edge and becomes more compressive when process pressure higher than 14mT. Within wafer film stress range can be reduced from ~600MPa to ~300Mpa when process pressure increased from 7mT to 14mT. Film becomes more rough with process pressure increased. Roughness RMS increased from 2.605~2.825nm to 3.131~3.692nm when pressure increased from 7mT to 14mT.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129667329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028297
N. Hiyoshi, M. Yamashita, H. Hokazono
This paper discusses the effect of additive elements on crack propagation behavior for Sn-Bi solders at high temperatures. Sn-Bi solders are lower melting point materials, so that it is useful for low temperature soldering. Crack initiation and propagation behavior of three kinds of Sn-Bi solders were observed in this study. There were effects of additive elements Ag, Cu, Ni and Ge on crack propagation rate although there was no effect on crack initiation. The crack propagation of Sn57.5Bi0.5AgCuNiGe solder seems to have a slower rate than Sn58Bi and Sn57.5Bi0.5Ag solders. The J-integral range parameter evaluates the crack propagation rate independent of the additive elements at high temperatures.
{"title":"Effect of additive elements on crack propagation behavior for Sn-Bi solders at high temperatures","authors":"N. Hiyoshi, M. Yamashita, H. Hokazono","doi":"10.1109/EPTC.2014.7028297","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028297","url":null,"abstract":"This paper discusses the effect of additive elements on crack propagation behavior for Sn-Bi solders at high temperatures. Sn-Bi solders are lower melting point materials, so that it is useful for low temperature soldering. Crack initiation and propagation behavior of three kinds of Sn-Bi solders were observed in this study. There were effects of additive elements Ag, Cu, Ni and Ge on crack propagation rate although there was no effect on crack initiation. The crack propagation of Sn57.5Bi0.5AgCuNiGe solder seems to have a slower rate than Sn58Bi and Sn57.5Bi0.5Ag solders. The J-integral range parameter evaluates the crack propagation rate independent of the additive elements at high temperatures.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129798839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028391
N. Watanabe, S. Nemoto, K. Kikuchi, M. Aoyagi, Tomoaki Tokuhisa, Takuo Owada, Masaru Kato
We conducted a basic evaluation of Au micro-bumps formed by cyanide-free electroless Au plating. The Au micro-bump diameter was approximately 10 μm. Bump height measurement, bump shear testing, and X-ray photoelectron spectroscopy of the Au surface were performed after Au micro-bump formation. Scanning ion microscope observation of the bonding interface, chip shear testing, four-terminal measurement, and daisy chain measurement were performed after flip-chip bonding. The results show that the Au micro-bumps have good mechanical and electrical properties.
{"title":"Basic evaluation of Au micro-bumps formed by cyanide-free electroless Au plating process","authors":"N. Watanabe, S. Nemoto, K. Kikuchi, M. Aoyagi, Tomoaki Tokuhisa, Takuo Owada, Masaru Kato","doi":"10.1109/EPTC.2014.7028391","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028391","url":null,"abstract":"We conducted a basic evaluation of Au micro-bumps formed by cyanide-free electroless Au plating. The Au micro-bump diameter was approximately 10 μm. Bump height measurement, bump shear testing, and X-ray photoelectron spectroscopy of the Au surface were performed after Au micro-bump formation. Scanning ion microscope observation of the bonding interface, chip shear testing, four-terminal measurement, and daisy chain measurement were performed after flip-chip bonding. The results show that the Au micro-bumps have good mechanical and electrical properties.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128752724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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