Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028257
Zhang Ruifen, Yap Kong Tat, Yam Lip Huei, R. Dexter
Void of solder joint can be considered to be one of the main defects in electronic assembly. The existence of void will influence not only the reliability of solder joint, but also the electrical, mechanical and thermal properties of solder joint. X-ray is the traditional method to analyze solder void. The inspection criteria to void are subjective, different customers have different requirements to the void performance of the product. Although the theory of forming void is known, different cases need different actions to get optimized void performance. The main objective of this paper is to study how much the application process can impact the void performance independently. The process parameters investigated in this study mainly include printing parameter effect, reflow profile effect and heating mechanism effect on void formation of solder joint.
{"title":"How to improve void performance in wafer bumping","authors":"Zhang Ruifen, Yap Kong Tat, Yam Lip Huei, R. Dexter","doi":"10.1109/EPTC.2014.7028257","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028257","url":null,"abstract":"Void of solder joint can be considered to be one of the main defects in electronic assembly. The existence of void will influence not only the reliability of solder joint, but also the electrical, mechanical and thermal properties of solder joint. X-ray is the traditional method to analyze solder void. The inspection criteria to void are subjective, different customers have different requirements to the void performance of the product. Although the theory of forming void is known, different cases need different actions to get optimized void performance. The main objective of this paper is to study how much the application process can impact the void performance independently. The process parameters investigated in this study mainly include printing parameter effect, reflow profile effect and heating mechanism effect on void formation of solder joint.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127945660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028324
K. Zoschke, T. Fischer, H. Oppermann, K. Lang
This manuscript describes process scenarios for advanced wafer level packaging which are enabled by temporary bonding and de-bonding capabilities but exceeding the skills of classical thin wafer handling approaches. An adhesive bonding and laser assisted de-bonding technology which is a proven platform for TSV wafer processing is introduced to be a versatile basis for these different kinds of handling scenarios. By adapting this base technology, single devices can be temporary fixed at carrier wafers, subsequently processed in parallel and finally release from the carrier wafers. Furthermore, processes for thin IC wafers can be adapted to end up with singulated thin ICs equipped with temporary bonded carrier dice on their backside which act as mechanical support during a standard pick&place and reflow process scheme. Another process scenario allows the custom specific fabrication of cap structures at wafer level and subsequent transfer bonding from a donor wafer to a target wafer. A further scenario allows the fabrication of thin film multilayer structures at carrier wafers and their subsequent release from these carrier wafers. The manuscript firstly describes the general process flow for adhesive bonding and de-bonding by laser release technology. Secondly, technical back ground and motivation as well as technological solutions for the above mentioned process scenarios are presented and discussed in detail. Special focus is drawn on the corresponding temporary handling processes which are based on adhesive bonding and laser assisted de-bonding. All described processes are proven at 200 mm wafer scale.
{"title":"Temporary handling technology for advanced wafer level packaging applications based on adhesive bonding and laser assisted de-bonding","authors":"K. Zoschke, T. Fischer, H. Oppermann, K. Lang","doi":"10.1109/EPTC.2014.7028324","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028324","url":null,"abstract":"This manuscript describes process scenarios for advanced wafer level packaging which are enabled by temporary bonding and de-bonding capabilities but exceeding the skills of classical thin wafer handling approaches. An adhesive bonding and laser assisted de-bonding technology which is a proven platform for TSV wafer processing is introduced to be a versatile basis for these different kinds of handling scenarios. By adapting this base technology, single devices can be temporary fixed at carrier wafers, subsequently processed in parallel and finally release from the carrier wafers. Furthermore, processes for thin IC wafers can be adapted to end up with singulated thin ICs equipped with temporary bonded carrier dice on their backside which act as mechanical support during a standard pick&place and reflow process scheme. Another process scenario allows the custom specific fabrication of cap structures at wafer level and subsequent transfer bonding from a donor wafer to a target wafer. A further scenario allows the fabrication of thin film multilayer structures at carrier wafers and their subsequent release from these carrier wafers. The manuscript firstly describes the general process flow for adhesive bonding and de-bonding by laser release technology. Secondly, technical back ground and motivation as well as technological solutions for the above mentioned process scenarios are presented and discussed in detail. Special focus is drawn on the corresponding temporary handling processes which are based on adhesive bonding and laser assisted de-bonding. All described processes are proven at 200 mm wafer scale.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121085415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028268
Kang Chen, Kok Hwa Lim, Kenneth Seah, Yaojian Lin, S. Yoon
The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a significant amount of capital. Since 200mm volumes will most likely decline within the next 5 years, it is difficult to justify the use of capital when the depreciation term is longer than the anticipated life cycle of the product. This paper introduces a new encapsulated WLCSP product (eWLCSP™) and innovative manufacturing known as FlexLineTM. The new product has a thin protective coating applied to all exposed silicon surfaces on the die. The applied coating protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The manufacturing process leverages existing high volume manufacturing methods with exceptionally high process yields. In this process the silicon wafer is diced prior to the wafer level packaging process. The dice are then reconstituted into a new wafer form with adequate distance between the die to allow for a thin layer of protective coating to remain after final singulation. Standard methods are used to apply dielectrics, thin film metals, and solder bumps. The resulting structure is identical to a conventional WLCSP product with the addition of the protective sidewall coating. This paper discusses the key attributes of the new package as well as the manufacturing process used to create it. Reliability data will be presented and compared to conventional WLCSP products and improvements in package reliability and performance will be discussed and compared to conventional WLCSP.
{"title":"Innovative wafer level package manufacturing with FlexLineTM","authors":"Kang Chen, Kok Hwa Lim, Kenneth Seah, Yaojian Lin, S. Yoon","doi":"10.1109/EPTC.2014.7028268","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028268","url":null,"abstract":"The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a significant amount of capital. Since 200mm volumes will most likely decline within the next 5 years, it is difficult to justify the use of capital when the depreciation term is longer than the anticipated life cycle of the product. This paper introduces a new encapsulated WLCSP product (eWLCSP™) and innovative manufacturing known as FlexLineTM. The new product has a thin protective coating applied to all exposed silicon surfaces on the die. The applied coating protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The manufacturing process leverages existing high volume manufacturing methods with exceptionally high process yields. In this process the silicon wafer is diced prior to the wafer level packaging process. The dice are then reconstituted into a new wafer form with adequate distance between the die to allow for a thin layer of protective coating to remain after final singulation. Standard methods are used to apply dielectrics, thin film metals, and solder bumps. The resulting structure is identical to a conventional WLCSP product with the addition of the protective sidewall coating. This paper discusses the key attributes of the new package as well as the manufacturing process used to create it. Reliability data will be presented and compared to conventional WLCSP products and improvements in package reliability and performance will be discussed and compared to conventional WLCSP.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126794063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028292
Bobe Lee, S. Chou
Delamination on the interface between mold compound to die, die paddle and inner leads study has been on-going for quite some time. This is a chronicle defect which will result in electrical continuity failure if delamination penetrates into the interface of mold compound to die surface and mold compound to inner leads e.g., delamination on inner leads or die surface to cause wire broken after thermal stress. To resolve delamination, better materials are needed such as Lead frame, die attach and mold compound. Other than that, a process optimization is also a must to achieve delamination free result. The paper portrays the phenomenon of how delamination occurred after improving the BOM e.g., less water absorption and higher adhesion mold compound. During qualification stage, no delamination occurred after thermal stress. But, on mass volume production run, the delamination occurs on inner leads by sampling check. Four “M” Men, Material, Method and Machines are thoroughly checked and compared with its qualification built and mass production run. No difference or conclusion can be observed and made. But, the delamination was there though no finding/difference was observed. However, one conclusion can be made is qualification is small volume but mass confirmation run is large volume. Based on the assumption, Delamination comparison between small volume VS. large volume was conducted to check the difference. Then, the root cause as die attach outgassing to cause contamination on package is observed. The contamination is later turn into delamination after Thermal.
{"title":"Inter-connecting process investigation to resolve delamination","authors":"Bobe Lee, S. Chou","doi":"10.1109/EPTC.2014.7028292","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028292","url":null,"abstract":"Delamination on the interface between mold compound to die, die paddle and inner leads study has been on-going for quite some time. This is a chronicle defect which will result in electrical continuity failure if delamination penetrates into the interface of mold compound to die surface and mold compound to inner leads e.g., delamination on inner leads or die surface to cause wire broken after thermal stress. To resolve delamination, better materials are needed such as Lead frame, die attach and mold compound. Other than that, a process optimization is also a must to achieve delamination free result. The paper portrays the phenomenon of how delamination occurred after improving the BOM e.g., less water absorption and higher adhesion mold compound. During qualification stage, no delamination occurred after thermal stress. But, on mass volume production run, the delamination occurs on inner leads by sampling check. Four “M” Men, Material, Method and Machines are thoroughly checked and compared with its qualification built and mass production run. No difference or conclusion can be observed and made. But, the delamination was there though no finding/difference was observed. However, one conclusion can be made is qualification is small volume but mass confirmation run is large volume. Based on the assumption, Delamination comparison between small volume VS. large volume was conducted to check the difference. Then, the root cause as die attach outgassing to cause contamination on package is observed. The contamination is later turn into delamination after Thermal.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127492714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028401
K. Zeng, A. Nangia
It has been widely reported in the literature that for packages that are required to pass thermal cycling test, the SnAgCu solder joints should have high Ag content. In this study, thermal cycling performance of a wafer level chip-scale package was evaluated with different combinations of high Ag solder (Sn3.9Ag0.6Cu) and low Ag solder (Sn1.2Ag0.5Cu) with thick and thin PCB. It was found that with the low Ag solder ball the package mounted on a thin PCB had better performance. Metallurgical analysis of solder joints, mechanical modeling of the package mounted on boards, and coplanarity measurement of the printed circuit boards were performed to understand the results. Because of the CTE mismatch between PCB and die, PCB warpage resulted in high tensile stress in solder joints in the central area, causing cracking of re-distribution layer Cu. The softer solder alloy Sn1.2Ag0.5Cu helped reduce the stress, leading to better performance in thermal cycling test.
{"title":"Thermal cycling reliability of SnAgCu solder joints in WLCSP","authors":"K. Zeng, A. Nangia","doi":"10.1109/EPTC.2014.7028401","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028401","url":null,"abstract":"It has been widely reported in the literature that for packages that are required to pass thermal cycling test, the SnAgCu solder joints should have high Ag content. In this study, thermal cycling performance of a wafer level chip-scale package was evaluated with different combinations of high Ag solder (Sn3.9Ag0.6Cu) and low Ag solder (Sn1.2Ag0.5Cu) with thick and thin PCB. It was found that with the low Ag solder ball the package mounted on a thin PCB had better performance. Metallurgical analysis of solder joints, mechanical modeling of the package mounted on boards, and coplanarity measurement of the printed circuit boards were performed to understand the results. Because of the CTE mismatch between PCB and die, PCB warpage resulted in high tensile stress in solder joints in the central area, causing cracking of re-distribution layer Cu. The softer solder alloy Sn1.2Ag0.5Cu helped reduce the stress, leading to better performance in thermal cycling test.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127019916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028420
Jie Wu, J. Yang, O. Yauw, I. Qin, T. Rockey, B. Chylak
With competitive price and superior electrical/thermal conductivity and mechanical properties, more and more IC package industries have adopted copper (Cu) and palladium coated copper (PdCu) wires as the alternative to gold (Au) wire in the past decade. However, the high hardness and the excessive ultrasonic energy and bonding motions required during bonding of Cu wire limit its usage in areas such as memory packages and sensitive devices that are prone to damages on the pads and under-layer dielectrics. Silver (Ag) and Ag-alloy wires emerge as other alternatives since they have similar properties like wire hardness, elongation and breaking load at room temperature as Au wire while having a more competitive price. Process capability of ultra-fine (0.6mil) Ag-alloy wire, including free air balls (FAB) and bonding capability on aluminum (Al) die pads were first investigated. Factors affecting the FAB performance were studied and optimum settings were recommended. Comparison of bonding responses between Au, PdCu and Ag-alloy wires on challenging scenarios, such as overhang dies and die-to-die bonding, were also included in the study. Benchmarked Au process, Ag-alloy wire possesses great portability and wide first bond process window. Ag-alloy wire also demonstrates good bonding capability and loop shape control on challenging applications, such as overhang die and long die-to-die applications. However, further optimization of Ag-alloy process is still necessary to overcome its constrains, such as higher hardness and higher energy required during bonding of Ag-alloy wire.
{"title":"Study of 0.6mil silver alloy wire in challenging bonding processes","authors":"Jie Wu, J. Yang, O. Yauw, I. Qin, T. Rockey, B. Chylak","doi":"10.1109/EPTC.2014.7028420","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028420","url":null,"abstract":"With competitive price and superior electrical/thermal conductivity and mechanical properties, more and more IC package industries have adopted copper (Cu) and palladium coated copper (PdCu) wires as the alternative to gold (Au) wire in the past decade. However, the high hardness and the excessive ultrasonic energy and bonding motions required during bonding of Cu wire limit its usage in areas such as memory packages and sensitive devices that are prone to damages on the pads and under-layer dielectrics. Silver (Ag) and Ag-alloy wires emerge as other alternatives since they have similar properties like wire hardness, elongation and breaking load at room temperature as Au wire while having a more competitive price. Process capability of ultra-fine (0.6mil) Ag-alloy wire, including free air balls (FAB) and bonding capability on aluminum (Al) die pads were first investigated. Factors affecting the FAB performance were studied and optimum settings were recommended. Comparison of bonding responses between Au, PdCu and Ag-alloy wires on challenging scenarios, such as overhang dies and die-to-die bonding, were also included in the study. Benchmarked Au process, Ag-alloy wire possesses great portability and wide first bond process window. Ag-alloy wire also demonstrates good bonding capability and loop shape control on challenging applications, such as overhang die and long die-to-die applications. However, further optimization of Ag-alloy process is still necessary to overcome its constrains, such as higher hardness and higher energy required during bonding of Ag-alloy wire.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131326958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028381
R. Litchfield, J. Graves, M. Sugden, D. Hutt, A. Cobley
Electroless copper plating of insulating substrates, such as printed circuit boards, typically requires the pre-deposition of a catalyst layer onto the surface to initiate the chemical reactions. Pd/Sn based catalysts are widely used, but carry a high cost and in many cases require specialist pre-treatment of the substrate to achieve good adhesion. In this work, functionalised copper nanoparticles have been investigated as alternative catalysts for electroless deposition. Commercially available copper nanoparticles were functionalised with different organic molecules and their functionalisation was confirmed with X-ray photoelectron spectroscopy. The ability of these particles to act as a catalyst was demonstrated, however their effectiveness was found to depend on the nature of the organic molecules that were used in the functionalisation. Furthermore, significant variability was found between batches of samples in both the particle dispersion and attachment to the substrate surface, which affected the reproducibility of the coverage and adhesion of the subsequent electroless plating, for which further work is required to understand these effects.
{"title":"Functionalised copper nanoparticles as catalysts for electroless plating","authors":"R. Litchfield, J. Graves, M. Sugden, D. Hutt, A. Cobley","doi":"10.1109/EPTC.2014.7028381","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028381","url":null,"abstract":"Electroless copper plating of insulating substrates, such as printed circuit boards, typically requires the pre-deposition of a catalyst layer onto the surface to initiate the chemical reactions. Pd/Sn based catalysts are widely used, but carry a high cost and in many cases require specialist pre-treatment of the substrate to achieve good adhesion. In this work, functionalised copper nanoparticles have been investigated as alternative catalysts for electroless deposition. Commercially available copper nanoparticles were functionalised with different organic molecules and their functionalisation was confirmed with X-ray photoelectron spectroscopy. The ability of these particles to act as a catalyst was demonstrated, however their effectiveness was found to depend on the nature of the organic molecules that were used in the functionalisation. Furthermore, significant variability was found between batches of samples in both the particle dispersion and attachment to the substrate surface, which affected the reproducibility of the coverage and adhesion of the subsequent electroless plating, for which further work is required to understand these effects.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133373330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028281
Tama Fouzder, Y. Chan, Daniel K. Chan
Nano-sized, non-reacting, non-coarsening CeO2 particles with a density close to that of solder alloy were incorporated into Sn-3.0wt%Ag-0.5wt%Cu solder paste. The interfacial microstructure and shear strength of Au/Ni metallized Cu substrates were investigated, as a function of aging time, at various temperatures. After solid state aging at low temperature, an island-shaped Cu6Sn5 intermetallic compound (IMC) layer was found to be adhered at the interfaces of the Cu/Sn-Ag-Cu solder systems. However, after a prolonged aging, a very thin, firmly adhering Cu3Sn IMC layer was observed between the Cu6Sn5 IMC layer and the Cu substrate. On the other hand, a scallop-shaped (Cu, Ni)-Sn IMC layer was found at the interfaces of the Sn-Ag-Cu based solder-Au/Ni metallized Cu substrates. As the solid-state aging time and temperature increase, the thicknesses of the IMC layers also remarkably increased. In the solder ball region of both systems, a fine microstructure of Ag3Sn and Cu6Sn5 IMC particles appeared in the β-Sn matrix. However, the growth behavior of the IMC layers of composite solders doped with CeO2 nanoparticles was inhibited, due to an accumulation of surface-active CeO2 nanoparticles at the grain boundary or in the IMC layers. In addition, the composite solder joints doped with CeO2 nanoparticles had higher shear strengths than that of the plain Sn-Ag-Cu solder joints, due to a well-controlled fine IMC particles and uniformly distributed CeO2 nanoparticles.
在Sn-3.0wt%Ag-0.5wt%Cu的锡膏中加入了密度接近焊料合金的纳米级、不反应、不粗化的CeO2颗粒。研究了不同温度下Au/Ni金属化Cu基体的界面微观结构和抗剪强度随时效时间的变化规律。经低温固相时效处理后，Cu/Sn-Ag-Cu钎料体系界面处形成了岛状Cu6Sn5金属间化合物(IMC)层。然而，经过长时间时效后，在Cu6Sn5 IMC层与Cu衬底之间形成了一层非常薄且粘附牢固的Cu3Sn IMC层。另一方面，在Sn-Ag-Cu基钎料- au /Ni金属化Cu衬底的界面上发现了扇形(Cu, Ni)-Sn IMC层。随着固态时效时间和温度的增加，IMC层的厚度也显著增加。在两种体系的钎料球区，β-Sn基体中均出现Ag3Sn和Cu6Sn5 IMC颗粒的微观结构。然而，由于表面活性的CeO2纳米颗粒在晶界或IMC层中积累，掺杂CeO2纳米颗粒的复合钎料的IMC层的生长行为受到抑制。此外，掺杂CeO2纳米粒子的复合焊点由于具有良好的IMC颗粒控制和CeO2纳米粒子的均匀分布，具有比普通Sn-Ag-Cu焊点更高的剪切强度。
{"title":"Interfacial microstructure and shear strength of Sn-Ag-Cu based composite solders on Cu and Au/Ni metallized Cu substrates","authors":"Tama Fouzder, Y. Chan, Daniel K. Chan","doi":"10.1109/EPTC.2014.7028281","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028281","url":null,"abstract":"Nano-sized, non-reacting, non-coarsening CeO2 particles with a density close to that of solder alloy were incorporated into Sn-3.0wt%Ag-0.5wt%Cu solder paste. The interfacial microstructure and shear strength of Au/Ni metallized Cu substrates were investigated, as a function of aging time, at various temperatures. After solid state aging at low temperature, an island-shaped Cu6Sn5 intermetallic compound (IMC) layer was found to be adhered at the interfaces of the Cu/Sn-Ag-Cu solder systems. However, after a prolonged aging, a very thin, firmly adhering Cu3Sn IMC layer was observed between the Cu6Sn5 IMC layer and the Cu substrate. On the other hand, a scallop-shaped (Cu, Ni)-Sn IMC layer was found at the interfaces of the Sn-Ag-Cu based solder-Au/Ni metallized Cu substrates. As the solid-state aging time and temperature increase, the thicknesses of the IMC layers also remarkably increased. In the solder ball region of both systems, a fine microstructure of Ag3Sn and Cu6Sn5 IMC particles appeared in the β-Sn matrix. However, the growth behavior of the IMC layers of composite solders doped with CeO2 nanoparticles was inhibited, due to an accumulation of surface-active CeO2 nanoparticles at the grain boundary or in the IMC layers. In addition, the composite solder joints doped with CeO2 nanoparticles had higher shear strengths than that of the plain Sn-Ag-Cu solder joints, due to a well-controlled fine IMC particles and uniformly distributed CeO2 nanoparticles.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028419
Bruce C. Kim, Saikat Mondal, Seok-Ho Noh
This paper describes the design and analysis of 3D through-silicon-via (TSV) inductors for integrated sensor applications. On-chip inductors are an integral part of small foot-print RF and analog chips. In an effort to further reduce foot-print, there have been numerous proposals of 3D TSV inductors. However, these inductors do not maintain higher quality factors due to the lossy silicon substrates through which the TSV must pass. We have designed and simulated a new structure to reduce losses through silicon substrates. Our novel structure tunes the inductors using TSV arrays for low-noise amplifiers. Through our simulation results, we were able to maintain a Q factor of approximately 5 on TSV-based inductors with excellent inductor values.
{"title":"Tunable 3D TSV-based inductor for integrated sensors","authors":"Bruce C. Kim, Saikat Mondal, Seok-Ho Noh","doi":"10.1109/EPTC.2014.7028419","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028419","url":null,"abstract":"This paper describes the design and analysis of 3D through-silicon-via (TSV) inductors for integrated sensor applications. On-chip inductors are an integral part of small foot-print RF and analog chips. In an effort to further reduce foot-print, there have been numerous proposals of 3D TSV inductors. However, these inductors do not maintain higher quality factors due to the lossy silicon substrates through which the TSV must pass. We have designed and simulated a new structure to reduce losses through silicon substrates. Our novel structure tunes the inductors using TSV arrays for low-noise amplifiers. Through our simulation results, we were able to maintain a Q factor of approximately 5 on TSV-based inductors with excellent inductor values.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"133 6‐8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028275
B. L. Lau, Yong Han, H. Zhang, L. Zhang, X. Zhang
In this paper, Gold-indium fluxless eutectic bonding at short process time has been successfully developed for stacking multi-layers and heterogeneous structure of silicon micro-cooler. This paper introduces gold-indium eutectic bonding process which uses deposited thin and multilayer composites directly onto the silicon surfaces which to be bonded. The parameters DOE (design of experiment) study was carried out to develop thermal compression bonding process conditions as tabulated in Table 1. These eutectic bonds are examined using shear test, Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDX). This shear test results is compared with eutectic AuSn which is best known as hard solders, good fatigue-resistance and mechanical properties. Nearly void-free bonds are achieved and confirmed by cross-sectional SEM and X-ray scanning. A pre-clean process steps is required to ensure sufficient wetting and good adhesion for this fluxless process. Furthermore, a thermal cycling test and Scanning Acoustic Microscope (SAM) analysis will be carried out to evaluate the failure mode, reliability of solder joint and the bonded structure.
{"title":"Development of fluxless bonding using deposited Gold-indium multi-layer composite for heterogeneous silicon micro-cooler stacking","authors":"B. L. Lau, Yong Han, H. Zhang, L. Zhang, X. Zhang","doi":"10.1109/EPTC.2014.7028275","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028275","url":null,"abstract":"In this paper, Gold-indium fluxless eutectic bonding at short process time has been successfully developed for stacking multi-layers and heterogeneous structure of silicon micro-cooler. This paper introduces gold-indium eutectic bonding process which uses deposited thin and multilayer composites directly onto the silicon surfaces which to be bonded. The parameters DOE (design of experiment) study was carried out to develop thermal compression bonding process conditions as tabulated in Table 1. These eutectic bonds are examined using shear test, Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDX). This shear test results is compared with eutectic AuSn which is best known as hard solders, good fatigue-resistance and mechanical properties. Nearly void-free bonds are achieved and confirmed by cross-sectional SEM and X-ray scanning. A pre-clean process steps is required to ensure sufficient wetting and good adhesion for this fluxless process. Furthermore, a thermal cycling test and Scanning Acoustic Microscope (SAM) analysis will be carried out to evaluate the failure mode, reliability of solder joint and the bonded structure.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128614026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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