Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313863
C. Enz, M. Chalkiadaki, A. Mangla
This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.
{"title":"Low-power analog/RF circuit design based on the inversion coefficient","authors":"C. Enz, M. Chalkiadaki, A. Mangla","doi":"10.1109/ESSCIRC.2015.7313863","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313863","url":null,"abstract":"This paper discusses the concept of the inversion coefficient as an essential design parameter that spans the entire range of operating points from weak via moderate to strong inversion, including velocity saturation. Several figures-of-merit based on the inversion coefficient, especially suitable for the design of low-power analog and RF circuits, are presented. These figures-of-merit incorporate the various trade-offs encountered in analog and RF circuit design. The use of the inversion coefficient and the derived figures-of-merit for optimization and design is demonstrated through simple examples. Finally, the simplicity of the inversion coefficient based analytical models is emphasized by their favorable comparison against measurements of a commercial 40-nm bulk CMOS process as well as with simulations using the BSIM6 model.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84289336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313817
S. Carrara
{"title":"New frontiers in digital health: Remote monitoring of animal and human metabolism on our smartphones and tablets","authors":"S. Carrara","doi":"10.1109/ESSCIRC.2015.7313817","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313817","url":null,"abstract":"","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75924630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313905
Luca Sant, A. Fant, S. Stojanovic, S. Fabbro, J. Ceballos
A system for measuring optical proximity based on reflection of modulated light is presented. Its novel input stage topology comprising an AC coupled TIA and a two stage DC rejection circuit based on a synthesized inductive impedance, provides readouts with a resolution better than 13.2 ENOB. This allows the sensor system to be used without modifications also for heart rate and blood oximetry monitoring.
{"title":"A 13.2b optical proximity sensor system with 130klx ambient light rejection capable of heart rate and blood oximetry monitoring","authors":"Luca Sant, A. Fant, S. Stojanovic, S. Fabbro, J. Ceballos","doi":"10.1109/ESSCIRC.2015.7313905","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313905","url":null,"abstract":"A system for measuring optical proximity based on reflection of modulated light is presented. Its novel input stage topology comprising an AC coupled TIA and a two stage DC rejection circuit based on a synthesized inductive impedance, provides readouts with a resolution better than 13.2 ENOB. This allows the sensor system to be used without modifications also for heart rate and blood oximetry monitoring.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75282177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a stacked power amplifier (PA) for X-band multifunctional chips using 0.13-μm SiGe HBTs. To achieve high output power, two 5-stacked PAs with optimum inter-stage matching networks are combined with Wilkinson power combiners. Furthermore, a 3-stacked amplifier is used as the driving amplifier to increase the gain of the whole PA. During on-chip measurements, the X-band stacked PA achieves peak output power of 890 mW and maximum power added efficiency (PAE) of 17.8 %. The chip area is 1.9 × 1.4 mm2 including the testing pads. To the authors' knowledge, our proposed PA achieves the highest output power at X-band with a silicon-based technology.
{"title":"An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips","authors":"Chao Liu, Qiang Li, Yihu Li, Xiang Li, Haitao Liu, Y. Xiong","doi":"10.1109/ESSCIRC.2015.7313830","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313830","url":null,"abstract":"This paper presents a stacked power amplifier (PA) for X-band multifunctional chips using 0.13-μm SiGe HBTs. To achieve high output power, two 5-stacked PAs with optimum inter-stage matching networks are combined with Wilkinson power combiners. Furthermore, a 3-stacked amplifier is used as the driving amplifier to increase the gain of the whole PA. During on-chip measurements, the X-band stacked PA achieves peak output power of 890 mW and maximum power added efficiency (PAE) of 17.8 %. The chip area is 1.9 × 1.4 mm2 including the testing pads. To the authors' knowledge, our proposed PA achieves the highest output power at X-band with a silicon-based technology.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80057650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313880
Z. Cai, R. V. Veldhoven, A. Falepin, H. Suy, E. Sterckx, K. Makinwa, M. Pertijs
This paper presents a readout circuit for thermal-conductivity-based resistive gas sensors. It digitizes the sensor's heat loss to its environment, which is a function of gas concentration, relative to that of a reference transducer, which is made of the same material and acts as a thermal-conductivity reference. Thus, dedicated voltage, power or temperature references are not needed. The ratiometric interface is based on a reconfigurable delta-sigma modulator that digitizes both the temperature and power ratio of the sensor and reference transducers, from which their thermal-conductivity ratio is calculated. It uses a dynamic baseline-resistance cancellation technique to relax the required dynamic range. In addition, dynamic element matching and 6-bit bias-current trimming are used to suppress errors due to transducer mismatch. The interface has been implemented in a standard 0.16 μm CMOS technology. Experimental results obtained in combination with CMOS-compatible tungsten-wire transducers show a CO2 resolution of 228 ppm (1σ), which is the highest resolution reported for thermal-conductivity-based CO2 sensors.
{"title":"A ratiometric readout circuit for thermal-conductivity-based resistive gas sensors","authors":"Z. Cai, R. V. Veldhoven, A. Falepin, H. Suy, E. Sterckx, K. Makinwa, M. Pertijs","doi":"10.1109/ESSCIRC.2015.7313880","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313880","url":null,"abstract":"This paper presents a readout circuit for thermal-conductivity-based resistive gas sensors. It digitizes the sensor's heat loss to its environment, which is a function of gas concentration, relative to that of a reference transducer, which is made of the same material and acts as a thermal-conductivity reference. Thus, dedicated voltage, power or temperature references are not needed. The ratiometric interface is based on a reconfigurable delta-sigma modulator that digitizes both the temperature and power ratio of the sensor and reference transducers, from which their thermal-conductivity ratio is calculated. It uses a dynamic baseline-resistance cancellation technique to relax the required dynamic range. In addition, dynamic element matching and 6-bit bias-current trimming are used to suppress errors due to transducer mismatch. The interface has been implemented in a standard 0.16 μm CMOS technology. Experimental results obtained in combination with CMOS-compatible tungsten-wire transducers show a CO2 resolution of 228 ppm (1σ), which is the highest resolution reported for thermal-conductivity-based CO2 sensors.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80997524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313814
J. Hansryd
In the last twenty years we have seen a revolution comparable to the industrialization. We have gone from voice, to data, to mobile broadband to a situation where half of the two-year olds in Sweden use internet. We have changed how we are creating and sharing knowledge, how we interact with family and friends, how we work and how we do business. We have seen traditional industries transform... music, media ... and how more and more industries are rapidly digitalizing and mobilizing - realizing the need for good ICT solutions where mobility is becoming not only an opportunity, but a necessity.
{"title":"5G wireless communication beyond 2020","authors":"J. Hansryd","doi":"10.1109/ESSCIRC.2015.7313814","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313814","url":null,"abstract":"In the last twenty years we have seen a revolution comparable to the industrialization. We have gone from voice, to data, to mobile broadband to a situation where half of the two-year olds in Sweden use internet. We have changed how we are creating and sharing knowledge, how we interact with family and friends, how we work and how we do business. We have seen traditional industries transform... music, media ... and how more and more industries are rapidly digitalizing and mobilizing - realizing the need for good ICT solutions where mobility is becoming not only an opportunity, but a necessity.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89806624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313910
Dmytro Cherniak, Michael Aichner, R. Nonis, N. D. Dalt
This paper presents a digitally controlled delay insertion unit (DIU) for precise dead-time insertion in DC-DC converters. A fundamental building block is the 100MHz relaxation oscillator with better than +/-1% frequency accuracy in the temperature range from -40C to +150C, which is introduced for the first time with such accuracy in this frequency range. The DIU is capable of up to 32ns delay generation with 500ps step size. It is implemented in 130nm CMOS, occupies 0.098mm2 and consumes 0.45mW in ultra-low power mode.
{"title":"Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters","authors":"Dmytro Cherniak, Michael Aichner, R. Nonis, N. D. Dalt","doi":"10.1109/ESSCIRC.2015.7313910","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313910","url":null,"abstract":"This paper presents a digitally controlled delay insertion unit (DIU) for precise dead-time insertion in DC-DC converters. A fundamental building block is the 100MHz relaxation oscillator with better than +/-1% frequency accuracy in the temperature range from -40C to +150C, which is introduced for the first time with such accuracy in this frequency range. The DIU is capable of up to 32ns delay generation with 500ps step size. It is implemented in 130nm CMOS, occupies 0.098mm2 and consumes 0.45mW in ultra-low power mode.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82206617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-02DOI: 10.1109/ESSCIRC.2015.7313906
M. B. Dayanik, Nicholas Collins, M. Flynn
This paper presents a 65nm CMOS 28.5GHz-to-33.5GHz mostly digital fractional-N PLL based on a new 3rd order noise-shaping continuous time delta sigma time-to-digital converter (TDC). With a measured time resolution of 176fs, the TDC has the finest measured time resolution in a 1MHz bandwidth of any published TDC, to the best knowledge of the authors. The PLL achieves a normalized phase noise of -213dBc/Hz2 (at a 100kHz offset) and FoMJitter of -230dB (from 10kHz-to-1MHz). Both the normalized phase noise and FoMJitter are 5dB better than for any published digital integer or digital fractional-N high frequency (>20GHz) PLL.
{"title":"A 28.5–33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution","authors":"M. B. Dayanik, Nicholas Collins, M. Flynn","doi":"10.1109/ESSCIRC.2015.7313906","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313906","url":null,"abstract":"This paper presents a 65nm CMOS 28.5GHz-to-33.5GHz mostly digital fractional-N PLL based on a new 3rd order noise-shaping continuous time delta sigma time-to-digital converter (TDC). With a measured time resolution of 176fs, the TDC has the finest measured time resolution in a 1MHz bandwidth of any published TDC, to the best knowledge of the authors. The PLL achieves a normalized phase noise of -213dBc/Hz2 (at a 100kHz offset) and FoMJitter of -230dB (from 10kHz-to-1MHz). Both the normalized phase noise and FoMJitter are 5dB better than for any published digital integer or digital fractional-N high frequency (>20GHz) PLL.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88803757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-30DOI: 10.1109/ESSCIRC.2015.7313885
T. Tikka, K. Stadius, J. Ryynanen, M. Kaltiokallio
This paper describes a wide-band receiver designed to be connected directly to a single-ended non-50 ohm antenna. The receiver is based on a four-phase mixer-first architecture and it includes an on-chip transformer balun. Reconfigurability in the balun extends the low-end operation band by 300 MHz. This design demonstrates that with an on-chip balun it is possible to achieve comparable performance to a similar receiver with an external high-performance balun. The receiver is implemented in 65-nm CMOS and it operates in 0.8-3 GHz band with 40 dB gain and 7 dB noise figure.
{"title":"European Solid-State Circuits Conference","authors":"T. Tikka, K. Stadius, J. Ryynanen, M. Kaltiokallio","doi":"10.1109/ESSCIRC.2015.7313885","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313885","url":null,"abstract":"This paper describes a wide-band receiver designed to be connected directly to a single-ended non-50 ohm antenna. The receiver is based on a four-phase mixer-first architecture and it includes an on-chip transformer balun. Reconfigurability in the balun extends the low-end operation band by 300 MHz. This design demonstrates that with an on-chip balun it is possible to achieve comparable performance to a similar receiver with an external high-performance balun. The receiver is implemented in 65-nm CMOS and it operates in 0.8-3 GHz band with 40 dB gain and 7 dB noise figure.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74779163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-30DOI: 10.1109/ESSCIRC.2015.7313893
Koki Tanaka, R. Saito, H. Ishikuro
A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. “Memory effect” caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.
{"title":"A 1.6 GS/s 3.17 mW 6-b passive pipelined binary-search ADC with memory effect canceller and reference voltage calibration","authors":"Koki Tanaka, R. Saito, H. Ishikuro","doi":"10.1109/ESSCIRC.2015.7313893","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2015.7313893","url":null,"abstract":"A 6-bit high-speed and low-power pipelined binary-search ADC is presented. Over GHz conversion rate is achieved by passive pipeline operation without amplifier. “Memory effect” caused by charge sharing in the passive pipeline operation is cancelled by charge reset and flatness of frequency response of the converter is improved. Memory effect canceller also makes it easy to calibrate reference voltage to each comparator and to enhance SNDR. The prototype ADC fabricated in 40nm-CMOS achieved 29.21 dB SNDR with 1.6 GS/s at supply voltage of 0.9 V. The ADC achieved a FoM of 84.1 fJ/conv.step.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79505378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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